b.

Optimized technology dependent netlist

c. Unoptimized technology independent netlist
d. Unoptimized technology dependent netlist

Reg. No.
SRM UNIVERSITY
10.

VADAPALANI CAMPUS

Cycle based simulation displays values at

a.all nodes b.Certain nodes c.only at boundaries

d.inputs

MODEL EXAMINATION OCT 2016

Seventh Semester Electronics and Communication Engineering

11.

Which encoding technique uses minimum logic difference in the state

transition
a.Adjacent
b.Moore
c.One hot d.Random

12.

Elaboration step is also known as

a. Translation b. Logic Mapping c. Optimization d.Timing

13.

In D algorithm D stands for

a.Discrepancy b.Detected

EC1115 ASIC DESIGN

Duration: 3 Hrs

Max. Marks: 100

PART A (20 X 1 = 20 Marks)
Answer ALL Questions

1.

2.

Which design style has the longest manufacturing lead time

a.Full custom b. Standard Cell c. Gate array d. FPGA
AOI22 CMOS logic cell has how many transistor
a. 10
b.12
c.14
d.8

14.

LFSR is used as
a.Pattern generator

The term h in measurement of delay is known as

a.Logical effort b.Electrical effort c.Stage effort d.Guard effect

5.

6.

b.BIST

c. IDDQ

d.PODEM

b.01

c.10

d.11

Which acts as a pull up device in CMOS logic

a.NMOS
b.PMOS
c.Both
d.neither of them

17.

ACTEL antifuse is designed using

a.ONO
b.FAMOS
c.SRAM

18. Power dissipation due to charging and discharging of Load capacitance

d.MIM

EPROM is built using which technology

a.ONO
b. MIM
c. FAMOS
Size of LUT in XC5200 is
a.16 bit
b.32 bit

c.4 bit

KL algorithm is based on which partitioning algorithm

a.Constructive b. Iterative
c.Simulated d.Boundary
is called
a.Dynamic

b.Short circuit

c.Static

d.Switching

d.SRAM
19.

7.

c.shift resister d.binary counter

16. Test Vector for SA0 at the output of a AND gate is

a.00
4.

b.comparator

d.Dominant

15. Which method is commonly used for testing CMOS based circuits

a.Boundary Scan
3.

c.Dynamic

Which physical design step decides the placement of Fixed blocks

a.Floorplan
b.Partitioning c. routing
d.Placement

d.8bit
20. Which Physical design step decides the location of power/IO pads

8.

9.

No. of inputs to the Flex LE

a.5
b.4
c.3

a.Routing
d.2

Logic synthesis step converts RTL to

a.Optimized technology independent netlist

b.Partitioning

c.Placement d.Floorplan

PART B (5 X 4 = 20 Marks)
Answer ANY FIVE questions

b. With an example explain left edge channel routing algorithm

21. List out the information contained in an ASIC cell library

22. Design an OAI221 cell and size it to achieve equal rise and fall time

23. Explain antifuse programming technology used in ACT logic

24. How Synchronous clock and reset are modeled in a sequential design

A
B

25. Draw a Boundary scan cell

26. Design an LFSR for the polynomial equation

Y=1+X+X3

C
Figure1

27. Explain the goals and objectives of Placement

PART C (5 X 12 = 60 Marks)
Answer ALL questions
28. a. Calculate the delay of 3 input NOR gate driving 5 other NOR gates

using logical effort.

(OR)
b. Compare Full custom ASIC design style with Semicustom ASIC style
29.

a. Draw and explain the features of XILINX XC3000 architecture

(OR)
b. Implement the logic function Y=AB+ (BC)+D in ACT1 logic module
and also draw the architecture of ACT2 logic module

30. a. Write a Synthesizable mealy FSM model in VHDL

(OR)
b. Explain various types of Logic simulators
31. a. Determine the Test vector for SA0 fault shown below in figure1 using D
algorithm

(OR)
b. What is BIST? Explain the various components associated with it.
32. a. Apply KL algorithm for figure2 and find the minimum cut cost

(OR)

Figure2