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LMP7300
SNOSAT7G AUGUST 2007 REVISED OCTOBER 2015
3 Description
2 Applications
Device Information(1)
PART NUMBER
LMP7300
PACKAGE
VSSOP (8)
3.00 mm 3.00 mm
SOIC (8)
3.91 mm 4.90 mm
Typical Application
VBATT = (TRIP @ .9V x 3 CELL)
R1
318.4 k:
1%
R2
1 M:
1%
INP
INN
HYSTP
HYSTN
LED
+
-
GND
OUT
VREF
R3
9.86 k:
1%
R4
1 M:
1%
R5 ADJUST
FOR LED
BRIGHTNESS
V = 12V
0.1 PF
CL = 10 pF
25
20
15
10
-40C
25C
85C
5
0
0
125C
20
40
60
80
100
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMP7300
SNOSAT7G AUGUST 2007 REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
6
7
8
Device Support......................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (March 2013) to Revision G
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Page
Page
LMP7300
www.ti.com
-IN
GND
OUT
REF
HYSTP
HYSTN
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
+IN
Noninverting Comparator Input. The +IN has a common-mode voltage range from 1 V above
the negative rail to, and including, the positive rail. Internal ESD diodes, connected from the
+IN pin to the rails, protect the input stage from overvoltage. If the input voltage exceeds the
rails, the diodes turn on and clamp the input to a safe level.
-IN
Inverting Comparator Input. The IN has a common-mode voltage range from 1 V above the
negative rail to, and including, the positive rail. Internal ESD diodes, connected from the IN
pin to the rails, protects the input stage from overvoltage. If the input voltage exceeds the
rails, the diodes turn on and clamp the input to a safe level.
GND
Ground. This pin may be connected to a negative DC voltage source for applications
requiring a dual supply. If connected to a negative supply, decouple this pin with 0.1-F
ceramic capacitor to ground. The internal reference output voltage is referenced to this pin.
GND is the die substrate connection.
OUT
Comparator Output. The output is an open-collector. It can drive voltage loads by using a
pullup resistor, or it can drive current loads by sinking a maximum output current. This pin
may be taken to a maximum of +12 V with respect to the ground pin, irrespective of supply
voltage.
HYSTN
Negative Hysteresis pin. This pin sets the lower trip voltage VIL. The common mode range is
from 1V above the negative rail to VCC. The input signal must fall below VIL for the
comparator to switch from high to low state.
HYSTP
Positive Hysteresis pin. This pin sets the upper trip voltage VIH. The common mode range is
from 1V above the negative rail to VCC. The input signal must rise above VIH for the
comparator to switch from low to high state.
REF
Reference Voltage Output pin. This is the output pin of a 2.048-V band gap precision
reference.
V+
Positive Supply Terminal. The supply voltage range is 2.7 V to 12 V. Decouple this pin with
0.1-F ceramic capacitor to ground.
(1)
LMP7300
SNOSAT7G AUGUST 2007 REVISED OCTOBER 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
VS
13.6
VIN differential
+
V 0.3
235
260
150
150
V+ + 0.3
65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The maximum power dissipation is a function of TJ(MAX), JA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) TA)/ JA. All numbers apply for packages soldered directly onto a PC Board.
V(ESD)
(1)
(2)
Electrostatic discharge
2000
250
Machine model
200
UNIT
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
MAX
UNIT
40
125
2.7
12
NOM
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Tables.
The maximum power dissipation is a function of TJ(MAX), JA. The maximum allowable power dissipation at any ambient temperature
is PD = (TJ(MAX) TA)/JA. All numbers apply for packages soldered directly onto a PC Board.
DGK (VSSOP)
D (SOIC)
UNIT
8 PINS
8 PINS
RJA
175.5
121.2
C/W
RJC(top)
66.1
67.5
C/W
RJB
95.6
61.5
C/W
JT
10
18.3
C/W
JB
94.2
61
C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953..
The maximum power dissipation is a function of TJ(MAX), JA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) TA)/ JA. All numbers apply for packages soldered directly onto a PC Board.
LMP7300
www.ti.com
Supply Current
TEST CONDITIONS
MIN
TA = 25C
RPULLUP = Open
TYP
MAX
12
TJ = TA
17
UNIT
A
COMPARATOR
VCM = V+/2 SOIC
VOS
TA = 25C
0.07
TJ = TA
0.75
2
TA = 25C
0.07
TJ = TA
1
2.2
mV
mV
TCVOS
See (1)
IB
IOS
CMRR
Common Mode
Rejection Ratio
80
100
dB
PSRR
80
100
dB
VOL
ILOAD = 10 mA
ILEAK
Output Leakage
Current
HCLIN
Hysteresis Control
Voltage Linearity
IHYS
Hysteresis Leakage
Current
TA = 25C
TPD
Propagation Delay
(High to Low)
Overdrive = 10 mV, CL = 10 pF
12
17
4.5
7.6
V/C
1.8
TA = 25C
1.2
TJ = TA
3
4
0.15
TA = 25C
0.25
TJ = TA
0.5
0.4
0.5
1.2
mV/V
0.950
TJ = TA
nA
pA
nA
3
4
nA
s
REFERENCE
VO
Reference Voltage
Line Regulation
SOIC
2.043
2.048
2.053
VSSOP
2.043
2.048
2.056
14
80
0.2
mV/m
0.5
A
VCC = 2.7 V to 12 V
Load Regulation
IOUT = 0 to 1 mA
Temperature
Coefficient
40C to 125C
VN
TCVREF/
(1)
(2)
55
V/V
ppm/
C
0.1 Hz to 10 Hz
80
VPP
10 Hz to 10 kHz
100
VRMS
Offset voltage average drift determined by dividing the change in VOS at temperature extremes, by the total temperature change.
Positive current corresponds to current flowing into the device.
LMP7300
SNOSAT7G AUGUST 2007 REVISED OCTOBER 2015
www.ti.com
Supply Current
TEST CONDITIONS
RPULLUP = Open
MIN (2)
TA = 25C
TYP (3)
MAX (2)
10
13
TJ = TA
18
UNIT
A
COMPARATOR
VOS
VCM = V+/2
SOIC
VCM = V+/2
VSSOP
TA = 25C
0.07
TJ = TA
0.75
2
TA = 25C
0.07
TJ = TA
1
2.2
mV
mV
TCVOS
See (4)
IB
IOS
CMRR
1 VCM 5 V
80
100
dB
PSRR
V+ = 2.7 V to 12 V
80
100
dB
VOL
ILOAD = 10 mA
ILEAK
HCLIN
IHYS
Hysteresis Leakage
Current
TA = 25C
TPD
Propagation Delay
(High to Low)
Overdrive = 10 mV, CL = 10 pF
12
15
V/C
1.8
TA = 25C
1.2
TJ = TA
3
4
0.15
0.25
0.5
0.4
mV/V
0.950
1.2
nA
pA
TJ = TA
nA
3
4
nA
s
REFERENCE
VO
Reference Voltage
TCVREF/
SOIC
2.043
2.048
2.053
VSSOP
2.043
2.048
2.056
Line Regulation
VCC = 2.7 V to 12 V
14
80
Load Regulation
IOUT = 0 to 1 mA
0.2
0.5 mV/mA
Temperature Coefficient
40C to 125C
V/V
55 ppm/C
VN
(1)
(2)
(3)
(4)
(5)
0.1 Hz to 10 Hz
80
VPP
10 Hz to 10 kHz
100
VRMS
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA.
Limits are 100% production tested at 25C. Limits over the operating temperature range are specified through correlations using
statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Offset voltage average drift determined by dividing the change in VOS at temperature extremes, by the total temperature change.
Positive current corresponds to current flowing into the device.
LMP7300
www.ti.com
Supply Current
TEST CONDITIONS
RPULLUP = Open
MIN
TA = 25C
TYP
MAX
11
14
TJ = TA
20
UNIT
A
COMPARATOR
VCM = V+/2 SOIC
VOS
TA = 25C
0.08
TJ = TA
0.75
2
TA = 25C
0.08
TJ = TA
1
2.2
TCVOS
See (2)
IB
IOS
CMRR
1 V VCM 12 V
80
100
PSRR
V+ = 2.7 V to 12 V
80
100
VOL
ILOAD = 10 mA
ILEAK
HCLIN
IHYS
TPD
Propagation Delay
(High to Low)
1.2
TJ = TA
3
4
0.15
0.25
0.5
dB
TJ = TA
V
pA
1
1.2
nA
0.4
mV/V
0.95
TA = 25C
nA
dB
mV
V/C
1.8
TA = 25C
mV
3
4
Overdrive = 10 mV, CL = 10 pF
11
15
3.5
6.8
nA
s
REFERENCE
VO
Reference Voltage
TCVREF/
TJ = 25C
SOIC
2.043
2.048
2.053
TJ = 25C
VSSOP
2.043
2.048
2.056
(1)
(2)
(3)
Line Regulation
VCC = 2.7 V to 12 V
14
80
V/V
Load Regulation
IOUT = 0 to 1 mA
0.2
0.5
mV/m
A
Temperature Coefficient
40C to 125C
55
ppm/
C
VN
0.1 Hz to 10 Hz
80
VPP
10 Hz to 10 kHz
100
VRMS
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA.
Offset voltage average drift determined by dividing the change in VOS at temperature extremes, by the total temperature change.
Positive current corresponds to current flowing into the device.
LMP7300
SNOSAT7G AUGUST 2007 REVISED OCTOBER 2015
www.ti.com
0.5
+
V = 12V
125C
15
85C
25C
10
-40C
5
10
0.4
125C
0.3
85C
0.2
-40C
0.1
25C
0
0
12
10
V = 2.7V
0.4
125C
0.3
85C
0.2
-40C
0.1
25C
0.4
125C
0.3
85C
0.2
-40C
0.1
25C
0
0
10
10
2.052
2.050
+
VREF UNLOADED
V = 12V
2.050
0.5
+
V = 5V
-40C
25C
2.048
85C
125C
2.046
2.044
2
10
12
-40C
25C
2.049
2.048
85C
2.047
125C
2.046
0
0.5
1.5
0.5
LMP7300
www.ti.com
2.050
V = 2.7V
-40C
25C
2.049
V = 2.7V
2.048
85C
2.047
125C
2.049
-40C
25C
2.048
85C
2.047
125C
2.046
0
50
100
150
200
2.046
250
0.5
1.5
30
V = 5V
25
20
15
-40C
25C
85C
5
0
25
V = 2.7V
10
20
15
10
-40C
20
40
60
80
25C
85C
125C
0
100
125C
20
40
60
80
100
30
V = 12V
CL = 10 pF
25
20
15
10
-40C
25C
85C
5
0
0
125C
20
40
60
80
100
LMP7300
SNOSAT7G AUGUST 2007 REVISED OCTOBER 2015
www.ti.com
7 Detailed Description
7.1 Overview
The LMP7300 device is a unique combination of micropower and precision. The open collector comparator has
low offset, high CMRR, high PSRR, programmable hysteresis and microamp supply current. The precision 2.048V reference provides a DAC or ADC with an accurate binary divisible voltage. The comparator and reference
combination forms an ideal single IC solution for low power sensor or portable applications.
INP
+
OUT
INN
HYSTP
GND
V+
2.048 V
VREF
HYSTN
GND
10
LMP7300
www.ti.com
R1 + R2
R1
VIH = VREF + VREF
R1 + R2
(1)
+
INP
+
-
VIN
INN
RPULLUP
1 M:
OUT
HYSTP
HYSTN
VREF
RP1
1.47 k:
1%
RP2
1 M:
1%
GND
2.048V
RN1
4.91 k:
1%
RN2
1 M:
1%
GND
11
LMP7300
SNOSAT7G AUGUST 2007 REVISED OCTOBER 2015
www.ti.com
OUTPUT
STATE
-10 mV
+3 mV
VIN
0
VIL
VIH
VREF
VIH = VREF +3 mV
INP
+
-
VIN
INN
RPULLUP
1 M:
OUT
HYSTP
HYSTN
VREF
GND V+
2.048V
GND
OUTPUT
STATE
VIN
VREF
12
LMP7300
www.ti.com
INP
+
-
VIN
RPULLUP
1 M:
OUT
INN
HYSTP
GND
HYSTN
VREF
2.048V
R1
2.45 k:
1%
R2
1 M:
1%
GND
OUTPUT
STATE
10 mV
0
VIN
VIL
VREF
VIH
INP
+
-
VIN
INN
RPULLUP
1 M:
OUT
HYSTP
HYSTN
VREF
GND
2.048V
RN1
4.91 k:
1%
RN2
1 M:
1%
GND
13
LMP7300
SNOSAT7G AUGUST 2007 REVISED OCTOBER 2015
www.ti.com
OUTPUT
STATE
VIN
VREF
VIL
INP
+
-
VIN
RPULLUP
1 M:
OUT
INN
HYSTP
GND
HYSTN
VREF
2.048V
RP1
4.91 k:
1%
GND
RP2
1 M:
1%
OUTPUT
STATE
VIN
VREF
VIH
14
LMP7300
www.ti.com
POSITIVE
TRIP POINTS
VOUT
VIH
VHYSTP
VTH
VHYSTN
VIL
HYSTERESIS
(DEAD) BAND
GND
TIME
VIN
NEGATIVE
TRIP POINTS
EXAMPLE 1
EXAMPLE 2
Figure 22. Output Response With Input Noise Less than Hysteresis Band
7.3.3.1 How Much Hysteresis Is Correct?
An effective way of determining the minimum hysteresis necessary for clean switching is to decrease the amount
of hysteresis until false triggering is observed, and then use a multiple of say three times that amount of
hysteresis in the final circuit. This is most easily accomplished in the breadboard phase by making R1 and R2
potentiometers. For applications near or above 100C, TI recommends a minimum of 5-mV hysteresis due to
peaking of the LMP7300 noise sensitivity at high temperatures.
15
LMP7300
SNOSAT7G AUGUST 2007 REVISED OCTOBER 2015
www.ti.com
0.1 PF
R2
19.6 k:
1%
1 M:
INP
INN
HYSTP
+
-
VHIGH
TEMPERATURE
FAULT
OUT
HYSTN C1
LMP7300
VREF
2.32 k:
1%
R3
15.4 k:
1%
* NTC Thermistor
Such as: OMEGA #44008
30 k: @ 25C
19.74 k: @ 35C
46.67 k: @ 15C
205 k:
1%
0.1 PF
+
INP
R1
61.9 k:
1%
R4
46.4 k:
1%
1 M:
INN
HYSTP
HYSTN C2
OUT
VLOW
TEMPERATUE
FAULT
LMP7300
VREF
2.32 k:
1%
205 k:
1%
16
LMP7300
www.ti.com
17
LMP7300
SNOSAT7G AUGUST 2007 REVISED OCTOBER 2015
www.ti.com
RADJ
3.24 k:
0.1 PF
VREF
RSET
78.7 k:
C1
6.8 PF
RSET
78.7 k:
RH1
1.44 k:
+
-
1 M:
VCC
LMP7300
HYSTN
HYSTP
GND
RH2
205 k:
18
LMP7300
www.ti.com
R2
1 M:
1%
so, if
INP
INN
HYSTP
HYSTN
LED
+
-
GND
OUT
VREF
VBATT
R2
R1 + R2
d VREF,
= D and R2 is known,
R1
318.4 k:
1%
R5
0.1 PF
VBATT - VREF
1 - D
= R2
then, R1 = R2 D
VREF
VREF
As an example:
R3
9.86 k:
1%
R4
1 M:
1%
19
LMP7300
SNOSAT7G AUGUST 2007 REVISED OCTOBER 2015
www.ti.com
10 Layout
10.1 Layout Guidelines
A good PCB layout is always important to reduce output to input coupling. Positive feedback noise reduces
performance. For the LMP7300, output coupling is minimized by the unique package pinout. The output is kept
away from the noninverting and inverting inputs, the reference and the hysteresis pins.
TP1
R1
1 M:
VIN
BNC
VCC
VOH
JP2
+
-
J4
JP3
JP4
HYSTP
HYSTN
J2
VREF
TP4
HYSTN
TP3
R8
OPEN
C4
0.1 PF
VCC
VCC
OUT
BNC
TP5
VOH
VOH
J5
LMP7300
HYSTP
TP2
R9
1 M:
GND
R3
OPEN
C2
OPEN
5 PF
C1
0.1 PF
VCC
JP1
R4
50 k:
VREF
R2
1 M:
R6
50 k:
R7
50 k:
R5
1 M:
R10
1 M:
CREF
OPEN
J6
GND
JP5
JP6
J1
VEE
VEE
VEE
C6
OPEN
5 PF
20
LMP7300
www.ti.com
21
LMP7300
SNOSAT7G AUGUST 2007 REVISED OCTOBER 2015
www.ti.com
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
22
www.ti.com
30-Jul-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
LMP7300MA/NOPB
ACTIVE
SOIC
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP73
00MA
LMP7300MAX/NOPB
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP73
00MA
LMP7300MM/NOPB
ACTIVE
VSSOP
DGK
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
C31A
LMP7300MME/NOPB
ACTIVE
VSSOP
DGK
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
C31A
LMP7300MMX/NOPB
ACTIVE
VSSOP
DGK
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
C31A
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
www.ti.com
30-Jul-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
3-Aug-2015
Device
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMP7300MAX/NOPB
SOIC
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMP7300MM/NOPB
VSSOP
DGK
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMP7300MME/NOPB
VSSOP
DGK
250
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMP7300MMX/NOPB
VSSOP
DGK
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
3-Aug-2015
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMP7300MAX/NOPB
SOIC
2500
367.0
367.0
35.0
LMP7300MM/NOPB
VSSOP
DGK
1000
210.0
185.0
35.0
LMP7300MME/NOPB
VSSOP
DGK
250
210.0
185.0
35.0
LMP7300MMX/NOPB
VSSOP
DGK
3500
367.0
367.0
35.0
Pack Materials-Page 2
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