Faculty of Arts, Computing, Engineering and Sciences

ASSESSMENT
DESIGN MICROPROCESSORS 32 BIT USED VHDL LANGUAGE

STUDENT NAME: PHAM NGOC TUNG

ID: 25002216
SUPERVISOR: DR J ROWE

MSc of Telecommunication and Electronic Engineering.

2015/2016

DESIGN MICROPROCESSORS 32 BIT USED VHDL LANGUAGE

1. Simulation Architecture processors

CU (Control Unit)
+ Receive instruction from memory
+Decrypt command and control signals to execute the command
+ Receive signals from external request to treat and meet the signal requirements

ALU (Arithmetic and Logic Unit)

+ Perform arithmetic calculations and logic

Register Set
+ They are the special memory cells located inside the processor used to store data
temporarily to help the operation of memory
Divided into the following groups
+ Register address (MAR): Used to contain the address of the memory or gateway in-out
+ Data Registers: Used for temporary data or intermediate results
+ Instruction registers (IR): Used to contain the commands are implemented
+ Register flags (Flag Register): Use to store the state of operations
+ Multi-function Register: perform many different functions depending on the
requirements of programmers

Architectural design of 32-bit processors with 4 blocks: the ALU (Arithmetic Logic Unit),
PCIMem (program counter and memory), RFcache (register file and cache), Cntrpipe (control
pipeline)

Figure 1.1: The parameters of operating frequency

Simulation system diagram:

Figure 1.2: simulation system diagram

Clock_50: clock for the performance of the CPU load code into RAM and loaded into the cache
value 210.08 MHz frequency, cycle: 4.760 ns.
Clock KEY (2): The pulse clock for operation of the CPU (the frequency is 33.94 MHz, the
cycle is 29.460 ns)
To perform the test design should be implemented with the following requirements:
Load code into RAM CPU: Code program loaded into ROM_code and loaded into the RAM of
the CPU through the code_loader.
Loaded into the cache: The value will be loaded into the cache was stored in the table ROM and
will be loaded into the cache through cache_loader.

Creating the clock: we have two clock signals. One used to enable the operation of the loader:
CLOCK_50. One refers to the operation of the CPU: KEY (2). In order to avoid miscalculation,
the speed of the CPU clocks at smaller levels the speed of the clock for the cache loader.
This means ensuring the full load data before the CPU performs the operation.
Results are shown through 8 leds - 7 segments.
2. Implementation of the test operation
Checking the operation of the processor is the final step, whether the processor is operating
correctly according to the will of the designer; perform the following operation
here to check the operation of a microprocessor.
2.1 Performs a plus: R1 + R2 R3
Performs plus two hexadecimal values between registers R1 and R2 and stored in the registers
R3, valuation should calculate loaded in ROM, then from ROM loaded into Cache to do the
calculation.
Perform plus: 00716 + 08316 = 0816

Figure 2.1: The results displayed on kit DE2

2.2 Subtraction
Perform subtraction two hexadecimal values between registers R1 and R2 and stored in the
registers R3, determine the value should calculate loaded into ROM, then from ROM loaded into
Cache to do the calculation.
Perform plus: F009877816 + E008865616 = 1001012216

Figure 2.2: The results displayed on kit DE2

2.3 Arithmetic left shift
Performs a left shift data 2 bits in the register R1 and store in register R3: R3 R1 << 2, shift
left the value: 1240032116 2 = 49000C8416

Figure 2.3: The results displayed on kit DE2

2.4 Arithmetic right shift
Performs a right shift data 2 bits in the register R1 and store in register R3: R3 R1 >> 2, shift
right the value: 0001111116 2 = 0000444416

Figure 2.4: The results displayed on kit DE2

2.5 Operands AND

Performs AND two hexadecimal values between registers R1 and R2 and stored in registers R3
Perform AND: 0000FC8F16 + 0000E0F016 = 0000E08016

Figure 2.5: The results displayed on kit DE2

2.6 Performs OR
Performs OR two hexadecimal values between R1 and R2 register and stored in the register R3
Perform OR: 0000FC8E16 + 0000E0F016 = 0000FCFE16

Figure 2.6: The results displayed on kit DE2

2.7 Operands XOR
Perform XOR two values from the registers R1 and R2 and store the value in the register R3.
Perform XOR: 0000123416 + 0000567816 = 0000444C16

Figure 2.7: The results displayed on kit DE2

2.8 Multiplication
Perform multiplication of two values from the registers R1 and R2 and store the value in
registers R3. 3 1 2
Perform multiplication: 00000046160000002316 + 0000000216 = 0000004616

Figure 2.8: The results displayed on kit DE2

3. Conclusions and future
In conclusion, I have designed 32 bit microprocessor successfully by using VHDL
programming language. It includes Simulation function blocks such as: Pcimem (Program
Counter and memory), Cntrpipe (Control pipeline), Rfcache (register file and cache), and ALU
(Arithmetic Logic Unit). Perform calculations on microprocessor by simulation waveforms and
perform on circuits DE2. Moreover, the control pipeline has 4 floors through 4 phases: (IInstruction), (R-Read), (E-Execute), (W-Write) to improve the operation of the processor
physical. However, the assessment is still limited. The speed of the microprocessor is designed
not fast, depending on the clock inlet. Although the program described the basic calculations,
there are still some other functions which must be implemented.