SRAM Array

Prof. Mitesh Limachia

SRAM Array
6T-Cells => replicated to create an SRAM array.

Highest storage density, short access time

SRAM=> N storage location, each location=> n-bit word
Dn-1.D1 D0
Size of SRAM=> N x n.
Each location=> m-bit address word (Am-1 Am-2 A1 A0)
i.e n=8, N=1024 , m=?
Prof. Mitesh Limachia

0th location (row)

N-1 location (row)

Prof. Mitesh Limachia

2m

Prof. Mitesh Limachia

Contd.
Two control signals
En=> Chip Select (CS) or Chip Enable (CE)

En=> 0 => activate read/write operations => WL=1

En=>1=> Memory in a hold state => WL=0
WE=>0=> write operation, WE=>1=> read operation.

Prof. Mitesh Limachia

Contd.
High density=> Dual core regions of storage cell=> shared
central WL (common)
Word Lines (WL)=> horizontally
Bit & Bit_bar lines (I/O lines)=> vertically
i.e 8-bit is word, each core => width of k x 8 where k is
number of words in row.
Width of core=> multiple of word data in each row.

Prof. Mitesh Limachia

Prof. Mitesh Limachia

Contd.
i.e 128K x 8 SRAM=> 17-bit address word (A16 to A0).
Single core, one Word/ one Row Word lines (WL)= ?
Dual core, one Word/one Row (word line)
Word lines (WL)= ?
16-bit address A15A0=> One row (WL)
1-bit address A16 => Word => Column address

Prof. Mitesh Limachia

Contd.
Each row=> 8 words => Number of word lines (WL) is
reduced to 8K.

13-bit Row address

(Row decoder)

A12A0=>

One

row

(WL)

4-bit Column address A16.A13=> select one word of a row

(Column decoder)

Prof. Mitesh Limachia

Prof. Mitesh Limachia

10

Contd.
O/P of Row decoder provides particular WL signals to
storage cells. (by one WL=> Number of Transistors ?)
Read/Write operations=> All transistors=> WL are turned on
O/P of row decoder=> used for left/right cores.
Row decoder O/P=> Row driver circuits=> WL signals to
storage cells.

Prof. Mitesh Limachia

11

Prof. Mitesh Limachia

12

Row Driver Circuit

Prof. Mitesh Limachia

13

Contd.
Row drivers=> drive large capacitive load presents by long
interconnects and number of access transistors are connected
to that line.
En=> 0 => read/write operation=> WL=1
En=1=> Hold state=> WL=0

Prof. Mitesh Limachia

14

Column Decoder Circuit

Choose a particular word from row=> Column decoder
required.
Each MUX/DEMUX=> connected to appropriate data line of
each word.
i.e bit_0 and bit_bar_0 lines => every word=> Bit_0
MUX/DeMUX block.

Read operation=> O/P from the cells => Circuits => MUX
Write operation => i/p to cells => Circuits => DEMUX

Prof. Mitesh Limachia

15

Contd.

Prof. Mitesh Limachia

16

in3
in2
in1
in0

WE
Write Circuit
BL0
pre_clk

BL0'

Precharge

Write Circuit
BL1

BL1'

Write Circuit
BL2

BL2'

Write Circuit
BL3

BL3'

Precharge

Precharge

Precharge

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

Vdd0

drowsy0

cell
WL0
Vdd1

drowsy1

cell
WL1
Vdd2

drowsy2

cell
WL2
Vdd3

drowsy3

cell
WL3
Vdd
Vdrowsy
(1.8v) (0.36v)

Sense Amp.

Sense Amp.

Sense Amp.

Sense Amp.

Read

dec_clk
a0
a1

2 to 4
Address
decoder

Prof. Mitesh Limachia

out0

out1

17
out2

out3