Experiment No.

2
Combinational Circuits
Course Code: CPE 402
Program: BSCPE
Course Title: Advanced Logic Circuit
Date Performed: Dec. 6, 2016
Section: CPE42FB1
Date Submitted: Dec. 13, 2016
Members: Cahapon, Mamaril, Rabino,
Rodriguez, Sotto

Instructor: Engr. Rommel Manalo

1. Objective(s):
The activity aims to Implement and simulate different kinds of Combinational Circuit in
the FPGA Board.
2. Intended Learning Outcomes (ILOs)
2.1 To describe the concept of active - low and active-high logic signals.
2.2 Analyze the behavior of each Combinational Circuit.
2.3 Test and download the codes in the FPGA Board.
3. Discussion:
Combinational circuits are the class of digital circuits where the outputs of the circuit are
dependent only on the current inputs. In other words, a combinational circuit is able to
produce an output simply from knowing what the current input values are.
Design of a combinational circuit begins with a behavioral specication and selection of
the implementation technique. These are then followed by simplication, hardware
synthesis, and verication.
Some examples of Combinational Circuit are Decoder, Encoder, Multiplexer and
Demultiplexer.
The Basic function of multiplexer is used very frequently in the digital circuit technology.
With the help of multiplexer a purposeful selected input is passed to the output. This
selection is made by using the required select signals. The reverse procedure takes
place with the use of Demultiplexer. In Demultiplexer the input is passed to the
selected output depending on the select signals.

Figure 2.1 Multiplexer and Demultiplexer

A decoder is a combinational circuit that converts coded inputs to other coded outputs.
The famous examples of decoders are binary n-to-2 n decoders and seven-segment
decoders.

Figure 2.2 Block Diagram of 2-to-4 Decoder

Table 2.1 Truth table of 2-to-4 Decoder

The encoder is a combinational circuit that performs the reverse operation of the
decoder. The encoder has a maximum of 2n inputs and n outputs.

Figure 2.3 Block Diagram of 4-to-2 Encoder

Table 2.2 Truth table of 4-to-2 Decoder

4. Resources:
4.1 A personal computer with installed Xilinx Software
4.2 Internet connection (recommended but not required)
4.3 FPGA BOARD
4.4 AC Adaptors
4.5 USB cable
5. Procedure:
Creating a New Project
Create a new ISE project which will target the FPGA device on Spartan 6 SP601
Evaluation Board.
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5

In the File> New Project > to open the New Project Wizard.
In the Project Name field type Encoder.
Verify that HDL is selected from the Top-Level Source Type list
Click Next to move to the device properties page.
Fill in the properties in the tables as show below:

5.1.6 Click Next to proceed to Project Summary Window in the New Project
Wizard.
5.1.7 Click Finish.
The Encoder project will appear in Design panel on the left.
Creating VHDL Source
In this section, you will create VHDL source code for OR gate.
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5

In the Project menu choose New Source.

In the Select Source type dialog box select VHDL Module Source.
In the File Name field type Encoder.
Verify that the Add to Project checkbox is selected. Click Next
In the Entity Name field type encod42 and in Architecture Name field type
encod42_df .

Double click the Port name field and declare ports for Encoder.
How to Create VHDL Test Bench
Design Simulation
Verifying functionality using Behavioral Simulation
Once the syntax is checked add a VHDL Test Bench file to the file to run simulation.
5.3.1 In the Project menu select New Source

5.3.2 In the New Source Wizard Select VHDL Test Bench for the source type
and enter testbench name for the file.

5.3.3 Click Next.

5.3.4 In associate Source dialog you will be asked to select the source file you
want to associate with the given test bench file. This dictates which source
file actually runs the simulation on. We run the simulation on the top level
module of the design (file}. Click Next.
5.3.5 In Summary window click Finish to complete the creation.
5.3.6 In the Design panel select Simulation radio button to view the file.
5.3.7 You will see that the Xilinx has already generated lines of code to start the
input definition. Scroll down the test bench to see the code between initial
begin and end blocks.
5.3.8 Save the file by Selecting File Save.
5.3.9 Go to the Process Panel, expand the ISim Simulator and double click
Simulate Behavioral Model.
5.3.10 Repeat the same procedure for Decoder, Multiplexer and Demultiplexer.
Decoder
Entity name: decod24
Architecture name: decod24_beh

Multiplexer
Entity name: Mux
Architecture name: behv1
Demultiplexer
Entity name: ent_mux_demux
Architecture name: arch_mux_demux

Create Timing Constraints / User Constraints File

5.4.1 On the Tools Menu click Constraints Editor.
5.4.2 Double click the .ucf file that has created. Edit the ucf and use the
necessary ports for the given program.

(Please refer to the User Constraints Page located at the back).

5.4.3 Close the Constraints Editor.
.
Implement Design and Verify Constraints
Implement the design and verify that it meets the timing constraints specified in
the previous section.
Implementing the Design
5.5.1 Select the source file in the Sources window.
5.5.2 Open the Design Summary by double-clicking the View Design
Summary process in the Processes tab.
5.5.3 Double-click the Implement Design process in the Processes
tab.
Notice that after Implementation is complete, the Implementation
processes have a green check mark next to them indicating that they
completed successfully without Errors or Warnings

5.5.4 Locate the Performance Summary table near the bottom of the
Design Summary.
5.5.5 Click the All Constraints Met link in the Timing Constraints field
to view the Timing
Constraints report. Verify that the design meets the specified timing
requirements
5.5.6 Close the Design Summary.
Download Design to the Spartan -3
This is the last step in the design verification process. This section provides
simple instructions for downloading the counter design to the Spartan-3.
5.6.1 Connect the 5V DC power cable to the power input on the demo
board.
5.6.2 Connect the download cable between the PC and FPGA board
(JTAG).
5.6.3 Select Implementation from the drop-down list in the Sources
window.
5.6.4 Select [file] in the Sources window.
5.6.5 In the Process window, double-click the Configure Target Device
process.
The Xilinx WebTalk Dialog box may open during this process. Click
Decline.
iMPACT opens and the Configure Devices dialog box is displayed.

5.6.6 In the Welcome dialog box, select Configure devices using

Boundary-Scan (JTAG).
5.6.7 Verify that automatically connect to a cable and identify
Boundary-Scan chain is selected.
5.6.8 Click Finish.
5.6.9 If you get a message saying that there are two devices found,
click OK to continue.
The devices connected to the JTAG chain on the board will be detected and
displayed in the iMPACT window.
5.6.10 The Assign New Configuration File dialog box appears. To
assign a configuration file to the device in the JTAG chain,
select the .bit file and click Open.

5.6.11 If you get a Warning message, click OK.

5.6.12 Select Bypass to skip any remaining devices.
5.6.13 Right-click on the device image, and select Program...The
Programming Properties dialog box opens.
5.6.14 Click OK to program the device. When programming is
complete, the Program Succeeded message is displayed.

On the board, LEDs indicating that the circuit / file is running.

5.6.15 Close iMPACT without saving.

6. Activity
6.1 Test and Simulate the VHDL codes below.
Encoder VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity encod42 is
Port ( a : in STD_LOGIC_vector(3 downto 0);
y : out STD_LOGIC_vector(1 downto 0));
end encod42;
architecture encod42_df of encod42 is
begin
with a select
y <= "00" when "0001",
"01" when "0010",
"10" when "0100",
"11" when "1000",
"00" when others;

end encod42_df;

Encoder Test bench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY testbench1 IS
END testbench1;
ARCHITECTURE behavior OF testbench1 IS
-- Component Declaration for the Unit
Under Test (UUT)
COMPONENT encod42
PORT(
a : IN std_logic_vector(3 downto 0);
y : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;

--Inputs
signal a : std_logic_vector(3 downto 0);
--Outputs
signal y : std_logic_vector(1 downto 0);
BEGIN
uut: encod42 PORT MAP (
a => a,
y => y
);

process
begin
a <= "0001";
wait for 100 ns;
a <= "0010";
wait for 100 ns;
a <= "0100";
wait for 100 ns;
a <= "1000";
wait for 100 ns;
end process;

END ;

Decoder VHDL CODE

library ieee;
use ieee.std_logic_1164.all;
entity decod24 is
port ( a : in std_logic_vector(1 downto 0);
y : out std_logic_vector(3 downto 0)
);
end decod24;
architecture decod24_beh of decod24 is
begin
process(a)
begin
case a is
when "00" => y <= "1000";
when "01" => y <= "0100";
when "10" => y <= "0010";
when "11" => y <= "0001";
when others => y <= "0000";
end case;
end process;
end decod24_beh;

Decoder Test bench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Decod24_tst IS
END Decod24_tst;
ARCHITECTURE behavior OF
Decod24_tst IS
COMPONENT decod24
PORT(
a : IN std_logic_vector(1 downto
0);
y : OUT std_logic_vector(3 downto
0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(1 downto
0) := (others => '0');
--Outputs
signal y : std_logic_vector(3 downto 0);

BEGIN
uut: decod24 PORT MAP (
a => a,
y => y
);
process
begin
a <= "00";
wait for 100 ns;
a <= "01";
wait for 100 ns;
a <= "10";
wait for 100 ns;
a <= "11";
wait for 100 ns;
end process;
END;
Multiplexer VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux is
port(
I3:
I2:
I1:
I0:
S:
O:
);
end Mux;

in std_logic_vector(2 downto 0);

in std_logic_vector(2 downto 0);
in std_logic_vector(2 downto 0);
in std_logic_vector(2 downto 0);
in std_logic_vector(1 downto 0);
out std_logic_vector(2 downto 0)

architecture behv1 of Mux is

begin
process(I3,I2,I1,I0,S)
begin

-- use case statement

case S is
when "00" => O <= I0;
when "01" => O <= I1;
when "10" => O <= I2;
when "11" => O <= I3;
when others =>
O <= "ZZZ";
end case;
end process;
end behv1;
Multiplexer Test bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY testbench_Mux IS
END testbench_Mux;
ARCHITECTURE behavior OF testbench_Mux IS
signal T_I3: std_logic_vector(2 downto 0):="000";
signal T_I2: std_logic_vector(2 downto 0):="000";
signal T_I1: std_logic_vector(2 downto 0):="000";
signal T_I0: std_logic_vector(2 downto 0):="000";
signal T_O: std_logic_vector(2 downto 0);
signal T_S: std_logic_vector(1 downto 0);
component Mux
port(
I3:
I2:
I1:
I0:
S:
O:
);
end component;
begin

in std_logic_vector(2 downto 0);

in std_logic_vector(2 downto 0);
in std_logic_vector(2 downto 0);
in std_logic_vector(2 downto 0);
in std_logic_vector(1 downto 0);
out std_logic_vector(2 downto 0)

U_Mux: Mux port map (T_I3, T_I2, T_I1, T_I0, T_S, T_O);
process
variable err_cnt: integer :=0;
begin
T_I3 <= "001";
T_I2 <= "010";
T_I1 <= "101";
T_I0 <= "111";

-- I0-I3 are different signals

-- case select eqaul "00"

wait for 10 ns;
T_S <= "00";
wait for 1 ns;
assert (T_O="111") report "Error Case 0" severity error;
if (T_O/="111") then
err_cnt := err_cnt+1;
end if;
-- case select equal "01"
wait for 10 ns;
T_S <= "01";
wait for 1 ns;
assert (T_O="101") report "Error Case 1" severity error;
if (T_O/="101") then
err_cnt := err_cnt+1;
end if;
-- case select equal "10"
wait for 10 ns;
T_S <= "10";
wait for 1 ns;
assert (T_O="010") report "Error Case 2" severity error;
if (T_O/="010") then
err_cnt := err_cnt+1;
end if;
-- case select equal "11"

wait for 10 ns;

T_S <= "11";
wait for 1 ns;
assert (T_O="001") report "Error Case 3" severity error;
if (T_O/="001") then
err_cnt := err_cnt+1;
end if;
-- case equal "11"
wait for 10 ns;
T_S <= "UU";
-- summary of all the tests
if (err_cnt=0) then
assert (false)
report "Testbench of Mux completed sucessfully!"
severity note;
else
assert (true)
report "Something wrong, try again!"
severity error;
end if;
wait;
end process;
end;
Demultiplexer VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Demux is
Port ( out_0 : out STD_LOGIC;
out_1 : out STD_LOGIC;
out_2 : out STD_LOGIC;
out_3 : out STD_LOGIC;
selector : in STD_LOGIC_vector(1 downto 0);
bit_in : in STD_LOGIC);
end Demux;

architecture Behavioral of Demux is

begin
process(bit_in,selector)
begin
case selector is
when "00" => out_0 <= bit_in; out_1 <= '0'; out_2 <= '0'; out_3 <='0';
when "01" => out_1 <= bit_in; out_0 <= '0'; out_2 <= '0'; out_3 <='0';
when "10" => out_2 <= bit_in; out_0 <= '0'; out_1 <= '0'; out_3 <='0';
when others => out_3 <= bit_in; out_0 <= '0'; out_1 <= '0'; out_2 <='0';
end case;
end process;
end Behavioral;
Demultiplexer Test bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Demux_tst IS
END Demux_tst;
ARCHITECTURE behavior OF Demux_tst IS
COMPONENT Demux
PORT(
out_0 : OUT std_logic;
out_1 : OUT std_logic;
out_2 : OUT std_logic;
out_3 : OUT std_logic;
selector : IN std_logic_vector(1 downto 0);
bit_in : IN std_logic
);
END COMPONENT;
--Inputs
signal selector : std_logic_vector(1 downto 0) := (others => '0');
signal bit_in : std_logic := '0';
--Outputs
signal out_0 : std_logic;
signal out_1 : std_logic;
signal out_2 : std_logic;
signal out_3 : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

BEGIN
-- Instantiate the Unit Under Test (UUT)

uut: Demux PORT MAP (

out_0 => out_0,
out_1 => out_1,
out_2 => out_2,
out_3 => out_3,
selector => selector,
bit_in => bit_in
);
PROCESS
BEGIN
bit_in <= '1';
selector <="00";
wait for 2 ns;
selector <="01";
wait for 2 ns;
selector <="10";
wait for 2 ns;
selector <="11";
wait for 2 ns;
--more input combinations can be given here.
end process;
END;

6.2 Sketch the resulting RTL Schematic

a. Encoder

Number of Slices:

Sketch of simulation timing diagram of Encoder

Sketch of simulation timing diagram of Encoder

____1___

Number of 4 input LUTs :

____1___

Number of bonded IOBs:

____6___

b. Decoder
Number of Slices:

___2____

Number of 4 input LUTs :

__2_____

Number of bonded IOBs:

___6____

Sketch of simulation timing diagram of Decoder

c. Multiplexer

Number of Slices:

Sketch of simulation timing diagram of Multiplexer

Sketch of simulation timing diagram of Multiplexer

___2____

Number of 4 input LUTs :

___2____

Number of bonded IOBs:

___17___

d. Demultiplexer
Number of Slices:

__2_____

Number of 4 input LUTs :

__2_____

Number of bonded IOBs:

___7____

Sketch of simulation timing diagram of Demultiplexer

Course: CPE402

Experiment No.: 2

Group No.:

Section: CPE42FB1

Group Members: Cahapon,

Rabino, Rodriguez, Sotto

Mamaril, Date Performed: Dec. 6, 2016

Date Submitted: Dec. 13, 2016
Instructor: Engr. Rommel Manalo

7. Data and Results:

7.1 Relate the VHDL module to test bench.
When signals are added/removed and removed from entities, they only need to
be added or removed from the entity declaration and the port map. Components
are useful when what is being instantiated does not have a VHDL module. While
the test bench is a specification in VHDL that plays the role of a complete
simulation environment for the analyzed system (unit under test, UUT). A test
bench contains both the UUT as well as stimuli for the simulation. ... The entity of
a test bench does not have any ports as this serves as an environment for the
UUT.
7.2 Discuss the difference of IOB and LUT.
An IOB is a collection or grouping of basic elements that implement the input and
output functions of FPGA and CPLD devices. While, LUT is a fast way to realize
a complex function in digital logic. The address is the function input, and the
value at that address is the function output.
7.3 Choose one from the test benches of Encoder, Decoder, Multiplexer and
Demultiplexer. Explain its behavior.
Encoder, Binary encoder has 1 input lines and 1 output. By selecting the output
as binary. VHDL Code for encoder can be designed both in structural and
behavioral modeling.
8. Conclusion:
In this activity, a combinational circuits is a circuit whose output depends only on
the state of its inputs, meaning, it will be able to produce a output that simply
knowing the current input values.

9. Assessment (Rubric for Laboratory Performance):