8086 Opcode

00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
ADD
ADD
ADD
ADD
ADD
ADD
PUSH
POP
OR
OR
OR
OR
OR
OR
PUSH
-ADC
ADC
ADC
ADC
ADC
ADC
PUSH
POP
SBB
SBB
SBB
SBB
SBB
SBB
PUSH
POP
AND
AND
AND
AND
AND
AND
ES:
DAA
SUB
SUB
SUB
SUB
SUB
SUB
CS:
DAS
XOR
XOR
XOR
XOR
XOR
XOR
SS:
AAA
CMP
ES
Eb
Ev
Gb
Gv
AL
eAX
Gb
Gv
Eb
Ev
Ib
Iv
ES
Eb
Ev
Gb
Gv
AL
eAX
Gb
Gv
Eb
Ev
Ib
Iv
Eb
Ev
Gb
Gv
AL
eAX
Gb
Gv
Eb
Ev
Ib
Iv
SS
Eb
Ev
Gb
Gv
AL
eAX
Gb
Gv
Eb
Ev
Ib
Iv
DS
Eb
Ev
Gb
Gv
AL
eAX
Gb
Gv
Eb
Ev
Ib
Iv
Eb
Ev
Gb
Gv
AL
eAX
Gb
Gv
Eb
Ev
Ib
Iv
Eb
Ev
Gb
Gv
AL
eAX
Gb
Gv
Eb
Ev
Ib
Iv
Eb
Gb
CS
SS
DS
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
CMP
CMP
CMP
CMP
CMP
DS:
AAS
INC
INC
INC
INC
INC
INC
INC
INC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
POP
POP
POP
POP
POP
POP
POP
POP
----------------JO
JNO
Ev
Gb
Gv
AL
eAX
eAX
eCX
eDX
eBX
eSP
eBP
eSI
eDI
eAX
eCX
eDX
eBX
eSP
eBP
eSI
eDI
eAX
eCX
eDX
eBX
eSP
eBP
eSI
eDI
eAX
eCX
eDX
eBX
eSP
eBP
eSI
eDI
Jb
Jb
Gv
Eb
Ev
Ib
Iv
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
JB
JNB
JZ
JNZ
JBE
JA
JS
JNS
JPE
JPO
JL
JGE
JLE
JG
GRP1
GRP1
GRP1
GRP1
TEST
TEST
XCHG
XCHG
MOV
MOV
MOV
MOV
MOV
LEA
MOV
POP
NOP
XCHG
XCHG
XCHG
XCHG
XCHG
XCHG
XCHG
CBW
CWD
CALL
WAIT
PUSHF
POPF
SAHF
LAHF
MOV
MOV
MOV
MOV
eAX
MOVSB
MOVSW
CMPSB
CMPSW
TEST
TEST
Jb
Jb
Jb
Jb
Jb
Jb
Jb
Jb
Jb
Jb
Jb
Jb
Jb
Jb
Ib
Iv
Ib
Ib
Eb
Ev
Eb
Ev
Eb
Ev
Gb
Gv
Ew
Gv
Sw
Ev
Eb
Ev
Eb
Ev
Gb
Gv
Gb
Gv
eCX
eDX
eBX
eSP
eBP
eSI
eDI
Gb
Gv
Eb
Ev
Sw
M
Ew
eAX
eAX
eAX
eAX
eAX
eAX
eAX
Ap
AL
eAX
Ob
Ov
AL
eAX
Ib
Iv
Ob
Ov
AL
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
STOSB
STOSW
LODSB
LODSW
SCASB
SCASW
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
--RET
RET
LES
LDS
MOV
MOV
--RETF
RETF
INT
INT
INTO
IRET
GRP2
GRP2
GRP2
GRP2
AAM
AAD
-XLAT
--------LOOPNZ
LOOPZ
LOOP
AL
CL
DL
BL
AH
CH
DH
BH
eAX
eCX
eDX
eBX
eSP
eBP
eSI
eDI
Ib
Ib
Ib
Ib
Ib
Ib
Ib
Ib
Iv
Iv
Iv
Iv
Iv
Iv
Iv
Iv
Iw
Gv
Gv
Eb
Ev
Iw
3
Ib
Eb
Ev
Eb
Ev
Jb
Jb
Jb
1
1
CL
CL
I0
I0
Mp
Mp
Ib
Iv
E3
E4
E5
E6
E7
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
JCXZ
IN
IN
OUT
OUT
eAX
CALL
JMP
JMP
JMP
IN
IN
OUT
OUT
eAX
LOCK
-REPNZ
REPZ
HLT
CMC
GRP3a
GRP3b
CLC
STC
CLI
STI
CLD
STD
GRP4
GRP5
GRP1/0
GRP1/1
GRP1/2
GRP1/3
GRP1/4
GRP1/5
GRP1/6
GRP1/7
ADD
OR
ADC
SBB
AND
SUB
XOR
CMP
E8
E9
EA
EB
EC
ED
EE
EF
Jb
Jv
Eb
Ev
Eb
Ev
AL
eAX
Ib
Ib
Jv
Ap
Jb
AL
eAX
DX
DX
Ib
Ib
AL
DX
DX
AL
GRP2/0
GRP2/1
GRP2/2
GRP2/3
GRP2/4
GRP2/5
GRP2/6
GRP2/7
GRP3a/0
GRP3a/1
GRP3a/2
GRP3a/3
GRP3a/4
GRP3a/5
GRP3a/6
GRP3a/7
GRP3b/0
GRP3b/1
GRP3b/2
GRP3b/3
GRP3b/4
GRP3b/5
GRP3b/6
GRP3b/7
GRP4/0
GRP4/1
GRP4/2
GRP4/3
GRP4/4
GRP4/5
GRP4/6
GRP4/7
GRP5/0
GRP5/1
GRP5/2
GRP5/3
GRP5/4
GRP5/5
GRP5/6
GRP5/7
ROL
ROR
RCL
RCR
SHL
SHR
-SAR
TEST
-NOT
NEG
MUL
IMUL
DIV
IDIV
TEST
-NOT
NEG
MUL
IMUL
DIV
IDIV
INC
DEC
------INC
DEC
CALL
CALL
JMP
JMP
PUSH
--
Eb
Ib
Ev
Iv
Mp
Mp
Argument Addressing Codes

A
Direct address. The instruction has no ModR/M byte; the address of

the operand is encoded in the instruction. Applicable, e.g., to far JMP
(opcode EA).
A ModR/M byte follows the opcode and specifies the operand. The
operand is either a general-purpose register or a memory address. If
it is a memory address, the address is computed from a segment
register and any of the following values: a base register, an index
register, a displacement.
The reg field of the ModR/M byte selects a general register.
Immediate data. The operand value is encoded in subsequent bytes of

the instruction.
The instruction contains a relative offset to be added to the address of

the subsequent instruction. Applicable, e.g., to short JMP (opcode
EB), or LOOP.
The ModR/M byte may refer only to memory. Applicable, e.g., to LES
and LDS.
The instruction has no ModR/M byte; the offset of the operand is

encoded as a WORD in the instruction. Applicable, e.g., to certain
MOVs (opcodes A0 through A3).
The reg field of the ModR/M byte selects a segment register.
Argument Operand Codes

0
Byte argument. Unusual in that arguments of this type are suppressed

in ASM output when they have the default value of 10 (0xA).
Applicable, e.g., to AAM and AAD.
Byte argument.
32-bit segment:offset pointer.
Word argument.
Word argument. (The 'v' code has a more complex meaning in later
x86 opcode maps, from which this was derived, but here it's just a
synonym for the 'w' code.)
Special Argument Codes

AL
8-bit register: The low byte of AX
CL
8-bit register: The low byte of CX
DL
8-bit register: The low byte of DX
BL
8-bit register: The low byte of BX
AH
8-bit register: The high byte of AX
CH
8-bit register: The high byte of CX
DH
8-bit register: The high byte of DX
BH
8-bit register: The high byte of BX
AX
16-bit register: The 'accumulator' register
CX
16-bit register: The 'counter' register
DX
16-bit register: The 'data' register
BX
16-bit register: The 'base' register
SP
16-bit register: The 'stack pointer' register
BP
16-bit register: The 'base pointer' register
SI
16-bit register: The 'source index' register
DI
16-bit register: The 'destination index' register
ES
16-bit register: The 'extra' segment register
CS
16-bit register: The 'code' segment register
SS
16-bit register: The 'stack' segment register
DS
16-bit register: The 'data' segment register
A constant argument of 1, implicit in the opcode, and not represented

elsewhere in the instruction. This argument *is* displayed in
assembly code.
A constant argument of 3, implicit in the opcode, and not

represented elsewhere in the instruction. This argument *is*
displayed in assembly code.
The ModR/M byte refers to a memory location, however the contents

of that memory location are irrelevant; the address itself is the
operand of the instruction. Applicable, e.g., to LEA.
Instructions and opcodes

oo : Function
00 : If mmm = 110, then a displacement follows the operation;

otherwise, no displacement is used
01 : An 8-bit signed displacement follows the opcode
10 : A 16-bit signed displacement follows the opcode
11 : mmm specifies a register, instead of an addressing mode
mmm : Function
000 : DS:[BX+SI]
001 : DS:[BX+DI]
010 : SS:[BP+SI]
011 : SS:[BP+DI]
100 : DS:[SI]
101 : DS:[DI]
110 : SS:[BP]
111 : DS:[BX]
rrr : W=0 : W=1 : reg32
000 : AL : AX : EAX
001 : CL : CX : ECX
010 : DL : DX : EDX
011 : BL : BX : EBX
100 : AH : SP : ESP
101 : CH : BP : EBP
110 : DH : SI : ESI
111 : BH : DI : EDI
sss : Segment Register
000 : ES
001 : CS
010 : SS
011 : DS
100 : FS (Only 386+)
101 : GS (Only 386+)
rrr : Index Register
000 : EAX
001 : ECX
010 : EDX
011 : EBX
100 : No Index
101 : EBP
110 : ESI
111 : EDI
32 bit addressing-mode
oo
mmm
rrr
Description
00
000
DS:[EAX]
00
001
DS:[ECX]
00
010
DS:[EDX]
00
011
DS:[EBX]
00
100
000
DS:[EAX+scaled_index]
00
100
001
DS:[ECX+scaled_index]
00
100
010
DS:[EDX+scaled_index]
00
100
011
DS:[EBX+scaled_index]
00
100
100
SS:[ESP+scaled_index]
00
100
101
DS:[disp32+scaled_index]
00
100
110
DS:[ESI+scaled_index]
00
100
111
DS:[EDI+scaled_index]
00
101
DS:disp32
00
110
DS:[ESI]
00
111
DS:[EDI]
01
000
DS:[EAX+disp8]
01
001
DS:[ECX+disp8]
01
010
DS:[EDX+disp8]
01
011
DS:[EBX+disp8]
01
100
000
DS:[EAX+scaled_index+disp8]
01
100
001
DS:[ECX+scaled_index+disp8]
01
100
010
DS:[EDX+scaled_index+disp8]
01
100
011
DS:[EBX+scaled_index+disp8]
01
100
100
SS:[ESP+scaled_index+disp8]
01
100
101
SS:[EBP+scaled_index+disp8]
01
100
110
DS:[ESI+scaled_index+disp8]
01
100
111
DS:[EDI+scaled_index+disp8]
01
101
SS:[EBP+disp8]
01
110
DS:[ESI+disp8]
01
111
DS:[EDI+disp8]
10
000
DS:[EAX+disp32]
10
001
DS:[ECX+disp32]
10
010
DS:[EDX+disp32]
10
011
DS:[EBX+disp32]
10
100
000
DS:[EAX+scaled_index+disp32]
10
100
001
DS:[ECX+scaled_index+disp32]
10
100
010
DS:[EDX+scaled_index+disp32]
10
100
011
DS:[EBX+scaled_index+disp32]
10
100
100
SS:[ESP+scaled_index+disp32]
10
100
101
SS:[EBP+scaled_index+disp32]
10
100
110
DS:[ESI+scaled_index+disp32]
10
100
111
DS:[EDI+scaled_index+disp32]
10
101
SS:[EBP+disp32]
10
110
DS:[ESI+disp32]
10
111
DS:[EDI+disp32]
Name
Regs
AAM
ASCII Adjust After

Addition
11010101
ASCII Adjust Register

AX Before Division
1101010100001010
ASCII Adjust Register

AX Before Division
11010100
ASCII Adjust AX
Register After
Multiplication
1101010000001010
ASCII Adjust AX
Register After
Multiplication
00111111
ASCII Adjust AL
Register After
Subtraction
Reg,Reg
0001001woorrrmmm
Add Integers with Carry
Mem,Reg
0001000woorrrmmm
Reg,Mem
0001001woorrrmmm
Acc,Imm
0001010w
Reg,Imm8
1000001woo010mmm
Mem,Imm8
1000001woo010mmm
Reg,Imm
1000000woo010mmm
Mem,Imm
1000000woo010mmm
Imm8
Imm8
AAS
ADC
Description
00110111
AAA
AAD
Opcode
ADD
AND
Reg,Reg
0000001woorrrmmm
Add Integers
Mem,Reg
0000000woorrrmmm
Add Integers
Reg,Mem
0000001woorrrmmm
Add Integers
Acc,Imm
0000010w
Add Integers
Reg,Imm8
1000001woo000mmm
Add Integers
Mem,Imm8
1000001woo000mmm
Add Integers
Reg,Imm
1000000woo000mmm
Add Integers
Mem,Imm
1000000woo000mmm
Add Integers
Reg,Reg
0010001woorrrmmm
Logical AND
Mem,Reg
0010000woorrrmmm
Logical AND
Reg,Mem
0010001woorrrmmm
Logical AND
Acc,Imm
0010010w
Logical AND
Reg,Imm8
1000001woo100mmm
Logical AND
Mem,Imm8
1000001woo100mmm
Logical AND
Reg,Imm
1000000woo100mmm
Logical AND
Mem,Imm
1000000woo100mmm
Logical AND
RegWord,RegW
0000111110111100oorrrmmm
ord
Bit Scan Forward
RegWord,Mem
Word
0000111110111100oorrrmmm
Bit Scan Forward
RegWord,RegW
0000111110111101oorrrmmm
ord
Bit Scan Reverse
RegWord,Mem
Word
0000111110111101oorrrmmm
Bit Scan Reverse
BSWAP
RegWord
0000111111001rrr
Byte swap
BT
RegWord,Imm8 0000111110111010oo100mmm
Bit Test
MemWord,Imm
0000111110111010oo100mmm
8
Bit Test
RegWord,RegW
0000111110100011oorrrmmm
ord
Bit Test
MemWord,Reg
Word
Bit Test
BSF
BSR
BTC
0000111110100011oorrrmmm
Bit Test and Complement
MemWord,Imm
0000111110111010oo111mmm
8
BTR
BTS
RegWord,RegW
0000111110111011oorrrmmm
ord
MemWord,Reg
Word
0000111110111011oorrrmmm
Bit Test and Reset
MemWord,Imm
0000111110111010oo110mmm
8
Bit Test and Reset
RegWord,RegW
0000111110110011oorrrmmm
ord
Bit Test and Reset
MemWord,Reg
Word
Bit Test and Reset
0000111110110011oorrrmmm
Bit Test and Set
MemWord,Imm
0000111110111010oo101mmm
8
Bit Test and Set
RegWord,RegW
0000111110101011oorrrmmm
ord
Bit Test and Set
MemWord,Reg
Word
0000111110101011oorrrmmm
Bit Test and Set
CBW
10011000
Convert Byte to Word
CDQ
10011001
Convert Doubleword to
Quad-Word
CLC
11111000
Clear Carry Flag (CF)
CLD
11111100
Clear Direction Flag (DF)
CLI
11111010
Clear Interrupt Flag (IF)
CLTS
0000111100000110
Clear Task-Switched Flag

in Control Register Zero
CMC
11110101
Complementer Carry Flag

(CF)
Reg,Reg
000011110100ccccoorrrmmm
Conditional Move
Reg,Mem
000011110100ccccoorrrmmm
Conditional Move
Reg,Reg
0011101woorrrmmm
Compare
Mem,Reg
0011100woorrrmmm
Compare
Reg,Mem
0011101woorrrmmm
Compare
Acc,Imm
0011110w
Compare
Reg,Imm8
1000001woo111mmm
Compare
Mem,Imm8
1000001woo111mmm
Compare
CMOVcc
CMP
Reg,Imm
1000000woo111mmm
Compare
Mem,Imm
1000000woo111mmm
Compare
CMPSB
10100110
Compare String - Byte
CMPSW
10100111
Compare String - Word
CMPSD
10100111
Compare String Doubleword
CMPXCHG Reg,Reg
000011111011000woorrrmmm
Compare and Exchange
000011111011000woorrrmmm
Compare and Exchange
CMPXCHG
Mem64
8B
0000111111000111oo001mmm
Compare and Exchange 8

Bytes
CPUID
0000111110100010
CPU Identification code

to EAX
CWD
10011001
Convert Word to
Doubleword
CWDE
10011000
Convert Word to
Extended Doubleword
DAA
00100111
Decimal Adjust Register

After Addition
00101111
Decimal Adjust AL
Register After
Substraction
RegWord
01001rrr
Decrement by One
Reg
1111111woo001mmm
Decrement by One
Mem
1111111woo001mmm
Decrement by One
Reg
1111011woo110mmm
Unsigned Integer Divide
Mem
1111011woo110mmm
Unsigned Integer Divide
Imm16,Imm8
11001000
Make Stack Frame for

Procedure Parameter
11110100
Halt
Reg
1111011woo111mmm
Signed Divide
Mem
1111011woo111mmm
Signed Divide
Mem,Reg
DAS
DEC
DIV
ENTER
HLT
IDIV
IMUL
RegWord,RegW
01101011oorrrmmm
ord,Imm8
Signed Integer Multiply
RegWord,Mem
Word,Imm8
01101011oorrrmmm
RegWord,RegW 01101001oorrrmmm
ord,Imm
RegWord,Mem
Word,Imm
01101001oorrrmmm
RegWord,Imm8 0110101111rrrqqq
RegWord,Imm
0110100111rrrqqq
RegWord,RegW
0000111110101111oorrrmmm
ord
RegWord,Mem
Word
0000111110101111oorrrmmm
Reg
1111011woo101mmm
Mem
1111011woo101mmm
Acc,Imm8
1110010w
Input from Port
Acc,DX
1110110w
Input from Port
RegWord
01000rrr
Increment by 1
Reg
1111111woo000mmm
Increment by 1
Mem
1111111woo000mmm
Increment by 1
INSB
01101100
Input Byte
INSW
01101101
Input Word
INSD
01101101
Input DoubleWord
11001100
Call to Interrupt
Procedure
Imm8
11001101
Call to Interrupt
Procedure
INTO
11001110
Interrupt on Overflow
INVD
0000111100001000
Invalidate data cache
0000111100000001oo111mmm
Invalidate TBL entry
IRET
11001111
Return from Interrupt
IRETD
11001111
Return from Interrupt 32-bit Mode
LAHF
10011111
Load Flags into AH

Register
IN
INC
INT
INVLPG
LAR
Mem
RegWord,RegW
0000111100000010oorrrmmm
ord
Load Access Rights Byte
RegWord,Mem
Word
Load Access Rights Byte
0000111100000010oorrrmmm
LDS
LES
LFS
LGS
LSS
LEA
Reg16,Mem32
11000101oorrrmmm
Load Pointer Using DS
Reg32,Mem64
11000101oorrrmmm
Load Pointer Using DS
Reg16,Mem32
11000100oorrrmmm
Load Pointer Using ES
Reg32,Mem64
11000100oorrrmmm
Load Pointer Using ES
Reg16,Mem32
0000111110110100oorrrmmm
Load Pointer Using FS
Reg32,Mem64
0000111110110100oorrrmmm
Load Pointer Using FS
Reg16,Mem32
0000111110110101oorrrmmm
Load Pointer Using GS
Reg32,Mem64
0000111110110101oorrrmmm
Load Pointer Using GS
Reg16,Mem32
0000111110110010oorrrmmm
Load Pointer Using SS
Reg32,Mem64
0000111110110010oorrrmmm
Load Pointer Using SS
RegWord,Mem
10001101oorrrmmm
Load Effective Address
11001001
High Level Procedure

Exit
LEAVE
LGDT
Mem64
0000111100000001oo010mmm
Load Global Descriptor

Table
LIDT
Mem64
0000111100000001oo011mmm
Load Interrupt Descriptor

Table
LLDT
Reg16
0000111100000000oo010mmm
Load Local Descriptor

Table
Mem16
0000111100000000oo010mmm
Load Local Descriptor

Table
Reg16
0000111100000001oo110mmm
Load Machine Status

Word
Mem16
0000111100000001oo110mmm
Load Machine Status

Word
LODSB
10101100
Load Byte
LODSW
10101101
Load Word
LODSD
10101101
Load Doubleword
LMSW
LSL
LTR
MOV
RegWord,RegW
0000111100000011oorrrmmm
ord
Load Segment Limit
RegWord,Mem
Word
0000111100000011oorrrmmm
Load Segment Limit
Reg16
0000111100000000oo011mmm
Load Task Register
Mem16
0000111100000000oo011mmm
Load Task Register
MemOfs,Acc
1010001w
Move Data
Acc,MemOfs
1010000w
Move Data
Reg,Imm
1011wrrr
Move Data
Mem,Imm
1100011woo000mmm
Move Data
Reg,Reg
1000101woorrrmmm
Move Data
Reg,Mem
1000101woorrrmmm
Move Data
Mem,Reg
1000100woorrrmmm
Move Data
Reg16,Seg
10001100oosssmmm
Move Data
Seg,Reg16
10001110oosssmmm
Move Data
Mem16,Seg
10001100oosssmmm
Move Data
Seg,Mem16
10001110oosssmmm
Move Data
Reg32,CRn
000011110010000011sssrrr
Move Data
CRn,Reg32
000011110010001011sssrrr
Move Data
Reg32,DRn
000011110010000111sssrrr
Move Data
DRn,Reg32
000011110010001111sssrrr
Move Data
Reg32,TRn
000011110010010011sssrrr
Move Data
TRn,Reg32
000011110010011011sssrrr
Move Data
MOVSB
10100100
Move Byte
MOVSW
10100101
Move Word
MOVSD
10100101
Move Doubleword
0000111110111110oorrrmmm
Move with Sign

Extension
RegWord,Mem8 0000111110111110oorrrmmm
Move with Sign

Extension
RegWord,Reg16 0000111110111111oorrrmmm
Move with Sign

Extension
RegWord,Mem1
0000111110111111oorrrmmm
6
Move with Sign

Extension
RegWord,Reg8
0000111110110110oorrrmmm
Move with Zero

Extension
RegWord,Mem8 0000111110110110oorrrmmm
Move with Zero

Extension
RegWord,Reg16 0000111110110111oorrrmmm
Move with Zero

Extension
RegWord,Mem1
0000111110110111oorrrmmm
6
Move with Zero

Extension
MOVSX
MOVZX
RegWord,Reg8
Reg
1111011woo100mmm
Unsigned Integer
Multiply of AL, AX or
EAX
Mem
1111011woo100mmm
Unsigned Integer
Multiply of AL, AX or
EAX
Reg
1111011woo011mmm
Negate(Two's
Complement)
Mem
1111011woo011mmm
Negate(Two's
Complement)
10010000
No Operation
Reg
1111011woo010mmm
Negate(One's
Complement)
Mem
1111011woo010mmm
Negate(One's
Complement)
Reg,Reg
0000101woorrrmmm
Logical Inclusive OR
Mem,Reg
0000100woorrrmmm
Reg,Mem
0000101woorrrmmm
Acc,Imm
0000110w
Reg,Imm8
1000001woo001mmm
Mem,Imm8
1000001woo001mmm
Reg,Imm
1000000woo001mmm
Mem,Imm
1000000woo001mmm
Imm8,Acc
1110011w
Output To Port
DX,Acc
1110111w
Output To Port
OUTSB
01101110
Output Byte
OUTSW
01101111
Output Word
OUTSD
01101111
Output Doubleword
RegWord
01011rrr
Pop a Word from the

Stack
MemWord
10001111oo000mmm
Pop a Word from the

Stack
SegOld
00sss111
Pop a Word from the

Stack
Seg
0000111110sss001
Pop a Word from the

Stack
MUL
NEG
NOP
NOT
OR
OUT
POP
POPA
01100001
POP All Registers
POPAD
01100001
POP All Registers - 32bit Mode
POPF
10011101
POP Stack into FLAGS
POPFD
10011101
POP Stack into EFLAGS
RegWord
01010rrr
Push Operand onto Stack
MemWord
11111111oo110mmm
SegOld
00sss110
Seg
0000111110sss000
Imm8
01101010
Imm
01101000
PUSHW
Imm16
01101000
PUSH Word
PUSHD
Imm32
01101000
PUSH Double Word
PUSHA
01100000
PUSH All Registers
PUSHAD
01100000
PUSH All Registers - 32bit Mode
PUSHF
10011100
PUSH FLAGS
PUSHFD
10011100
PUSH EFLAGS
Reg,1
1101000woo010mmm
Rotate Left through Carry

- Uses CF for Extension
Mem,1
1101000woo010mmm

Reg,CL
1101001woo010mmm

Mem,CL
1101001woo010mmm

Reg,Imm8
1100000woo010mmm

Mem,Imm8
1100000woo010mmm

Reg,1
1101000woo011mmm
Rotate Right through

Carry - Uses CF for
Extension
1101000woo011mmm

Carry - Uses CF for
Extension
PUSH
RCL
RCR
Mem,1
Reg,CL
1101001woo011mmm

Carry - Uses CF for
Extension
Mem,CL
1101001woo011mmm

Carry - Uses CF for
Extension
Reg,Imm8
1100000woo011mmm

Carry - Uses CF for
Extension
Mem,Imm8
1100000woo011mmm

Carry - Uses CF for
Extension
0000111100110010
Read from Model

Specific Register
RDMSR
RET
NEAR
11000011
Return from
subprocedure
RET
imm NEAR
11000010
Return from
subprocedure
RET
FAR
11001011
Return from
subprocedure
RET
imm FAR
11001010
Return from
subprocedure
0000111100110011
Read Performance
Monitor Counter
Reg,1
1101000woo000mmm

- Wrap bits around
Mem,1
1101000woo000mmm

- Wrap bits around
Reg,CL
1101001woo000mmm

- Wrap bits around
Mem,CL
1101001woo000mmm

- Wrap bits around
Reg,Imm8
1100000woo000mmm

- Wrap bits around
Mem,Imm8
1100000woo000mmm

- Wrap bits around
Reg,1
1101000woo001mmm

Carry - Wrap bits around
Mem,1
1101000woo001mmm
RDPMC
ROL
ROR

Reg,CL
1101001woo001mmm

Mem,CL
1101001woo001mmm

Reg,Imm8
1100000woo001mmm

Mem,Imm8
1100000woo001mmm

RSM
0000111110101010
Return from System

Management mode
SALC
11010110
Set AL on Carry
SAHF
10011110
Load Flags into AH

Register
Reg,1
1101000woo100mmm
Shift Arithmetic Left
Mem,1
1101000woo100mmm
Reg,CL
1101001woo100mmm
Mem,CL
1101001woo100mmm
Reg,Imm8
1100000woo100mmm
Mem,Imm8
1100000woo100mmm
Reg,1
1101000woo111mmm
Shift Arithmetic Right
Mem,1
1101000woo111mmm
Reg,CL
1101001woo111mmm
Mem,CL
1101001woo111mmm
Reg,Imm8
1100000woo111mmm
Mem,Imm8
1100000woo111mmm
Reg8
000011111001ccccoo000mmm
Set Byte on Condition

Code
Mem8
000011111001ccccoo000mmm
Set Byte on Condition

Code
Reg,1
1101000woo100mmm
Shift Logic Left
Mem,1
1101000woo100mmm
Shift Logic Left
Reg,CL
1101001woo100mmm
Shift Logic Left
Mem,CL
1101001woo100mmm
Shift Logic Left
Reg,Imm8
1100000woo100mmm
Shift Logic Left
SAL
SAR
SETcc
SHL
Mem,Imm8
1100000woo100mmm
Shift Logic Left
Reg,1
1101000woo101mmm
Shift Logic Right
Mem,1
1101000woo101mmm
Shift Logic Right
Reg,CL
1101001woo101mmm
Shift Logic Right
Mem,CL
1101001woo101mmm
Shift Logic Right
Reg,Imm8
1100000woo101mmm
Shift Logic Right
Mem,Imm8
1100000woo101mmm
Shift Logic Right
Reg,Reg
0001101woorrrmmm
Substract Integers with

Borrow
Mem,Reg
0001100woorrrmmm

Borrow
Reg,Mem
0001101woorrrmmm

Borrow
Acc,Imm
0001110w

Borrow
Reg,Imm8
1000001woo011mmm

Borrow
Mem,Imm8
1000001woo011mmm

Borrow
Reg,Imm
1000000woo011mmm

Borrow
Mem,Imm
1000000woo011mmm

Borrow
SCASB
10101110
Compare Byte
SCASW
10101111
Compare Word
SCASD
10101111
Compare Doubleword
0000111100000001oo000mmm
Store Global Descriptor

Table
SHR
SBB
SGDT
Mem64
SHLD
RegWord,RegW
0000111110100100oorrrmmm
ord,Imm8
Double Precision Shift

Left
MemWord,Reg
Word,Imm8
0000111110100100oorrrmmm

Left
RegWord,RegW
0000111110100101oorrrmmm
ord,CL

Left
MemWord,Reg
Word,CL

Left
0000111110100101oorrrmmm
RegWord,RegW
0000111110101100oorrrmmm
ord,Imm8

Right
MemWord,Reg
Word,Imm8
0000111110101100oorrrmmm

Right
RegWord,RegW
0000111110101101oorrrmmm
ord,CL

Right
MemWord,Reg
Word,CL
0000111110101101oorrrmmm

Right
SIDT
Mem64
0000111100000001oo001mmm
Store Interrupt Descriptor

Table
SLDT
Reg16
0000111100000000oo000mmm
Store Local Descriptor

Table Register (LDTR)
Mem16
0000111100000000oo000mmm
Store Local Descriptor

Table Register (LDTR)
Reg16
0000111100000001oo100mmm
Store Machine Status

Word
Mem16
0000111100000001oo100mmm
Store Machine Status

Word
STC
11111001
Set Carry Flag(CF)
STD
11111101
Set Direction Flag(DF)
STI
11111011
Set Interrupt Flag(IF)
STOSB
10101010
Store String Data Byte
STOSW
10101011
Store String Data Word
STOSD
10101011
Store String Data

DoubleWord
Reg16
0000111100000000oo001mmm
Store Task Register
Mem16
0000111100000000oo001mmm
Store Task Register
Reg,Reg
0010101woorrrmmm
Subtract
Mem,Reg
0010100woorrrmmm
Subtract
Reg,Mem
0010101woorrrmmm
Subtract
Acc,Imm
0010110w
Subtract
Reg,Imm8
1000001woo101mmm
Subtract
Mem,Imm8
1000001woo101mmm
Subtract
Reg,Imm
1000000woo101mmm
Subtract
Mem,Imm
1000000woo101mmm
Subtract
SHRD
SMSW
STR
SUB
TEST
Reg,Reg
1000010woorrrmmm
Test Operands
Mem,Reg
1000010woorrrmmm
Test Operands
Reg,Mem
1000010woorrrmmm
Test Operands
Acc,Imm
1010100w
Test Operands
Reg,Imm
1111011woo000mmm
Test Operands
Mem,Imm
1111011woo000mmm
Test Operands
Reg16
0000111100000000oo100mmm
Verify Read
Mem16
0000111100000000oo100mmm
Verify Read
Reg16
0000111100000000oo101mmm
Verify Write
Mem16
0000111100000000oo101mmm
Verify Write
WAIT
10011011
Wait for FPU
WBINVD
0000111100001001
Write Back and

Invalidate Data Cache
WRMSR
0000111100110000
Write to Model Specific

Register
Reg,Reg
000011111100000woorrrmmm
Exchange and Add
Mem,Reg
000011111100000woorrrmmm
Exchange and Add
VERR
VERW
XADD
XCHG
AccWord,RegW
10010rrr
ord
Exchange
RegWord,AccW
10010rrr
ord
Exchange
Reg,Reg
1000011woorrrmmm
Exchange
Mem,Reg
1000011woorrrmmm
Exchange
Reg,Mem
1000011woorrrmmm
Exchange
11010111
Translate
Reg,Reg
0011001woorrrmmm
Exclusive-OR
Mem,Reg
0011000woorrrmmm
Exclusive-OR
Reg,Mem
0011001woorrrmmm
Exclusive-OR
Acc,Imm
0011010w
Exclusive-OR
Reg,Imm8
1000001woo110mmm
Exclusive-OR
Mem,Imm8
1000001woo110mmm
Exclusive-OR
Reg,Imm
1000000woo110mmm
Exclusive-OR
Mem,Imm
1000000woo110mmm
Exclusive-OR
XLAT
XOR
CALL
MemFar
11111111oo011mmm
Call a Procedure
Near
11101000
Call a Procedure
Far
10011010
Call a Procedure
RegWord
11111111oo010mmm
Call a Procedure
MemNear
11111111oo010mmm
Call a Procedure
Short
0111cccc
Jump on Some Condition

Code
Near
000011111000cccc
Jump on Some Condition

Code
JCXZ
Short
11100011
JCXE
Short
11100011
JECXZ
Short
11100011
JECXE
Short
11100011
JMP
MemFar
11111111oo101mmm
Short
11101011
Near
11101001
Far
11101010
RegWord
11111111oo100mmm
MemNear
11111111oo100mmm
LOOP
Short
11100010
Loop Control While ECX

Counter Not Zero
LOOPZ
Short
11100001
Loop while Zero
LOOPE
Short
11100001
Loop while Equal
LOOPNZ
Short
11100000
Loop while Not Zero
LOOPNE
Short
11100000
Loop while Not Equal
LOCK
11110000
Assert Lock# Signal

Prefix
LOCK:
11110000
Assert Lock# Signal

Prefix
REP
11110011
Repeat Following String

Operation
REPE
11110011
Repeat while Equal
REPZ
11110011
Repeat while Zero
REPNE
11110010
Repeat while Not Equal
Jcc
REPNZ
11110010
Repeat while Not Zero
CS:
00101110
CS segment override
prefix
DS:
00111110
DS segment override
prefix
ES:
00100110
ES segment override
prefix
FS:
01100100
FS segment override
prefix
GS:
01100101
GS segment override
prefix
SS:
00110110
SS segment override
prefix

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8086 Opcode

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00

Argument Addressing Codes

Direct address. The instruction has no ModR/M byte; the address of

The reg field of the ModR/M byte selects a general register.

Immediate data. The operand value is encoded in subsequent bytes of

The instruction contains a relative offset to be added to the address of

The instruction has no ModR/M byte; the offset of the operand is

The reg field of the ModR/M byte selects a segment register.

Argument Operand Codes

Byte argument. Unusual in that arguments of this type are suppressed

32-bit segment:offset pointer.

Special Argument Codes

8-bit register: The low byte of AX

8-bit register: The low byte of CX

8-bit register: The low byte of DX

8-bit register: The low byte of BX

8-bit register: The high byte of AX

8-bit register: The high byte of CX

8-bit register: The high byte of DX

8-bit register: The high byte of BX

16-bit register: The 'accumulator' register

16-bit register: The 'counter' register

16-bit register: The 'data' register

16-bit register: The 'base' register

16-bit register: The 'stack pointer' register

16-bit register: The 'base pointer' register

16-bit register: The 'source index' register

16-bit register: The 'destination index' register

16-bit register: The 'extra' segment register

16-bit register: The 'code' segment register

16-bit register: The 'stack' segment register

16-bit register: The 'data' segment register

A constant argument of 1, implicit in the opcode, and not represented

A constant argument of 3, implicit in the opcode, and not

The ModR/M byte refers to a memory location, however the contents

Instructions and opcodes

00 : If mmm = 110, then a displacement follows the operation;

rrr : W=0 : W=1 : reg32

sss : Segment Register

rrr : Index Register

ASCII Adjust After

ASCII Adjust Register

ASCII Adjust Register

Add Integers with Carry

Add Integers with Carry

Add Integers with Carry

Add Integers with Carry

Add Integers with Carry

Add Integers with Carry

Add Integers with Carry

Add Integers with Carry

Bit Scan Forward

Bit Scan Forward

Bit Scan Reverse

Bit Scan Reverse

Bit Test and Complement

Bit Test and Complement

Bit Test and Complement

Bit Test and Complement

Bit Test and Reset

Bit Test and Reset

Bit Test and Reset