UNIT I

1. Define Threshold voltage

The threshold voltage VT for a MOS transistor can be defined as the
voltage between the gate and the source terminals below which the drain
to source current effectively drops to zero.
2,Define body effect or substrate bias effect.
The threshold voltage VT is not a constant with respect to the
voltage difference between the substrate and the source of the
MOS transistor.This effect is called the body effect or substrate
bias effect.
3. Give the different modes of operation of MOS transistor
a) Cut off mode
b) Linear mode
c) Saturation mode
d)
4. What are the different regions of operation of a MOS transistor?
a. Cut off region
Here the current flow is essentially zero (accumulation mode)
b. Linear region
It is also called weak inversion region where the drain current is
dependent on the gate and the drain voltage w. r. to the substrate.
c. Saturation region
Channel is strongly inverted and the drain current flow is ideally
independent of the drain-source voltage (strong-inversion region).
5. Give the expressions for drain current for different modes of operation of
MOS transistor.
a. Cut off region
ID =0
b.Linear region
ID = kn [(VGS VT) VDS VDS2/2]
c. Saturation region
ID = (kn /2) (VGS VT) 2
6. Plot the current-voltage characteristics of a nMOS transistor.

7. Define accumulation mode.

The initial distribution of mobile positive holes in a p type silicon substrate of a
mos transistor for a voltage much less than the threshold voltage.
8. What are the secondary effects of MOS transistor?
a. Threshold voltage variations
b. Source to drain resistance
c. Variation in I-V characteristics
d. Subthreshold conduction
e. CMOS latchup
9. What is CMOS latchup? How it can be prevented?
The MOS technology contains a number of intrinsic bipolar transistors.These are
especially troublesome in CMOS processes, where the combination of wells and subtrates
results in the formation of p-n-p-n structures. Triggering these thyristor like devices leads
to a shorting of VDD & VSS lines, usually resulting in a destruction of the chip.
The remedies for the latch-up problem include:
i) an increase in substrate doping levels with a consequent drop in the value of
Rp subs.
(ii) reducing Rnwell by control of fabrication parameters and ensuring a low
contact resistance to VDD.
(iii) by introducing guard rings.

10. What are the different fabrication processes available to CMOS technology?
a. p-well process
b. n-well process
c. Twin-tub process
d. Silicon On Insulator (SOI) / Silicon On Sapphire (SOS) process
11. What are four generations of Integration Circuits?
SSI (Small Scale Integration)
MSI (Medium Scale Integration)
LSI (Large Scale Integration)
VLSI (Very Large Scale Integration)
12.Give the advantages of IC?
Size is less
High Speed
Less Power Dissipation
13.Give the variety of Integrated Circuits?

More Specialized Circuits

Application Specific Integrated Circuits(ASICs)

Systems-On-Chips

14.Give the basic process for IC fabrication

Silicon wafer Preparation
Epitaxial Growth
Oxidation
Photolithography
Diffusion
Ion Implantation
Isolation technique
Metallization
Assembly processing & Packaging

15.What are the various Silicon wafer Preparation?

Crystal growth & doping
Ingot trimming & grinding
Ingot slicing
Wafer polishing & etching
Wafer cleaning.
16.What are the secondary effects of MOS transistor?
a) Thresholdvoltagebodyeffect
b) Subthresholdregion
c) Channel length modulation
d) Fowler- Nordheim tunneling
e) Drain punch through effect
f) Impactionization
17.What is Channel-length modulation?
The current between drain and source terminals is constant and independent of
the applied voltage over the terminals. This is not entirely correct. The effective
length of the conductive channel is actually modulated by the applied V DS, increasing
VDS causes the depletion region at the drain junction to grow, reducing the length of
the effective channel.
18.What are the steps involved in twin-tub process?
Tub Formation
Thin-oxide Construction
Source & Drain Implantation
Contact cut definition
Metalization
19. What are the advantages of CMOS process?

Low power Dissipation

High Packing density

Bi directional capability

20. What are the different layers in MOS transistors?

Drain , Source & Gate
21.What is Enhancement mode transistor?
The device that is normally cut-off with zero gate bias.
22.What is Depletion mode Device?
The Device that conducts with zero gate bias.
23.When is the channel said to be pinched off?
If a large Vds is applied, this voltage with deplete the Inversion layer .This
Voltage effectively pinches off the channel near the drain.
UNIT II
1. Draw the circuit of an nMOS inverter?

2. Give the expression for pull-up to pull down ratio (Zpu/Zpd) for an nMOS
another nMOS inverter?

inverter driven by

3. Give the expression for pull-up to pull down ratio (Zpu/Zpd) for an nMOS inverter driven by
another nMOS inverter through number of pass transistor?

4. Draw the circuit of a CMOS inverter?

5. What are stick diagram?

It is used to convey the layer information through the use of colour codes. It is the Cartoon
of the chip layout.
6. Draw the stick diagram of 2-input nMOS NAND gate?

7. Draw the stick diagram of 2-input nMOS NOR gate?

8. Draw the stick diagram of nMOS inverter?

9. What is pull down device?

In CMOS inverter, if the input is high, then the nMOS will conduct and the pMOS does not
conduct, then the output pulls to ground. Thus the nMOS transistor is called as pull down device.
10. What is pull up device?
In CMOS inverter, if the input is low, then the pMOS will conduct and the nMOS does not
conduct, then the output pulls to VDD. Thus the pMOS transistor is called as pull up device.
11. What are the uses of stick diagram?
Stick diagram may be used to convey layer information through the use of
color codes.
It can be drawn much easier and faster than a complex layout.
These are especially important tools for layout built from large cells.

12.Give the various color coding used in stick diagram?

Green n-diffusion
Red polysilicon
Blue metal
Yellow implant
Black contact area

13.Draw the stick diagram of 2 inputs CMOS NAND gate?

14.Draw the stick diagram of 2 inputs CMOS NOR gate?

15) What are the two types of CMOS Design?

Static CMOS design
Dynamic CMOS design
16) What are the different color codes used for single polysilicon NMOS technology?

Green n-difference n+ active thinox

Red Polysilicon
Blue Metal 1
Black contact cut
Gray overglass
nMos only Yellow implant
nMos only Brown Buried contact

17) Draw the CMOS Logic gate for the function F=AB+C (A+B)

VDD

Vout
B

A
A

GND

18) What are design rules?

Design rules are the communication link between the designer
specifying requirements and the fabricator who materializes them. Design rules are
used to produce workable mask layouts from which the various layers in silicon will
be formed or patterned. The design rule conform to a set of geometric constraints or
rules specify the minimum allowable line widths for physical objects on chip such as
metal and polysilicon interconnects or diffusion area, minimum feature dimensions
and minimum allowable separations between two layers .

19) Give the different symbols for transmission gate?

20) What is Lambda () - based design rules?

These rules popularized by Mead and Conway are based on a single
parameter, , which characterizes the linear feature the resolution of the complete
wafer implementation process and permits first order scaling. They have been widely
used, particularly in the educational context and in the design of multiproject chips. In
lambda based design rules, all paths in all layers will be dimensioned in units and
subsequently . can be allocated an appropriate value compatible with the feature size
of the fabrication process. Design rules; specify line widths, separations, and
extensions in terms of
Lambda rules specify the layout constraints such as minimum feature sizes and
minimum allowable feature separation are stated in terms of single parameter and
thus allow linear proportional scaling of all geometric constraints.

21) What is meant by transmission gate?

The parallel connection of p and n channel MOSFET is called
transmission gate .The transmission gates are used to transmit the logical values
without any degradation. The Transistor connection for a complementary switch or
transmission gate is viewed in fig
S

V in

V out

S
It consists of an n channel transistor and a p channel transistor with separate gate
connection and common source and drain connection .The control signal is applied to
the gate of n device and its complement is applied to the gate of p device.
22) Define a super buffer?
A super buffer is a symmetric inverting or non inverting gate that
can supply or remove large currents and switch large capacitive loads faster than a
standard inverter. Basically a super buffer consists of a totem pole or push pull output
driven by an inverting or non inverting input that supplies the signal and its
complement to the totem pole. The super buffer speeds switching both ways and by
proper choice of geometry can be made almost independent of the inverter ratio.

UNIT III
1) What is meant by constant field scaling?
Constant field scaling maintains a constant electric field however its
dimensions are reduced by scaling.Here both the supply voltage and the device
dimensions are scaled by k, such that the electric field remains unchanged. This result in
scaling of drain current or current drive. At the same time gate capacitance is also scaled
due to reduced device size. This method of scaling provides a good framework for cmos
scaling without any degradation in its reliability.
i.e., tox=tox/k L=L/k W=W/k NA=NA.k VDD=VDD/k
2) What is meant by constant voltage scale?
Constant voltage scaling maintains a constant power supply voltage even though
its dimensions are reduced due to scaling. It is the most preferred method of scaling
because it provides much voltage compatibility as compared with older circuit
technologies .This method has the disadvantage that the electric field is increased as the
minimum featured length is reduced .This leads to velocity saturation, mobility
degradation, increased leakage currents and lower break down voltages.
i.e., tox=tox/k L=L/k W=W/k NA=NA/k VDD=VDD
3) What is meant by rise time?
Rise time t r is the time for the waveform to rise from 10% to 90% of its steady
state value. The rise time of a cmos inverter is primarily a function of the load
capacitances and the beta of the PMOS transistor p.
tr =4CL/ p. VDD , where CL= load capacitances
4) What is meant by fall time?
Fall time is the time taken for the waveform to fall from 90% to 10% of its steady
state value. The fall time is primarily a function of the betas of the NMOS transistor n.
tp =4CL/ n. VDD
5) What is propagation delay?
Propagation delay is the measure of the delay from the time that the input signal
reaches a 50% level to the time for the output to reach a 50% level. The propagation
delay for a cmos circuit can be calculated by
tdelay= (tr+ tp)/4

6) What are the various types of scaling available?

The various types of scaling are
a) Constant field scaling- Maintains a constant electric field even though its
dimensions are scaled down.
b) Constant voltage scaling- Maintains a constant power supply even though its
dimensions are scaled down.
7) What are the two components of power dissipation?
The two components in power dissipation are
a) Static power dissipation- due to the leakage current drawn from power supply.
b) Dynamic power dissipation- due to switching transient current and charging and
discharging of load capacitances.
8) What is meant by fault models?
Fault model is a model for how faults occur and their impact on the circuits.
The different types of fault model are
a) Stuck at zero or stuck at one-due to thin oxide shorts or metal-metal shorts.
b) Short circuit or open circuit faults.
9) What is meant by design margining?
There are three different sources of variation, two environmental and one
manufacturing .These are 1) operating temperature 2) supply voltage 3) process
variation .One must aim to design a circuit that will reliably operate over all extremes of
these three variables. Failure to do so invites circuit failure, potentially catastrophic
system failure, and a rapid decline in reliability.
10) A particular layer of MOS circuit has resistivity =1-cm.A section of this layer is
55m long and 5m wide and has a thickness of 1m. Calculate the resistance?
R= l/w.t
Or
R=1/Rs (l/t) where Rs- sheet resistance
R=15510^ (-6)/ (510^ (-6) 110^ (-6))
R=1110^ (6)
R=11 M

11) What is meant by charge sharing?

In many structures a bus can be modeled as a capacitor cb. Sometimes the
voltage on this bus is sampled (latched) to determine the state of a given signal.
Frequently this system can be modeled by two capacitors cb and cs and a switch.In
general cs is related to the switching element. The charge associated with each of the
capacitances prior to closing the switch can be described by
Qb = Cb Vb
Qs = Cs Vs

cb
cs

Vb

The total charge QT is given by

QT= CbVb+CsVs
and Total capacitance is given by
CT=Cb+Cs
Therefore when the switch is closed the resultant voltage is given by
VR=QT/CT = (CbVb+CsVs) / (Cb+Cs)
For eg:- if Vb=VDD
Then Vb> Vs and then
VR=VDD [Cb/ (Cb+Cs)]
To ensure reliable data transfer from Cb to Cs, it is necessary to ensure Cs<Cb. A useful
rule to follow is Cb>Cs*10.

12. What are the various types of scaling available.

Constant voltage scaling
Constant field scaling
Combined voltage and field scaling
13.How capacitive cross talk can be reduced.
Capacitive cross talk can be reduced by decreasing the distance between
two conductors , because capitance is increased with increase in distance .
14. Give the equation of total power dissipation.
The total power dissipation can be obtained by the sum of three dissipation
Components
Ptotal = Ps + Pd + Psc
15. How we can calculate the dynamic power.
percntage activity CTotal V DD
Pd =
tp

16.What are the factors including the electromigrating rate ?

Current desity
Temperature
Crystal structure
17.Write the equation for short circuit power dissipation
The equation for short circuit power dissipation is
Psc

t rf

(V DD 2Vt ) 3
12
p

18.Define static power dissipation .

The static power dissipation is the product of device leakage
current and the supply voltage.
19.Write the different delays occur in CMOS inverter.
Input wave form slope
Input capacitance
switch level R-C models
Macromodeling

20.Write the empirical delay model.

AP t dr spice

p
L

UNIT IV
1.Write the verilog code for shift register.
Verilog code for an 8-bit shift-left register with a positive-edge clock, serial in,
and serial out.
module shift (C, SI, SO);
input C,SI;
output SO;
reg [7:0] tmp;
always @(posedge C)
begin
tmp = tmp << 1;
tmp[0] = SI;
end
assign SO = tmp[7];
endmodule
2. Write the verilog code for 3-bit 1-of-9 Priority Encoder.
Verilog code for a 3-bit 1-of-9 Priority Encoder.
module priority (sel, code);
input [7:0] sel;
output [2:0] code;
reg [2:0] code;
always @(sel)
begin
if (sel[0]) code <= 3'b000;
else if (sel[1]) code <= 3'b001;
else if (sel[2]) code <= 3'b010;
else if (sel[3]) code <= 3'b011;
else if (sel[4]) code <= 3'b100;
else if (sel[5]) code <= 3'b101;
else if (sel[6]) code <= 3'b110;
else if (sel[7]) code <= 3'b111;
else
code <= 3'bxxx;
end
endmodule

3. Write the verilog code for for a tristate element.

module three_st (T, I, O);
input T, I;
output O;
reg O;
always @(T or I)
begin
if (~T)
O = I;
else
O = 1'bZ;
end
endmodule

4. Write the verilog code for the flip-flop with a positive-edge clock.
module flop (C, D, Q);
input C, D;
output Q;
reg Q;
always @(posedge C)
begin
Q = D;
end
endmodule
5. Write the verilog code for a 4-to-1 1-bit MUX using a Case statement.
module mux (a, b, c, d, s, o);
input a,b,c,d;
input [1:0] s;
output o;
reg o;
always @(a or b or c or d or s)
begin
case (s)
2'b00 : o = a;
2'b01 : o = b;
2'b10 : o = c;

default : o = d;
endcase
end
endmodule
6. Write the verilog code for a logical shifter.
module lshift (DI, SEL, SO);
input [7:0] DI;
input [1:0] SEL;
output [7:0] SO;
reg [7:0] SO;
always @(DI or SEL)
begin
case (SEL)
2'b00 : SO <= DI;
2'b01 : SO <= DI << 1;
2'b10 : SO <= DI << 2;
default : SO <= DI << 3;
endcase
end
endmodule
7. Write the verilog code for for a 1-of-8 decoder.
module mux (sel, res);
input [2:0] sel;
output [7:0] res;
reg [7:0] res;
always @(sel or res)
begin
case (sel)
3'b000 : res = 8'b00000001;
3'b001 : res = 8'b00000010;
3'b010 : res = 8'b00000100;
3'b011 : res = 8'b00001000;
3'b100 : res = 8'b00010000;
3'b101 : res = 8'b00100000;
3'b110 : res = 8'b01000000;
default : res = 8'b10000000;
endcase
end
endmodule

8. Write the verilog code for 4-bit unsigned up counter with asynchronous clear.
module counter (C, CLR, Q);
input C, CLR;
output [3:0] Q;
reg [3:0] tmp;
always @(posedge C or posedge CLR)
begin
if (CLR)
tmp = 4'b0000;
else
tmp = tmp + 1'b1;
end
assign Q = tmp;
endmodule
9. Write the verilog code for a 4-bit unsigned down counter with synchronous set.
module counter (C, S, Q);
input C, S;
output [3:0] Q;
reg [3:0] tmp;
always @(posedge C)
begin
if (S)
tmp = 4'b1111;
else
tmp = tmp - 1'b1;
end
assign Q = tmp;
endmodule
10. Write the verilog code for a 4-bit unsigned up counter with asynchronous clear and
clock enable.
IO Pins Description
C

Positive-Edge Clock

CLR

Asynchronous Clear (active High)

CE

Clock Enable

Q[3:0]

Data Output

module counter (C, CLR, CE, Q);

input C, CLR, CE;
output [3:0] Q;
reg [3:0] tmp;
always @(posedge C or posedge CLR)
begin
if (CLR)
tmp = 4'b0000;
else
if (CE)
tmp = tmp + 1'b1;
end
assign Q = tmp;
endmodule
11 Write the Verilog code for a 4-bit unsigned up accumulator with asynchronous
clear.
module accum (C, CLR, D, Q);
input C, CLR;
input [3:0] D;
output [3:0] Q;
reg [3:0] tmp;
always @(posedge C or posedge CLR)
begin
if (CLR)
tmp = 4'b0000;
else
tmp = tmp + D;
end
assign Q = tmp;
endmodule
12,Write the verilog code for encoder.
IO pins Description
s[2:0]

Selector

res

Data Output

Following is the Verilog code.

module mux (sel, res);

input [2:0] sel;
output [7:0] res;
reg [7:0] res;
always @(sel or res)
begin
case (sel)
3'b000 : res = 8'b00000001;
3'b001 : res = 8'b00000010;
3'b010 : res = 8'b00000100;
3'b011 : res = 8'b00001000;
3'b100 : res = 8'b00010000;
3'b101 : res = 8'b00100000;
// 110 and 111 selector values are unused
default : res = 8'bxxxxxxxx;
endcase
end
endmodule
13.What is meant by floor planning
Floor planning is to arrange the blocks inside the chip .
14.Write the different types of floor planning.
different types of floor planning are
Sliceable floor plan
Non-sliceable floor plan
15.Define sliceable floor plan
Sliceable floor plan is defined as either a single module or a floor
plan that can be partitioned in to modules using the vertical or horizontal lines.
16.Define Non-sliceable floor plan.
We can devide the floor plan without cutting the blocks
17.Define vector.
A vector is an array of binary inputs that are applied to the device under test
or the chip under test.
18.What is meant by functional testing.
Functional testing is used to determine whether a chip is good or
bad by forcing the circuit to perform various functions and checking the response.
19.Write the types of faults
1) stuck-at-0 fault
2) stuck-at-1 fault
20.What are the various testing available in CMOS.
Gate level testing
IDDQ testing

UNIT V
1. Write the acronym for verilog?
Verilog HDL is a hardware description language that can be used to model a
digital system at many levels of abstraction ranging from the algorithmic level to the gate
level to the switch level.
12. What are the various modeling used in verilog?
There are four types of modeling and they are
Circuit level modeling
Gate level modeling
Dataflow modeling
Behavioral level modeling
13. What is the structural gate-level modeling?
Designing the logic circuit in terms of basic gates. All the basic gates are available
as modules called primitives. Each primitive is defined in terms of inputs and outputs is
called structural gate level modeling.
14. What is switch-level modeling?
Designing leaf-level module such as MOS transistor, CMOS transistor is called
switch level modeling. Switch level modeling forms the basic level of modeling digital
circuits.
15. What are identifiers?
Identifiers are names given to objects so that they can be referenced in the design.
An identifier in verilog HDL is any sequence of letters, digits, $ character and the
underscore with the restriction that first character must be a letter or an underscore.
Identifiers are case-sensitive.
E.g., abar
ABAR
_x2
16. What are the value sets in verilog?
Verilog has a predefined-value system or value set that supports four values to
model the functionality. They are
Value level
Condition in hardware circuit
0
Logic zero, false condition

1
x
z

Logic one, true condition

Unknown logic value
High impedance, floating state

7. Give the different arithmetic operators?

Operator type
Arithmetic operation in
verilog on vectors is
predefined. If any operand
bit has a value x, then the
result of the entire
expression is x.

Operator
symbol
*

Operation performed

Divide

Add

Subtract

Modulus

**

Power
(exponent)

8. What are the different bitwise operators?

Operator type
Operator
symbol
Bitwise operators
~
perform a bit-by-bit
&
operation on two
\
operands. They take each
bit in one operand and
^
perform the operation
with the corresponding bit
^~ or ~^
in the other operand.

Multiply

Operation performed
Bitwise negation
Bitwise AND
Bitwise OR
Bitwise XOR
Bitwise XNOR

9. What are gate primitives?

Circuit is described in terms of gates. Here is an example for gate primitives
nand g1 (o, a, b)

nand=>gate type
g1=>instance name
o=>output terminal
a, b=>input terminals
10. Write the expression for carry look ahead adder?
Sum= A xor B xor Cin
Carry= (A and B) or (A and Cin) or (B and Cin)
11. Give the two blocks in behavioral modeling.
1. An initial block executes once in the simulation and is used to set up
Initial conditions and step-by-step data flow
2. An always block executes in a loop and repeats during the simulation.
12. What are the types of conditional statements?
1. No else statement
Syntax: if ([expression]) true statement;
2. One else statement
Syntax: if ([expression]) true statement;
Else false-statement;
3. Nested if-else-if
Syntax : if ( [expression1] ) true statement 1;
else if ( [expression2] ) true-statement 2;
else if ( [expression3] ) true-statement 3;
else default-statement;
The [expression] is evaluated. If it is true (1 or a non-zero value) true-statement is
executed. If it is false (zero) or ambiguous (x), the false-statement is executed.
13. Name the types of ports in Verilog
Types of port

Keyword

Input port

input

Output port

output

Bidirectional port

inout

14. What are the types of procedural assignments?

Assignments made inside procedural blocks are called procedural assignments.
1. Blocking assignment
2. Non-blocking assignment
Blocking assignments are executed in the order they are coded. Hence they are
sequential. Since they block the execution of the next statement, till the current statement
is executed, they are called blocking assignments. Assignments are made with =
symbol.
Eg: a=b
Non blocking assignments are executed in parallel. Since the execution of the
next statement is not blocked due to the execution of current statement, they are called
non blocking assignments. Assignments are made with <= symbol.
Eg: a<=b
15. Write the difference between task and function
FUNCTION
1. A function can enable another

TASK
1. A task can enable other task and

function but not another task.

function.

2. Functions always execute in 0

2. Task may execute in non zero

simulation time.

simulation time.

3. Functions must not contain any delay, 3. Task may contain any delay, event or
event or timing control statements.

timing control statements.

4. Functions may have at least one input

4. Task may have zero or more

arguments. They can have more than

arguments of type input, output or in

one input.

out.

5. Functions always return a single

5. Task do not return with a value, but

value. They cannot have output or input

can pass multiple values through output

arguments.

and in out arguments.

16. What is meant by test bench?

A test bench is a virtual environment used to verify the correctness or soundness of
a design or model.
17.Write the difference between data flow and behavioral modeling
DATA FLOW MODELING
1. The data flow model is written as asset

BEHAVIORAL MODELING
1. The behavioral model is written as a set

of concurrent assignment statements.

of sequential assignment statements.

2. 2.A data flow model has no process

2. A behavioral model has one or more

statements.

process statements each with a sensitivity

unit.

3. The data flow model is not able to

3. The behavioral model enables to

describe the system at a high level of

describe the system at a high level of

abstraction. It is more restrictive than

abstraction.

behavioral modeling.
4. The statements are evaluated

4. The statements are evaluated

concurrently.

sequentially.

ALL POSSIBLE SIXTEEN MARK QUESTIONS

1. Derive the equation for Threshold voltage.

Thershold voltage equation is the combination of threshold
voltage of the MO S capacitor and the ideal flat band voltage
2.Explain Body effect
ThethresholdvoltageVTisnotaconstantwithrespecttothe
voltagedifferencebetweenthesubstrateandthesourceoftheMOStransistor.This
effectiscalledthebodyeffectorsubstratebiaseffect.
3.Explain the saturation and linear region

1.Linearregion
Itisalsocalledweakinversionregionwherethedraincurrentisdependent
onthegateandthedrainvoltagew.r.tothesubstrate.
2.Saturationregion
Channelisstronglyinvertedandthedraincurrentflowisideallyindependent
ofthedrainsourcevoltage(stronginversionregion).
4 .what is meant by transconductance give its equation
Tranconductance is defined as the ratio of output current to input
voltage
5. Explain any four second order effects in MOS in detail.
a. Thresholdvoltagebodyeffect
b. Subthresholdregion
c. Channel length modulation
d. Fowler- Nordheim tunneling
6. Draw the small signal model for MOS and explain its parameters.
Small signal model of the MOS consists of transconductance , output
resistance and the input resistance
7. Draw the circuit of a nMOS inverter.

8. Derive the expression for pull-up to pull-down ratio (Zpu/ Zpd) for an nMOS
inverter driven by another nMOS inverter.
Vinv= VT- VTH

9. Derive the expression for pull-up to pull-down ratio (Zpu/ Zpd) for an nMOS
inverter driven by another nMOS inverter through number of pass inverter.
Z p.u .2
Z p.u .1

Z p.u .1
Z p.d .1

(V DD Vt )
(V DD Vtp Vt )

10. Explain transmission gate.

Transmission gate is formed by the parallel combination of NMOS and
PMOS transistor.
11. Explain stick diagrams.
Stick diagrams are rhe cartoon of the chip layout .
12. Explain CMOS super buffer
ACMOSsuperbufferisasymmetricinvertingornoninvertinggate
thatcansupplyorremovelargecurrentsandswitchlargecapacitiveloadsfaster
thanastandardinverter
13. Explain NMOS super buffer
ANMOSsuperbufferisasymmetricinvertingor
noninvertinggatehatcansupplyorremovelargecurrentsandswitchlargecapacitive
loadsfasterthanastandardinverter.
14. Explain about resistance estimation.
Resistance may be estimated by means of simple resistance
equation
15 .What is meant by scaling .Explain its parameters.
Scaling is used to reduce the dimension.
16. Explain charge sharing in detail.
In many structures a bus can be modeled as
a capacitor cb. Sometimes the voltage on this bus is sampled (latched) to
determine the state of a given signal. Frequently this system can be modeled by
two capacitors cb and cs and a switch.In general cs is related to the switching
element.
17. What are the various types of power dissipation in CMOS inverter.Explain any
one in detail.
The various types of power dissipation in CMOS inverter are static
and dynamic power dissipation.

17. Explain the 4:1 multiplexer in detail.

The 4:1 multiplexer consists of 4 input 1 output and 2 select lines
18. Briefly explain the comparator.
Two words are compared by means of comparator.
20.What is meant by shift register write its verilog code.
The shift register is used for shifting operation.
21.Draw the models for cross talk.
The cross talk model consists of parasitic capacitance
22.Explain the term floor planning
Floor planning is used to allocate the blocks inside the chip.
23.What are the high speed adders .Explain any one high speed adder with neat
diagram.
The high speed adders are carry look ahead adder, carry select
adder,carry save adder and conditional sum adder.
24.Explain the hierarchical design.
The hierarchical design consists of top down methodology and bottom up
methodology.
25. Differentiate tasks and functions.
FUNCTION
TASK
1. A function can enable another
1. A task can enable other task and
function but not another task.

function.

2. Functions always execute in 0

2. Task may execute in non zero

simulation time.

simulation time.

3. Functions must not contain any delay, 3. Task may contain any delay, event or
event or timing control statements.

timing control statements.

4. Functions may have at least one input

4. Task may have zero or more

arguments. They can have more than

arguments of type input, output or in

one input.

out.

5. Functions always return a single

5. Task do not return with a value, but

value. They cannot have output or input

can pass multiple values through output

arguments.

and in out arguments.

26. Derive the CMOS inverter DC characteristics and obtain the relationship for
output voltage at different region in the transfer characteristics.

27. Explain the various second order effects affeecting the operation of a MOSFET.
a. Thresholdvoltagebodyeffect
b. Subthresholdregion
c. Channel length modulation
d. Fowler- Nordheim tunneling
e. Drain punch through effect
f. Impactionization
28. With appropriate illustrations explain P-well CMOS process.
In the P-well CMOS process P-well is formed
29. With appropriate illustrations explain N-well CMOS process
In the N-well CMOS process n-well is formed
30. With appropriate illustrations explain twin tub CMOS process
In the Twin-tub CMOS process P&N-well is formed
31. With neat diagrams explain SOI process.
No well formation in the SOI process.
32. Explain the operation of PMOS Enhancement transistor.
PMOS Enhancement transistor voltage appled to gate and drain are
negative.

33. Explain the operation of NMOS Enhancement transistor.

NMOS Enhancement transistor voltage appled to gate
and drain are positive.
34. Explain the switching time for NAND gate.
Switching time for NAND gate is used to find out the delay time and
rise time.
35. Explain the switching time for NOR gate.
Switching time for NOR gate is used to find out the delay
time and rise time.
36. Find out pull-up to pull-down ratio (Zpu/ Zpd) for an nMOS inverter driven by
another nMOS inverter through number of pass inverter.
Z p.u .2
Z p.u .1

Z p.u .1
Z p.d .1

(V DD Vt )
(V DD Vtp Vt )

37. Explain the dynamic CMOS design in detail.

A Dyamic CMOS circuit provide lower power dissipation
than static CMOS.
38. Explain capacitance estimation with neat diagram
Using capacitance estimation we can find out the various parasitic
capacitance present in the MOS transistor.
39. Explain the switching characteristics of CMOS inverter.
switching characteristics is used to find out rise time , delay
time
40. Explain the following in detail. Delay time calculation, Static power dissipation
Delay time calculation, Static power dissipation
41. Explain the dynamic power dissipation with appropriate models.
Explain the dynamic power dissipation
42. Explain the design margining in detail.
i. Operating temperature.
ii. Supply voltage
iii. Process variation
43. Explain the stick encodings used for NMOS and CMOS p-well process.
Stick encoding is the colour coding, which is the cartoon of chip
layout.
44. Explain the ripple carry adder
Summing the number of full adders form the ripple carry adder.

45. Explain the basics of CMOS testing.

CMOS testing is used to findout various faults present in the
CMOS circuits.
46. Explain the carry look ahead adder and write its verilog code.
CLA is the high speed adder ,which consists of generate aswellas
propagate carry terms
47. Explain task in detail?
. A task can enable other task and function. Task may execute in non zero
simulation time.
48. Explain functions in detail?
A function can enable another function but not another task.Functions always
execute in 0 simulation time.
49. Explain the gate level modeling with one example.
The program is written with respect to number of logic gates
present.
50. Explain the behavioral modeling with one example.
The program is written with respect to behaviour of the circuit