S-R Flip-Flop:

JK Flip Flop:

Truth Table for JK Flip Flop

Cloc

0
0

Same as
Previous

Latch

State

for SR

Not Permitted

Experiment: 4

Date:
VERIFICATION OF FLIP FLOPS

Aim:
To study the truth tables of various flip flops and verify them experimentally using
appropriate integrated circuits.
Apparatus Required:
S.No
1.
2.
3.
4.
5.
6.

Component Name
OR Gate
NOT Gate
NAND Gate
NOR Gate
IC Trainer Kit
Connecting Wires

Part No/Range
IC 7432
IC 7404
IC 7400
IC 7402
-

Quantity in Nos
1
1
1
1
1
As required

Theory:
S-R Flip-flop:
In SR flip flop S and R stand for set and reset. It can be constructed from a pair of crosscoupled NOR logic gates. The stored bit is present on the output marked Q. While the S and R
inputs are both low, feedback maintains the

and

outputs in a constant state, with

the

complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output is
forced high, and stays high when S returns to low; similarly, if R is pulsed high while S is held
low, then the Q output is forced low, and stays low when R returns to low.
The R = S = 1 combination is called a restricted combination or a forbidden state
because, as both NOR gates then output zeros, it breaks the logical equation Q = not

. The

combination is also inappropriate in circuits where both inputs may go low simultaneously. The
output would lock at either 1 or 0 depending on the propagation time relations between the gates
(a race condition). Although this condition is usually avoided, it can be useful in some
applications.

JK Flip Flop:
The JK flip-flop is basically a gated SR flip-flop with the addition of a clock input circuitry that
prevents the illegal or invalid output condition that can occur when both inputs S and R are equal
to logic level "1". Due to this additional clocked input, a JK flip-flop has four possible input
combinations, "logic 1", "logic 0", "no change" and "toggle". Both the S and the R inputs of the
previous SR bistable have now been replaced by two inputs called the J and K inputs,
respectively. The two 2-input AND gates of the gated SR bistable have now been replaced by
two 3-input NAND gates with the third input of each gate connected to the outputs at Q and Q.

This cross coupling of the SR flip-flop allows the previously invalid condition of S = "1" and R =
"1" state to be used to produce a "toggle action" as the two inputs are now interlocked. If the
circuit is "SET" the J input is inhibited by the "0" status of Q through the lower NAND gate. If
the circuit is "RESET" the K input is inhibited by the "0" status of Q through the upper NAND
gate. As Q and Q are always different we can use them to control the input. When both inputs J
and K are equal to logic "1", the JK flip-flop toggles as shown in the truth table.
Pre-Lab Questions:
1. Define flip-flop
2. Explain the flip-flop excitation tables for D flip-flop
3. Explain the flip-flop excitation tables for JK flip-flop
4. What is a master-slave flip-flop?
5. What is edge-triggered flip-flop?
6. What are the different types of flip-flop?
7. Draw the logic diagram of three bit ring counter.

8. Write the characteristic equation of JK and D flip-flop.

9. Define glitch.
10. Write the excitation tables of JK and D flip-flops.
Procedure:
1. Connections are made as shown in the logic diagram.
2. The input clock pulse are applied from digital trainer and the corresponding output logic levels
are checked through LEDs.
3. The workings of flip-flops are verified using truth table.
Result:
Max.
Assessment

Mark

Preparation
Performance
Record
Total

s
30
30
40
100

Mark
s

Post-Lab Questions:
1.
2.
3.
4.
5.

What is race around condition?

What is the operation of D flip-flop?
Design a synchronous decade counter using D flip flop.
State the advantages of a master slave JK flip flop
Distinguish between synchronous and asynchronous sequential circuits.

6. Convert an SR flip-flop to D flip-flop.

7. List out the limitations of SR flip-flop.
8. Convert a D flip flop into a T flip flop.
9. How can the race conditions be avoided in flip-flops?
10. If the input frequency of a T flip flop is 1600 KHz, what will be the output frequency?
Give reason for your answer.