Kuwait University

Computer Engineering Department

Computer Architecture Lab
Lab 2: Introduction to the MIPS Processor

1. LEARNING OBJECTIVES

Familiarizing the student with Quartus II Software.

Reviewing the concept of modularity.

Improving the ability of designing in the behavioral level.

Reviewing the MIPS processor instruction set.

2. THE MIPS PROCESSOR

MIPS is a reduced instruction set computer (RISC) developed by MIPS Technology. It is
widely used in many different fields such as gaming consoles (PS2), embedded systems (Windows
CE Mobiles) and in network components (router and gateways). The reason of its wide usage is the
generality of its instructions set and its simple architecture. There are several different
implementations for this processor. Single-cycle implementation, multi-cycles implementation and
pipelined implementation.
Our concentration in this lab will be in developing both the single-cycle and pipelined 16Bits MIPS computers. Both use almost the same components.

2.1. The Instruction Set

Although, as mentioned, the general MIPS architecture provides a large set of instructions
for integer and floating-points operations, we are going to concentrate only on a small set of integer
operation due to the complexity of the floating points systems. Before discussing the instruction set,
we have to define the general instruction formats. There are three general formats used in our MIPS
processor:
1. R-Type Format:
Opcode
15

rs
12

11

rt
9

rd
6

Function
3

2. I-Type Format:
Opcode
15

rs
12

11

rt
9

immediate
6

3. J-Type Format:
Opcode
15

immediate
12

11

The fields can be explained as follows:

1. Opcode: the instruction specifier. It is used mainly by the processor controller to
differentiate the path each instruction takes.
2. rd, rs and rt: theses are registers indices. rd is the destination of the R-type
instructions. rs is a source. rt is a source for the R-type and destination for the IType. An Exception is the BEQ instruction where the rt is a source.
3. Function: specifies the operation that will be executed in the ALU. Used to simplify the
controller logic.
4. Immediate of I-Type: a constant used for the following:
a. For the immediate instructions, it is used as an operand for an arithmetic or
logical operation.
b. For the memory instructions, it is used to calculate the address of the memory
wanted.
c. For the branch, it is used as the branch address.
5. Immediate of J-Type: a constant used only in the jump instructions as the jump address.
The instruction set we are going to implement in this lab is shown in Table 1.

Instruction Name

Type

Opcode/Functio
n

and

R-type

(0001)2 / (000)2

R[rd] = R[rs] & R[rt]

or

R-type

(0001)2 / (001)2

R[rd] = R[rs] | R[rt]

xor

R-type

(0001)2 / (010)2

R[rd] = R[rs] ^ R[rt]

not

R-type

(0001)2 / (011)2

R[rd] = ~ R[rs]

srl

R-type

(0001)2 / (100)2

R[rd] = R[rs] >> 1

add

R-type

(0001)2 / (110)2

R[rd] = R[rs] + R[rt]

sub

R-type

(0001)2 / (111)2

R[rd] = R[rs] - R[rt]

addi

I-type

(0010)2

R[rt] = R[rs] + SignExtImm

I-type

(0011)2

R[rt] = M [ R[rs] + SignExtImm ]

I-type

(0100)2

M [ R[rs] + SignExtImm ] = R[rt]

I-type

(0101)2

if ( R[rs] == R[rt] )
PC = PC + 1 + SignExtImm

jmp
(jump)

J-type

(0110)2

PC = JumpAddress

jal (jump
and link)

J-type

(0111)2

ret
(return)

J-type

(1000)2

(shift right logically)

(add immediate)

lw
(load word)

sw
(store word)

beq
(branch equal)

Operation

R[7] = PC + 1; PC = JumpAddress

SignExtImm = {10{immediate[5]}, immediate}

JumpAddress = { PC+1[15:12], immediate}
Table 1. The Instructions Set

PC = R[7]

2.2. The MIPS Main Components

In any processor, there are three components that can be considered as the main
components: the ALU, the register file and the controller. As we discussed the ALU
in the previous lab, here we are going to discuss the register file and the controller of
the MIPS processor in the following subsections.
2.2.1. The Register File
The register file is the fastest location that can be used to store or access data in the
computer system. It is usually used to store values needed to be manipulated
frequently by the processor. As in MIPS processor, some of the processors restrict
most of their operations operands to be only registers. Thats to guarantee the speed of
the instructions execution.

Figure 1. The Register File

Our MIPS register file consists of 8 registers that are available to be read from, and
written on. There are 6 inputs for this sequential circuit: ai (3 bits), bi (3 bits), c (3
bits), data (16 bits), write (1 bit) and the clock (1 bit). The outputs are A (16 bits) and
B (16 bits). The following explains the role of these ports:
1.

ai selects register to be read on bus A.

2.

bi selects register to be read on bus B.

3.

c selects the register to be written to.

4.

data is the 16-bit data to be written to the register specified by c when write is
1 (at negative edge of the clock).

5.

write is the signal that enables writing to the register file.

6.

clock is the clock signal that enables writing to a register.

7.

A and B are 16-bit output buses for reading two registers.

For every clock cycle, there will be outputs from the register file regardless of the
instruction that is being executed. The registers in the register file must be negative
edge flip-flops. The reason of that will be explained in lab 5.

2.2.2. The Control Unit

The control unit is the main component in any processor. Its main role is to specify
the path that the data takes for each instruction. There are several types of controllers
exists in the processors. Depend on the application the processor used for and the
whole processor architecture; the controller can take many different shapes. For
single-cycle architecture, the processor is just a combinational circuit. While for a
multi-cycle version, its usually a state machine. For processor that needs to be
flexible in its instruction set, the controller must micro programmed. The micro
programmed controller uses an internal memory to store the signals for each
instruction in each cycle. This memory can be reloaded with different signals any
time.

Figure 2. The control unit

In our MIPS single cycle, the controller is hardwired combinational circuit. The unit
receives 4-bits opcode and has a 11 control signals as outputs. The specification of the
control signals is described in Table 2.

Control Signal

Functionality

RegDst

Specifies whether to use rt or rd

as the destination register

Branch

Turns on branch logic

Values
0: use rt
1: use rd
1: beq comparator drives the PC
input
0: the beq comparator does not do
anything
0: do not read from memory

MemRead

Loads data from memory

1: read from memory
00: ALU

MemToReg

Specifies the source of data to be

written to the register file

01: Memory
10: PC + 1
11: nothing

ALUop

MemWrite

ALUSrc

RegWrite

Jump

Specifies
the
operation
performed in ALU (addition or
operation specified in function
field)
Enables writing data to memory

00: Function field

01: addition
0: no write to memory
1: write to memory

Specifies the second operand of the 0: R[ rt ]

ALU
1: SignExtImm
Enables writing data to register file
Loads the JumpAddress to the
PC

Ret

Loads R[7] to the PC

Jal

Specifies R[7] as destination

register

0: do not write to register file

1: write to register file
0: do not load
1: load JumpAddress to PC
0: do not load
1: load R[7] to PC
0: use either rd or rt
1: use R[7] as destination register

Table 2. The control signals functionalities

LAB EXERCISE #2:

BUILDING THE REGISTER FILE AND CONTROL UNIT OF THE MIPS
PROCESSOR
Name:
ID:

Section:

1. PROBLEM STATEMENT
1.1. The MIPS register file
Design and implement the MIPS register file specified in subsection 2.2.1. The register file
is a sequential circuit that contains 8 registers. It outputs two of its registers contents continuously
using ai and bi indices. The C is used to specify the register to be written with the port d
content. You have to implement it using verilog design language.

1.2. The Mips Control Unit.

Design and implement the MIPS control unit specified in subsection 2.2.2. The control unit
is a combinational circuit that outputs 11 control signal specifies in table 2.

2. DESIGN PROCEDURE
1. Open the project created in the previous lab.
2. Create a new verilog file and call it RegisterFile.
3. Specify the ai, bi, C, d, clk, and write as inputs and A and B as outputs.
4. There are two logical parts in the register file. The first part derives the output ports, A
and B, by the ai" and bi indices. The second part writes the data d to R[C] if the
write signal is asserted. This part is triggered by the negative edge of clk. You have
to implement these two parts separately.
5. After you finish writing the code, compile and simulate the design using vector
waveform file. The vector waveform must be similar to what is shown in Figure 1.

Figure 1. A register file simulation sample.

6. Create a new verilog file and call it ControlUnit.

7. Specify the opcode as input and the control signals as outputs.
8. The whole control unit is derived by the opcode. You have to initialize the
whole signals by 0. For each opcode, you have to check the signals that needs
to be changed from 0.
9. After you finish writing the code, compile and simulate the design
using vector waveform file.

3. WHAT TO SUBMIT
1. Th Exercise Sheet.
2. The verilog files, commented with your names.
3.

The vector waveform simulation files.