Dr.

Abhishek Dutta
Interfacing with the ISA Bus

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Abstract: Parallel port is the most popular choice for interfacing. The 8 data output lines and sometimes the CONTROL
and STATUS ports of the parallel port, used to feed data into the computer, are not sufficient for some complex projects.
Some projects require more data I/O lines. This project shows how to get 32 general purpose I/O lines by interfacing the
ISA Bus. Though PCI bus can be a candidate for interfacing experiments, its greater speed and feature rich nature
poses great complexity in terms of hardware and software to beginners. So this project can be a stepping stone to those
think ing of ultimately getting to PCI Bus for interfacing experiments. This project can also be useful for those think ing of
mak ing Digital Oscilloscope using PC, A/D and D/A converters, Microcontroller programmer, etc.

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NOTE: This article was published in March 2006 issue of linuxgazette

Before going into the details of the full project of interfacing the ISA Bus, we have to get familiar with some details given
below:

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We have considered X(n) as the side that contains components in any

standard ISA cards. Similarly, Y(n) is the side that contains the solder. It is
very important for you to be clear of the above convention. You will damage
your motherboard if you connect just the other way.
The description for most commonly used pins are given below:

SIDE X
D0 D7 (pins X2 to X9)
They are the 8 data lines representing the 8-Bit data bus.
A0 A19 (pins X31 to X12)
They are the 20 address lines that contain the address bits. This
address bus can address 1MB (2^20=1024 Kbytes)
AEN (pin X11)
It is used by the DMA controller to tak e over to data and address bus
during DMA transfer.

Side Y
GND (pins Y1,Y10,Y31)
They are connected to ground of computer.
+5V (pin Y3)
+5 Volt DC output
-5V (pin Y5)
-5 Volt DC output
+12V (pin Y9)
+12 Volt DC output
-12V (pin Y7)
-12 Volt DC output
MEMW(pin Y11)*
The microprocessor mak es this line LOW while doing WRITE TO MEMORY.
MEMR (pin Y12)*
The microprocessor mak es this line LOW while doing READ FROM MEMORY.
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IOW (pin Y13)

The microprocessor mak es this line LOW while doing WRITE TO PORT. (eg: when you write
outportb(ADDRESS,BYTE), this line becomes LOW)
IOR (pin Y14)
The microprocessor mak es this line LOW while doing READ FROM PORT. (eg: when you write byte =
inportb(ADDRESS), this line becomes LOW)
DACK0 DACK3 (pins Y19,Y17,Y26,Y15)*
The DMA controller signals on these lines to let devices k now that that DMA has the control of buses.
DRQ1 DRQ3 (pins Y18,Y6,Y16)*
These pins allows the peripheral boards to request the use of the buses.
T/C (pin Y27)*
The DMA controller sets this signal to let the peripheral k now that the programmed number of bytes has been sent.
IRQ2 IRQ7 (pins Y4,Y25,Y24,Y23,Y22,Y21)*
Interrupt Signals. The peripheral devices set these signals to request the attention of the microprocessor.
ALE (pin Y28)*
Address Latch Enable. This signal is used by the microprocessor to lock the 16 lower address bus in a latch during
a memory or port input/output operation.
CLOCK (pin Y20)*
The system clock
OSC (pin Y30)*
It is a high frequency clock which can be used for the I/O boards.
* these pins will not be used in this project

Getting Four Output lines our of a ISA Bus

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Before going into the details of full project lets explain the part that handles the four 8-Bit output lines only. The
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addresses in the range 0x338 to 0x33B was not used by any devices for input output operations in our computer.
The three 74LS138 ICs handle the address decoding part. We have connected the address lines in a way such that there
is short pulse (CLOCK) in the wires (represented by green wire) whenever the address lines contains the address in the
range 0x338 to 0x33B and port output (IOW) is requested.
Whenever the 74LS374 get a CLOCK PULSE it latches-in the 8-Bit data present in the data bus. 74LS245 is a 3-STATE
Octal Bus Transreceiver. It reduces DC loading on the data bus and allows isolation of data bus when required.
To know that I/O port address are available for use in this project we examine the contents of ioports in the /proc
directoryof our linux system.
[root@thelinuxmaniac~]# cat /proc/ioports
0000-001f: dma1
0020-0021: pic1
0040-0043: timer0
.......................
.......................
01f0-01f7: ide0
0378-037a : parport0
037b-037f : parport0
03c0-03df : vga+
.......................
.......................
It is clear from the above output that the addresses 0x238-0x23B and 0x338-0x33B are not being used by any device.
Usually this is the case in most computers. However, if this address is occupied by some device, then you have to
change the wiring of address lines to three 74LS138 IC (used for address decoding).We describe the address decoding
technique here briefly so that you can setup unique address for I/O device we are trying to build according to the nonused address available in your computer.

ADDRESS DECODING
We use 74LS138, 3-to-8 multiplexer for address decoding. Suppose we want to assign the addresses 0x338-0x33B for
four 8-Bit output lines and 0x238-0x23B for four 8-Bit input lines.The binary equivalent of these addresses are:
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Address
0x338
0 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0
0x339
0 0 0 0 0 0 1 1 0 0 1 1 1 0 0 1
0x33A
0 0 0 0 0 0 1 1 0 0 1 1 1 0 1 0
0x33B
0 0 0 0 0 0 1 1 0 0 1 1 1 0 1 1
0x238
0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 0
0x239
0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 1
0x23A
0 0 0 0 0 0 1 0 0 0 1 1 1 0 1 0
0x23B
0 0 0 0 0 0 1 0 0 0 1 1 1 0 1 1
Address Lines A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0
We observe that address lines A 8A 1A 0 only change in case of all the eight addresses. The whole process of connecting
wires to 74LS138 IC is like solving a puzzle. Connect the remaining wires ( A 15A 14A 13A 12A 11A 10A 9A 7A 6A 5A 4A 3A 2) to
two 74LS138 such that they finally give low output when these lines have the address bits that partially match our
addresses (except A 8A 1A 0 ).Now we connect the remaining lines (A 8A 1A 0 A 2) to the third 74LS138.All the 8 outputs of
this IC is used to select the 74LS374 latches corresponding to input and output addresses after it is NORed with IOR and
IOW using 74LS02 to distinguish between memory IO and port IO addressing.
74LS138 Truth Table
G1 G2 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X H XXXH H H H H H H H
L X XXXH H H H H H H H
H L LLLL H H H H H H H
H L L L HH L H H H H H H
H L L HL H H L H H H H H
H L L HHH H H L H H H H
H L HL L H H H H L H H H
H L HL HH H H H H L H H
H L HHL H H H H H H L H
H L HHHH H H H H H H L
Refer to datasheet of 74LS138 for details

The Real Stuff

Now we are ready to describe the functioning of the complete circuit that will give us 32 general purpose I/O lines.

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Description of ICs used in this project

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74LS138 and 74LS139

Decoders/De-multiplexers.Used for Address Decoding
74LS245
Octal 3-STATE Buffer/Line Driver/Line Receiver
74LS374
Octal Transparent Latch with 3-STATE outputs; Octal D-TYPE FLIP-FLOP with 3-STATE output
74LS02
QUAD 2-INPUT NOR gate
The three 74LS138 IC are used for address decoding along with the two 74LS02(2 input NOR gate). Whenever a match is
found in the address lines, the respective output line, Y(x) of the third 74LS138 IC (connected to the two 74LS02 IC), gets
LOW. These lines along with IOW (and IOR) are connected to the NOR gates (74LS02), which gives HIGH only when the
two inputs go LOW simultaneously.
Hence,the output is high only when:
1. a match is found in the address lines
2. the IOW or IOR lines go LOW, representing the PORT IO operation.
Remember,if we do not consider the second case, our device will conflict with the memory IO operations in the addresses
0x238-0x23B and 0x338-0x33B.
We can see in the circuit diagram that the output lines of NOR gates are connected to the CLOCK pins of 74LS374 latch
(represented by green wires).So whenever the above two cases match simultaneously, CLOCK pulse is sent to the
respective latch and the data in the data bus is latched-in which appears in the output lines.

Coding controlling the I/O lines using C

isa.c illustrates the some simple coding methods to control and test the I/O lines of the device created in this project.
if(ioperm(OUTPUT_PORT,LENGTH+1,1))
{
...
}
if(ioperm(INPUT_PORT,LENGTH+1,1))
{
...
}
outb(data,port);
data = inb(port);
ioperm() gets the permission to access the specified ports from the kernel. outb() and inb() functions defined in sys/io.h
helps us write and read to specified port.

SOME DEBUGGING TECHNIQUES

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It is not easy to get something work by just reading an article like this. At some point you will need to debug your
hardware.These debugging techniques will help you(as it has helped us a lot) to find the problem in your work.You will
need a multimeter, some LEDs. Remember,what we learned while debugging is that LEDs are the best way to debug
hardware of this nature when you dont have sophisticated debugging instruments. Some important techniques we
discovered while debugging are:

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Use of Multim eter

Multimeter will be very useful to check the zeros and ones coming across ICs.Verify that expected output is coming at
every IC.ZERO will be measured as 0.8V and ONE will be measured as 3.8V (this will vary with computer).This can be
used if the address decoding does not work and when unexpected data is seen at output lines.DO NOT CONNECT THE
MULTIMETER PROBES DIRECTLY TO DATA BUS OR THE ADDRESS LINES.ALWAYS CONNECT IT ACROSS THE
OUTPUT OF RESPECTIVE IC
Use of LEDs

LEDs can be very useful to verify the data bits coming at output lines.The lighting up of LED will be visible across latches.
To check whether the clock pulse is going to the right latch, connect a LED across the CLK pin and send data to that
port continuously in a loop like:
while(1) {
outb(0x80,0x338);
}
There are lots of other debugging techniques which you will probably discover by yourself when you get into problems.Try
to ensure that the wiring at the connector that gets into the ISA slot is correct.We checked every part of the device(every
IC,all those jumper wires,etc) and after debugging for about one week we found that IOW and IOR wires were connected
to some other pins of the ISA slot.So, recheck the wiring.We fortunately did not mistake the 12V pin for a 5V pin ;)
We are not responsible for any loss or damage caused by this article.The probability of frying up your motherboard is
more than 100% if you work on this project without using your mind.Keep your eyes open and mind alert while doing the
wiring and connecting the ICs and verify all the VCC and GND connection everytime you switch on your computer after
connecting this device to ISA slot.YOU HAVE BEEN WARNED :). Fortunately the motherboard used for this experiment
is still alive and the experiment was a huge success.
Send in your comments and suggestions to:
Abhishek Dutta, <thelinuxmaniac _AT_ gmail.com>
Badri Adhikari, <badri.aquarius _AT_ gmail.com>
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Pushpeshwor Pokharel, <pushpeshwor.pok harel _AT_ gmail.com>

Some corrections
As pointed by Kozak, Joe on Jan 27, 2006 1:00 AM, the following was corrected:
ERR: This address bus can address 1MB (2^20=1024bytes)
OK : This address bus can address 1MB (2^20=1024 Kbytes)
Gregg C Levine on Jan 31, 2006 8:36 AM wrote:One thing all of you do not describe on your well laid out site is the
board for your project. Jameco used to sell a breadboard mounted on an ISA bus card. Also one of the locations on
the site returns a 403 error message from this browser. Incidentally thats the location for datasheets.
TLM replied:.. we are from a place where you dont find ready made project boards and enjoy other such luxuary
tools.We assembled the whole project by connecting(interlock ing) two standard bread boards (which work ed quite
well).For the connector, we found a ISA expansion slot from a OLD Compaq computer in which we soldered(it took 1 day)
all the required pins with jumper wires to get the required data and address lines. Thank you for pointing the 403 error.I
corrected it to point to the datasheets of the respective IC at texas instruments website.
Harrison Mclean on Aug 2, 2006 wrote: It seems to me that with all the output control lines of the input 374s tied
to ground, the data bus between the 374s and the 245 would be a mess of intefering signals from the output of each
374. To help explain myself better, I have highlighted the area I was talking about on your diagram at this url:
When I said data bus I meant line A0 A7 (the thick black line) that connect all the 374s used for input to the 245.Note
that I mean the lines A0 A7 in the highlighted area only.The 374s and 245 I refer to are only the ones that are either
partially or completely inside the red box I have drawn.
The OC line (pin 1) on each 374 is connected to ground, which enables the outputs of each 374 all the time and it also
keeps its outputs in the state that they were when the last clock pulse was recieved, even when the clock line is LOW
because this is how the 374 works according to the datasheet.With every 374s output enabled, any bits that are HIGH
on any 374 connected to A0 A7 would be grounded or interfered with by the 3 other 374s that are connected to A0
A7 too.
E.g:
If A0 on the 374 at address 0x238 was set HIGH and the 3 other 374s (0x239, 0x23A, 0x23B) that are connected to it
through A0 had their outputs set LOW, they would make A0 go LOW.
This is because each 374 that has an output that is LOW is actually connecting the output to ground through its internal
circuits. The way to resolve this problem is to use the OC line to enable the 374s output onto A0 A7 only when it is
needed. As you probably already know, if we make the OC line (pin 1) of a 374 HIGH, its outputs will go into a high
impedance state which would basically have the effect of disconnecting the outputs of the 374 from lines A0 A7.
If we connect the clock line that goes to each 374 to an inverter too and then connect the output of the inverter to the
374s OC pin, only the 374 that is currently being read from will have its output enabled and therefore the other 374s will
not be able to interfere with the data on line A0 A7
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TLM replied: Yes, you are right. You can connect an inverters(whose input comes from the clock line) output to the OC
pins of 374 latches to prevent the possible interference. I didnt not k now that LOW output of 374 IC lines are actually
connected to ground through its internal circuits. I have learnt a new (and very important) thing about 374 ICs today.
I will update my circuit to implement the idea suggested by you.

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Written by abhishekdutta
August 30, 2010 at 2:47 pm

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