Introduction High Level Design Hardware/Software Design Results

Conclusions

Source Code and

References

All Digital FPGA Based Lock-in

Amplifier
Tristan Rocheleau
tor2@cornell.edu
ECE 576 Final Project
Fall 2008

Introduction:
This project implements a lockin amplifier using an all-digital architecture on an
FPGA. Historically, lockin amplifiers were constructed of precision analog components,
filters, mixers, etc.... A well designed lockin of this natures can preform beautifully, but
requires high quality, expensive components and careful engineering. By implementing all
the signal path components in digital form on an FPGA a number of advantages are realized.
First, using digital multipliers, ideal digital mixers and filters can be created. This removes
any possibility of added noise after digitization as well as reducing complexity. Secondly, if
sufficient precision is used in all calculations, the linear response range of each digitized
component can be arbitrarily large, again making the engineering easier. Finally, the
simplicity of having almost all components on a single chip, could greatly decrease cost. In
addition the modular nature and reprogramability of FPGA logic could allow lockin
amplifiers to be easily implemented into other designs.
For these reasons, combined with the belief that creating a lockin from scratch would
be an excellent educational endeavor, an FPGA lockin was designed and built. This report
details the design and construction of the lockin along with results and testing of the final
product.

Brief Overview of Lockins:

At its heart, a lockin amplifier consists simply of a mixer followed by a low pass
filter. By applying a reference sine wave sign wave signal to one port of the mixer, and the
signal to be measured to the other, sum and difference frequencies are generated at the output.
The low pass filter then filters out all but the difference frequencies below a certain cutoff.
This output signal then contains spectral information of the original signal in narrow band
around the reference frequency. By adjusting the filter cutoff and reference frequency, signals
of arbitrary bandwidth and frequency can be measured.
The lockin measurement scheme has a number of advantages. The primary one in
most measurement schemes is that of increased signal to noise vs a broadband measurement,
such as would be made with an oscilloscope. This can be understood by considering the
mixer + low pass filter as a variable, narrow bandwidth band pass filter. Assuming noise

sources are broad-band, the amount of actual noise captured in the measurement is
proportional to the bandwidth. If the signal of interest is at a well known frequency, the low
pass filter can be configured to a minimum bandwidth, thus providing a potential increase in
signal to noise of many magnitudes.
As an additional feature, the signal output of the low pass filter is dependant the
relative phases of the reference and signal. As such, the lockin not only measures magnitude
but also phase of a signal. As a practical matter, most lockin systems actually use two sets of
mixers and filters to allow the measurement of both quadratures of signal simultaneously.
The final oft-quoted feature of lockin amplifiers is their ability to track a signal that
varies in frequency over time. So long as the reference frequency is somehow locked to the
signal frequency, the lockin will accurately measure the signal regardless of frequency
changes. This is the origin of the term "lockin".

High Level Design:

The lockin designed here follows the general picture described above, with a few
practical complications. A high level schematic of the lockin amplifier can be seen in Figure
1.

Figure 1. Schematic diagram of the lockin amplifier.

The analog signal was acquired using an A/D converter and fed to a pair of mixers
which mix with a pair of quadrature reference signals. The reference signals can be generated
by a fixed set frequency onboard direct digital synthesis unit, or derived from an external
reference. The external reference signal is also A/D sampled, and then converted to a pulse
train which feeds the reference of an add digital phase locked loop (ADPLL). This then
generates the output quadrature sine waves. Once mixed down, the signals are fed through
programmable digital filters and are then measured and routed by a NIOS II processor. The
signal outputs can be directly routed to analog output ports as well as displayed.
For simplicity, both design and conceptual, the low pass filters were implemented via
a single pole IIR filter configured to emulate an analog RC filter. This design allowed
implementation using minimal system resources as well as minimal complexity, while also

allowing easy on-the-fly calculation of filter parameters when changing settings. The
parameters could be generated by the NIOS from a user selected time constant. The single
pole filter was implemented with two multipliers with filter output given by:
out = a0 * in + b1 * out_previous.
Time constant was selected by tuning a0 and b1 according to:
b1 = e^(-1/d)
a0 = 1 - a0
where d is the time required to decay to 1/e in number of clock ticks.
In order to allow maximal flexibility of the device, a NIOS II processor was also
implemented to control the signal path. Although not explicitly shown in the figure, the NIOS
acts as a high level control system, switching signals from the the lockin components to the
output. In this fashion, the output DACs can be used to output signals from any part of the
signal path including the reference sources, giving the advantage of maximal flexibility as
well as a useful tool in debugging. In addition, the NIOS can be used to control filter
operation/decay time.
Implementing these components in FPGA allows all operations after A/D sampling to
be done digitally at high speed. The target platform for this project was the Altera DE-2 board
with a Cyclone II FPGA, speed grade 6, with 35K logic elements. The lockin design should
fit easily within this chip and looking up the speed specs for this speed grade gives an
advertised 18 x 18 bit multiplication of over 200MHz. This type of clock speed is probably
not attainable for the system a whole, but clocking at 50MHz should be entirely stable. As a
reasonable expectation, input signal sine waves operating at frequencies of up to one or two
MHz should be easily achievable at these clock rates.

User Interface:
For basic lockin functionality, a number of settings must be entered and displayed by
the user. Control of the reference, whether external or an internally set frequency, as well
filter bandwidth are essential. In addition control of the output signals along with the ability
to display information about current measured values is useful. To this end, it was decided to
generate a video display output from a NIOS II processor. The NIOS II processor provided
plenty of processing power to generate an output display as well as handle user input and
control elements of the lockin signal path.

Hardware implementation
overview:
The entirety of the digital components of this project were implemented on a Terasic
DE-2 board with an Altera Cyclone II FPGA. The DE-2 board provided the majority of the
hardware components needed, such as the basic FPGA support circuity (power supply,
programming, etc), as well switches and buttons for user input along with a VGA output

port. The only real lack of this board for a lockin is the absence of a high speed A/D
converters. A number of A/D options were considered for the project, mostly based on a
homebuilt add-on board, but it was decided in the end to use a Terasic P0003_GPIO high
speed digital acquisition daughterboard.
The Terasic product was chosen primarily due to it's convenience, but also had a quite
high sampling rate. The board is designed to interface with the DE-2 board and includes two
ports of 100MS/s 14 bit DAC outputs and 2 ports of 65MS/s 14 bit A/D input. This was
deemed entirely sufficient for a design goal of 1MHZ input bandwidth and gave a good
option for either high frequency reference outputs or low frequency output signals.
Unfortunately, as discussed in more detail later, the Terasic board failed to meet
expectations. Of critical importance for the intended application, both the input and output
ports on the board were coupled via transformers which had an effective cut-off of ~100KHz.
For input signals this simply limited the range of measurement to signals above 100KHz -- an
annoyance but still functional. In order to output the low frequency or DC measured signals,
however, the output ports simply do not work.
To get around this problem, two DAC ports of the VGA output chip on the DE-2 main
board were used. The VGA interface featured 3 10-bit DACs rated at up to 100MS/s and
allowing DC outputs. While slightly low in resolution, these ports fit the output needs well.
Unfortunately, the use of two of the VGA DACs precluded the output of a VGA video, a
necessary component of the user interface. To get around this issue, it was decided to use the
third VGA output DAC to generate an NTSC signal for display on a standard TV. The
resolution of this display is certainly lower, but was acceptable.

Hardware details:
In designing the digital hardware, there were several non-trivial components. As laid
out in the overview above, these consisted of an ADPLL, low pass filters, a video generator,
the reference signal zero-crossing detector, as well as various interconnect logic. Each is
described in detail below:
Zero-Crossing Detector:

The reference zero-crossing detector was probably the simplest component. It simply
took the digitized reference input, and waited for zero crossing. In order to prevent noise on
the signal receptively triggering the crossing detect, both positive and negative hysteresis was
added. This required the signal to reach a certain magnitude before a zero crossing would be
triggered. The output was always triggered at the zero crossing, not at a higher or lower
hysteresis value, however, to prevent any phase shift. This hysteresis value was semiarbitrarily set to ~0.2V.
ADPLL:

In order to lock to an externally generated reference signal a phase locked loop was
needed. In keeping with the all digital design methodology of the project, this was
implemented as an all digital phase locked loop (ADPLL) which as input took a digitized

data stream of the reference signal and as output gave a pair of locked quadrature sine waves.
A schematically diagram of the chosen topology is shown in Figure 2:

Figure 2. ADPLL.

As with any PLL, this ADPLL consisted of a phase comparator, a loop filter, and a
programmable oscillator. The phase comparator in this case was functionally equivalent to the
standard dual edge-triggered flip-flop design used in analog charge pump PLLs. The output
of the phase comparator is a pair of signals, one indicating a lead in the local oscillator pulse
edge, the other a lag. These signals were fed to the loop filter which consisted of a digital
counter implementing an integral response which was combined with a straight proportional
gain response. Each unit was fed by the 100MHz system clock. For each clock tick that the
lead signal was high, the integral counter was incremented by a value; for each clock tick the
lag signal was high it was decremented. Similarly, whenever the lead signal was high a
positive value was output from the proportional unit, while for a lag signal a negative output
was induced. The outputs were then summed and fed to the local oscillator.
The programmable oscillator in this case consisted of a high accuracy direct digital
synthesis(DDS) module. Frequency was set by a 40 bit fixed point input in 24.16 format(this
was overkill, by the way). The input was fed by the output of the loop filter which then
adjusted frequency. The DDS unit then output a pair of quadrature sine waves in 18 bit
resolution which were used for the mixers. In addition, a digital square wave of the same
frequency was output and used to feed the phase comparator.
As a final feature, a simple lock detector was also implemented. This was not
neccessary for the rest of the system, but seemed like a good idea for completeness's sake.
This was done by implementing a pair of counters at the rise of the reference signal which
counted till the reference went low for one or the DDS output for the other. By outputting a
signal when the values were within a certain fractional range of each other, a simple lock
signal was generated. Further using this signal to trigger a counter and then requiring the
counter reach a certain value(255 in this case) provided a simple but seemingly functional
lock detect.
Low Pass Filter:

Low pass filters on the output of the quadrature mixers were implemented by a simple single
pole IIR filter and were designed to emulate simple analog RC filters with an adjustable time

constant. Implementation of this was done using two multipliers to multiply the two filter
parameters against the input and previous output signal, respectively. The outputs were then
summed, and stored in an output register which also previous output to the filter.
NTSC Video Output:

To generate a useful user interface, a video output was needed from the single
remaining VGA DAC. As such, it was decided to generate an NTSC composite video signal
for display on a television. In order to generate the signal, an accurate timing sync timing
system had to be designed, along with coordinate generation and actual video signal output
during the correct portions of the video scan.
For an NTSC signal, a single analog output output signal encoded with video data as
well as synchronization pulses is used to directly control the TV image scan. Figure 3 shows
timing information for the NTSC signal. During the display period, signal intensity is
encoded directly by signal voltage. while color is encoded by a sine wave overlay signal. For
the lockin output, only text information was needed, so a luminosity encoded output(no
colour) was sufficient. The generation of this timing information and luminosity signals were
done with straightforward timing and comparator logic.

Figure 3. NTSC Video timing information

Source: http://www.williamson-labs.com/480_tvc.htm

Horizontal resolution and retrace are both controlled by this timing information. In
order to control the vertical retrace additional synchronization signals are needed every ~260
scan lines. Figure 4. shows a more complete entire screen timing information, including the
vertical sync pulses. The full NTSC specification calls for 525 total interlaced line per screen,
of which only 485 are visible. Interlacing is accomplished by starting dithering each new
frame by half a horizontal sweep. In the interest of simplicity, as well as due to lack of a need
for greater resolution, the NTSC generator in this project only generated a visible resolution
of 240 lines. This was accomplished by simply generating the vertical retrace without the
half sweep dithering, effectively generating a half vertical resolution, non-interlaced image.

Figure 4. Full NTSC timing inforation

Source: http://www.williamson-labs.com/480_tv.htm

The actual user interface consisted of a text display controlled by the NIOS II
processor. A diagram of text generation system is seen in Figure 5. The text was generated by
a simple character generator which as input took x and y coordinates and an ascii character.
For the ascii font, a modified version of the font provided on the CD accompanying [7]. The
ascii was fed via a text buffer implemented as dual port ram. This allowed a dedicated port
for access by the character generator when needed for display, while also allowing
transparent writing by the NIOS. The character ram was memory mapped directly into the
NIOS address space via an Avalon switch fabric connection, thus further further simplifying
software development by allowing direct memory access to the ram. As an additional feature,
a blinking cursor was implemented to provide a visual feedback as to the currently selected
setting to be modified.

Figure 5. Text generation video system

Software Design:
Software was written for the NIOS II processor in c code using the NIOS II C IDE
provided by Altera. The software was primarily to implement the user interface as well as
control the filters and operating mode of the lockin. The interface consisted of a text display
with various changeable settings as well as continually updated outputs of the locking. By
reading in the measured values of the two quadratures of the locking, the NIOS could both
display these values on-screen, as well as calculate derivative quantities. Useful information
that was chosen for display was the total response of the lockin(R) as well as the measured
phase angle. These values were easily calculated as:
R^2 = X^2 + Y^2
Theta = Atan(X/Y)
Where X and Y are the measured values of the two quadratures. In order that these values be
calculated without slowing down other processing, floating point hardware was also included
in the NIOS design. In all likelyhood, this was entirely unnecessary as the only speed
requirement be that the output values update at a reasonable human timescale for display.
The NIOS II was programmed to loop through these calculations, updating output
values on every loop, while also keeping track of user input provided by three on-board
pushbuttons as well as the 18 toggle switches. Two of the buttons were used to navigate a
simple setting selection system, while the third was used to either toggle settings, or to write
an input number to a NIOS variable from the toggle switches.

Results and testing:

After lengthy debugging and tweaking the lockin was deemed generally functional. A
number of tests, mostly qualitative in nature, were preformed and are described below. In
general, performance was good, with speedy response and accuracy to within ~1% as
determined by comparison with signal output levels from a test source. The user input was a
little clunky, having to use the on board switches, but generally worked well. the video out,

while low resolution, was entirely sufficient. An example image of the interface while
measuring a low amplitude signal is shown in Figure 6. Due to slight inconsistency between
TV's, the left couple pixels are cut off, but in general the image is clear.

Figure 6. Picture of user interface in action. The moire pattern is an artifact of the picture,
not the display.

As a preliminary test, the ADPLL performance was examined. Several important

parameters were noted, particularly settling time, frequency range of reliable operation, and
output jitter. While no thorough quantitative analysis of the loop filter function performance
was made, a significant amount of parameter space was explored while trying to find optimal
performance. PLL performance was highly dependant on the relative constants of gain and
integration, with an increase in either allowing for sometimes faster locking but at the cost of
increased jitter or oscillations. In the final version, these parameters were set to give a
reasonable compromise between settling time and operation frequency range.
With the final values, the PLL performance seemed quiet good. The PLL reliably
locked within ~<1s for any frequency between the lowest operating frequency of 100KHz
and 1MHz. Above 1MHz the PLL could still lock till ~5Mhz, but occasionally had trouble
locking in a timely fashion. An example wavefrom of the PLL locked to an irregular input
function can be seen in Figure 7.

Figure 7. ADPLL output locked to an irregular reference waveform.

Once locked, the PLL output appeared very stable and was easily able to follow slow
changes in frequency on order of at least 10KHz/s. Based upon observation of the set
frequency displayed in the user interface, the output frequency appeared to be stable to within
less than 1Hz. In addition, the PLL had no trouble locking to any reasonably shaped periodic
waveform.
The Mixers were tested by inputting various signal inputs and reference frequencies.
Performance was found to be exactly as expected, with the multiplied signal being output
with sum and difference components. The filters were then tested by comparing input to filter
with the output. Once properly debugged the filters worked without issue, smoothing input
signals in what qualitatively seemed reasonable. The time constant was measured by applying
a step change in signal and observing response rate and was found to be what it should be
based on programed filter constants.

Figure 8. Output of mixers vs. output of filter for a square wave signal input. Left trace is direct
mixer output, right is output after filtering. Yellow trace is outputs, green is reference signal.

Additional testing was done

reference frequency and observing
frequency signal and reference were
determining that the output levels
perfectly in all these respects.

by measuring signals very slightly detuned from the

slow oscillation of the output. In addition identical
measured while adjusting phase shift of the signal and
shifted quadrature as expected. The lockin behaved

Limitations on performance:
As mentioned earlier, a major limitation on the lockin was the input transformers on
the A/D board. The high cutoff of these transformers limited operation to around 100KHz and
above. Figure 9 below shows an input square wave at 300KHz after sampling with the A/D
board.

Figure 9. 300KHz square wave after sampling through input transformer.

In addition to this limitation, there seemed to be a certain degree of coupling between

the input ports of the A/D board, as well as a definite degree of crosstalk on the output ports
of the DAC. This produced an increased amount of noise on the input signal, as well as noise
on the analog output. The input noise produced a small, non-zero measured signal output
even with no signal input while the output noise simply reduced fidelity of the analog out.
An addition major limitation of this design in terms of an actual useful measurement
device is the lack of a preamplifier stage. As lockins are typically used as precision
measurement tools, having a low noise input with adjustable gain is essential. While
performance was acceptable for large input signals, smaller signals are easily drowned out.
An input amplifier would also reduce the issue of crosstalk in the input A/D converters.

Conclusions:
In general, the lockin fulfilled all the expectations for functionality. The limited
frequency operation range and input signal fidelity was disappointing, but not surprising
given the analog hardware used. All in all, it was an interesting and extremely educational
project, but the previously mentioned limitations prevent it from being truly useful in a
scientific setting as currently designed.

As a revised version, a few modifications would greatly improve the quality of the
device. In terms of the FPGA logic, the major area for improvement would be in the
ADPLL. While performance was reasonable here, more care in the design of the loop filter
would undoubtedly increase performance greatly. The implementation of the filter in all
digital logic gives hugely interesting possibilities for highly non-linear feedback, possibly
surpassing analog PLLs. Other than the ADPLL, the remaining digital logic seemed well
suited for the device, with the possible exception of the user interface which was slightly
clunky, although more of a function of limited input devices on the DE-2 board than anything
logic design related. The use of a mouse and keyboard interface or application specific button
arrays might make use much simpler.
The main region for improvement would definitely be in the analog components.
Replacing the Terasic A/D board with something that was better shielded and offered lower
frequency, ideally DC, operation would be a great boon. In addition, higher precision and
quality DAC outputs would allow for higher grade analog outputs.
Briefly analyzing rough costs associated with this form of lockin device yields
tantalizing results. The current design when compiled and fitted into the Cyclone II FPGA
used ~11K logic elements. Given that this includes a full featured 32 bit processor with
instruction cache, full floating point hardware, as well as a number of other entirely nonspace-optimized components, it seems reasonable that the entire design could be fit within a
8K or even 5K device, costing a mere ~$30. Combine this with high precision, moderately
low speed A/D and D/A converters which cost ~$10 each. Adding the costs of a low noise
amplifier and it seems that you could achieve a very competitive instrument working up to
~200KHz for under $100. Of course there would be significantly further hardware
development from the project described here to reach this goal.
In conclusion, the lockin device described here was a success, if somewhat limited by
the hardware used. Building upon the basic device with better, customized hardware could
yield a device suitable for for high quality measurements. Despite the need for better
engineering of the analog components here, the mostly digital design would still seem to be
simpler to engineer than an all analog device and offers tantalizing possibilities.

Source Code:
Top level verilog module:
lockin_amp.v

Support modules:
ref_digital_PLL.v
zero_crossing_detector.v
exponential_decay_filter.v
character_generator.v
DDS_signal_generator.v
ntsc_disp_generator.v

SOPC builder file:

control_nios.sopc

User interface NIOS code:

lockin.c

References:
[1] Stanford Research Systems application note #3.
http://www.thinksrs.com/downloads/PDFs/ApplicationNotes/AboutLIAs.pdf
[2] http://www.terasic.com -- Information of the A/D board as well as downloads of the data
sheets.
[3] Very useful video tutorials and information: http://www.williamson-labs.com/480_tv.htm
[4] An excellent article on simple NTSC generation in a microcontroller: AVR Video
Generator Teaching Programming and Graphics, Circuit Cellar Magazine #150, pp 40-44,
Jan 2003
[5] www.altera.com.
[6] Dale Grover and John R. Deller, Digital Signal Processing and the microcontroller ,
Prentice-Hall/Motorola University Press 1999
[7] JO Hamblen, TS Hall and MD Furman, Rapid protoyping of digital systems, SPOC
edition , Springer 2008