CMOS Digital Integrated Circuits

Chapter6:
Interconnect Analysis

CMOS Digital Integrated Circuits

Interconnect Analysis
The Wire

interconnect 2

interconnect 1

transmitters

Schematics
2

receivers

Physical
CMOS Digital Integrated Circuits

Interconnect Analysis
Wire Models

All-inclusive model
3

Capacitance-only
CMOS Digital Integrated Circuits

Interconnect Analysis
Impact of Interconnect Parasitics
Interconnect parasitics
Reduce reliability
Affect performance and power consumption

Classes of parasitics
Capacitive
Resistive
Inductive

CMOS Digital Integrated Circuits

Interconnect Analysis
Capacitance (1/8)
Capacitance of Wire Interconnect
VDD

VDD

M2
Vin

Cg4

Cdb,p

C gd,pn

M4

Vout

Cdb,n

C int

M1

Vout2

Cg3

M3

Interconnect

Fanout
Vin

Simplified
Model

Vout
Cload

CMOS Digital Integrated Circuits

Interconnect Analysis
Capacitance (2/8)
The Parallel Plate Capacitance
Current flow

l
Electrical-field lines

t
h

Dielectric
Substrate

C pp
6

di
h

wl
CMOS Digital Integrated Circuits

Interconnect Analysis
Capacitance (3/8)
Permittivity

CMOS Digital Integrated Circuits

Interconnect Analysis
Capacitance (4/8)
Fringing Capacitance
Fringing-field capacitance

w t /2

c wire c pp c fringe
2h

2h
2h

ln
1

t t

for w

t
2

1 0.0543t /2h
w

1.47
c wire c pp c fringe
h

2h
2h 2h

ln
1

t t

for w

t
2

CMOS Digital Integrated Circuits

Interconnect Analysis
Capacitance (5/8)
Fringing versus Parallel Plate

(from [Bakoglu89])
9

CMOS Digital Integrated Circuits

Interconnect Analysis
Capacitance (6/8)
Interwire Capacitance

fringing

10

parallel

CMOS Digital Integrated Circuits

Interconnect Analysis
Capacitance (7/8)
Impact of Interwire Capacitance

(from [Bakoglu89])
11

CMOS Digital Integrated Circuits

Interconnect Analysis
Capacitance (8/8)
Wire Capacitances (0.25m CMOS)

12

CMOS Digital Integrated Circuits

Interconnect Analysis
Impact of Interconnect Capacitance
Influence of Interconnect Capacitance
The wire delay is proportional to the capacitance charged.
More capacitance means more dynamic power.
Coupling capacitance
Is an increasing source of noise.
Makes delay estimation hard.

How to Reduce Interconnect Capacitance

Use low k dielectric which reduces permittivity and hence the capacitance.
Increase the spacing between the wires (Not always possible).
Separate the two signals with a power or ground line (acting as shield).
Use minimum wire width wherever possible. (Increase resistance!)

This slide is courtesy of Professor He.

13

CMOS Digital Integrated Circuits

Interconnect Analysis
Resistance (1/3)
Wire Resistance

R=

l
t w

Sheet Resistance
Ro

14

CMOS Digital Integrated Circuits

Interconnect Analysis
Resistance (2/3)
Interconnect Resistance

15

CMOS Digital Integrated Circuits

Interconnect Analysis
Resistance (3/3)
Sheet resistance

16

CMOS Digital Integrated Circuits

Interconnect Analysis
Impact of Interconnect Resistance
Influence of Interconnect Resistance
The wire delay is proportional to the wire resistance.
IR Drop Along the Wire
Proportional to the resistance The noise margin is reduced.
A significant problem in the power lines where current density is
high.
Contact resistance makes them vulnerable to electromigration.

How to Reduce Interconnect Resistance

Use materials with low resistivity (Cu).

Reduce wire length (Not always possible).
Increase width (Increase area and capacitance!).
Increase height (Increase fringe capacitance!).
Provide bigger contacts: Use less vias.
Use metal instead of polysilicon even for short distance routing.
Use silicide coating to reduce polysilicon resistance.
This slide is courtesy of Professor He.

17

CMOS Digital Integrated Circuits

Interconnect Analysis
Dealing with Resistance
Selective technology scaling
Scale w while holding t constant

Use better interconnect materials

Lower resistivity materials like copper
As processes shrink, wires get shorter (reducing C) but they get closer
together (increasing C) and narrower (increasing R). So RC wire delay
increases and capacitive coupling gets worse.
Copper has about 40% lower resistivity than aluminum, so copper wires
can be thinner (reducing C) without increasing R

Use silicides (WSi2, TiSi2, PtSi2 and TaSi)

silicide

Conductivity is 8-10 times better than poly alone

polysilicon
SiO2

n+

Use more interconnect layers

n+

reduces the average wire length l (but beware of extra contacts)

18

CMOS Digital Integrated Circuits

Interconnect Analysis
Analysis of Simple RC Circuit (1/2)
i(t)

R i (t ) v(t ) vT (t )
d (Cv(t ))
dv(t )
i (t )
C
dt
dt
dv(t )
RC
v(t ) vT (t )
dt

vT(t)

v(t)

first-order linear differential

equation with
constant coefficients

state
variable
Input
waveform
This slide is courtesy of Professor He.

22

CMOS Digital Integrated Circuits

Interconnect Analysis
Analysis of Simple RC Circuit (2/2)
zero-input response: RC dv(t ) v (t ) 0
(natural response)

dt
1 dv(t)
1
t

v N (t) Ke RC
v(t) dt
RC

step-input response: RC

dv(t )
v(t ) v0u (t )
dt

vF (t ) v0u (t ) v(t ) Ke
match initial state: v(0) 0
output response
for step-input:

RC

v0u (t )

K v0u(t ) 0

v (t ) v0 (1 e

v0
RC

)u (t )

v0u(t)
v0(1-eRC/T)u(t)

This slide is courtesy of Professor He.

23

CMOS Digital Integrated Circuits

Interconnect Analysis
Step-response of RC wire
L

Vin
L/10

L/4

Vout

L/2

2.5

L/10
2

L/4

1.5

L/2

0.5
0
0

0.5

1.5

2.5

3.5

4.5

time (nsec)
25

CMOS Digital Integrated Circuits

 Ideal Wire

Interconnect Analysis
Wire Delay Models (1/3)

Same voltage is present at every segment of the wire at every point in time
- at equal potential
Only holds for very short wires, i.e., interconnects between very nearest
neighbor gates
Lumped RC Model
Total wire resistance is lumped into a single R and total capacitance into a
single C
Good for short wires; pessimistic and inaccurate for long wires
R
Vout

Vin
C

Vout(t) = VDD(1-exp(-t/RC))
V50%(t) = VDD(1-exp(-PLH/RC))

PLH 0.69RC
26

CMOS Digital Integrated Circuits

Interconnect Analysis
Wire Delay Models (2/3)
This simplest model provides a very rough approximation of the
actual transient behavior of the interconnect line.
T-Model
The above simple lumped RC model can be significantly
improved by the T-model as

R/2

R/2

Vin

Vout
C

27

CMOS Digital Integrated Circuits

Interconnect Analysis
Wire Delay Models (3/3)
Distributed RC Model
The transient behavior of an interconnect line can be more
accurately represented using the RC ladder network. The
transient behavior of this model approaches that of a
distributed RC line for very large N
R/N

R/N

R/N

R/N

Vout

Vin
C/N

C/N

C/N

C/N

VOUT
1.0

0.5

DISTRIBUTED

LUMPED

1.0RC

2.0RC

time

Step response of distributed and lumped RC networks.

A potential step is applied at VIN, and the resulting VOUT
is plotted. The time delays between commonly used
reference points in the output potential is also tabulated.
28

CMOS Digital Integrated Circuits

Interconnect Analysis
Computation of Elmore Delay (1/5)
Consider a general RC tree network
No resistor loop
All of the capacitances are connected between a node and ground
One input node

The Elmore Delay

First order time constant (first moment of the impulse response) at
node is a sum of RC components
All the upstream resistances are taken into account
Thus each node contributes to the delay
Amount of contribution is the product of the capacitance at the
node and the amount of resistance from source to the node.
39

CMOS Digital Integrated Circuits

Interconnect Analysis
Computation of Elmore Delay (2/5)
Elmore analyzed the distributed model of the general RC tree
network and came up with the figures for delay

D C j Rij
i

j 1

Rij=Rk where Rk [path(si)path(sj)]

40

CMOS Digital Integrated Circuits

Interconnect Analysis
Computation of Elmore Delay (3/5)
RC Chain

R1

Vin

1
C1

R2

C2

Ri-1

i-1

Ci-1

RN

Ri

i
Ci

N
CN

VN

Elmore delay equation

41

DN = Cj RNj

CMOS Digital Integrated Circuits

Interconnect Analysis
Computation of Elmore Delay (4/5)
D1=C1R1 D2=C1R1 + C2(R1+R2)
R1
Vin

1
C1

R2

C2

Ri-1
Ci-1

i-1

RN

Ri

Ci

CN

VN

Di=C1R1+ C2(R1+R2)++Ci(R1+R2++Ri)
N

Elmore delay equation

42

DN = Cj RNj = Cj Ri

CMOS Digital Integrated Circuits

Interconnect Analysis
Computation of Elmore Delay (5/5)
Assume: Wire modeled by N equal-length segments
R/N

R/N

R/N

R/N

Vout

Vin
C/N

DN
j 1 N

C/N

C/N

C/N

R
R
N 1

2
R

NR

RC

2
N
N
2
N

k 1
j

For large values of N:

DN = RC/2
where R and C are the total lumped resistance and capacitance of the
wire

43

CMOS Digital Integrated Circuits

Interconnect Analysis
Comments on Elmore Delay Model
Advantages
Simple closed-form expression
Useful for interconnect optimization
Upper bound of 50% delay [Gupta et al., DAC95, TCAD97]
Actual delay asymptotically approaches Elmore delay as input
signal rise time increases
High fidelity [Boese et al., ICCD93],[Cong-He, TODAES96]
Good solutions under Elmore delay are good solutions under
actual (SPICE) delay

Disadvantages
Low accuracy, especially poor for slope computation
Inherently cannot handle inductance effect
Elmore delay is first moment of impulse response
Need higher order moments
44

CMOS Digital Integrated Circuits

CMOS Digital Integrated Circuits

Super Buffer Design

CMOS Digital Integrated Circuits

Supper Buffer
Supper Buffer

Cload

Given a large capacitance load Cload

How many stages are needed to minimize the delay?
How to size the inverters?
Equiv INV

1
Cg

Cd

Cg

2
Cd

2Cg

2Cd

NCg

NCd

Cload

N: number of inverter stages

: optimal stage scale factor

2

CMOS Digital Integrated Circuits

Supper Buffer (Cont.)

where

Cg: the input capacitance of the first stage inverter.

Cd: the drain capacitance of the first stage inverter.
Each inverter is scaled up by a factor of per stage.
Cload = N+1Cg
All inverters have identical delay of 0(Cd+Cg)/(Cd+Cg) which 0 is
per gate delay for Equiv INV in ring oscillator circuit with load
capacitance = Cg+Cd

CMOS Digital Integrated Circuits

Supper Buffer Design

Equiv INV

1
Cg

Cd

Cd

Cg

2
2Cd

2Cg

NCg

NCd

Cload

Consider N stages, each inverter has same delay 0(Cd+Cg)/(Cd+Cg).

Therefore,
C d C g

1
total
0

C
C
d
g

CMOS Digital Integrated Circuits

Supper Buffer Design (Cont.)

Goal: Choose and N to minimize total.
By Cload = N+1Cg, we have

ln C load
N 1 C g
ln

Plug the above equation into total, we get

C load

ln
C g C d C g

total
0

ln
Cd C g

To minimize total:

total ln C load C d C g 1 C g 0
0
2

C g ln C d C g ln C d C g

opt ln opt 1
5

Cd
Cg
CMOS Digital Integrated Circuits

Supper Buffer Design (Con.)

For the special case Cd=0 ln(opt)=0 opt = e. However, in
reality the drain parasitics cannot be ignored.
Example: For Cd=0.5 fF, Cg=1 fF, determine opt and N for Cload = 50
pF.
opt (ln opt -1) = 0.5 opt = 3.18

N 1

lnC load / C g

ln opt
N lnC load / C g / ln opt 1

ln50 1012 / 1 1014 / ln 3.18 1

6.36

The Super Buffer Design which minimizes total for Cload = 50 pF is

N=7 Equiv INV stages, and opt = 3.18

CMOS Digital Integrated Circuits

CMOS Ring Oscillator Circuit

Oscillation period T is equal to
T=PHL1+PLH1+PHL2+PLH2+PHL3+PLL3
=2p+2p+2p
=32p=6p
For arbitrary odd number (n) of cascade-connected invertes, we
have
f=1/T=1/(2np)
Also, we can write
p=1/(2nf)
1

V1
Cload,1

V2
Cload,2

V3
Cload,3
CMOS Digital Integrated Circuits

Voltage Waveforms of Ring Oscillator

Vout
VOH

V2

V1

V3

V2

V1

V3

V50%
VOL
t
PHL2 PLH3 PHL1 PLH2 PHL3 PLH1

CMOS Digital Integrated Circuits