9/22/2016

M20KmemoryblockDefinition

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QuartusIIHelpv15.0>M20KmemoryblockDefinition

M20Kmemoryblocks

Asynchronous,truedualportmemoryblock,withregisteredinputsandoptionallyregisteredoutputs,availableinStratixVfamily
devices.YoucanusetheM20Kblockforstoringprocessorcode,implementinglookupschemes,andimplementinglargememory
applications.Eachblockisa51240RAMblockandcontains20,480programmablebits,includingparitybits.Youcanconfigure
theM20Kblockastruedualport,simpledualport,andsingleportRAM,andROM.YoucanuseaMemoryInitializationFile(.mif)
orHexadecimal(IntelFormat)File(.hex)topreloadthememorycontentswhentheM20KmemoryblockisconfiguredasaRAM
orROM.AllRAMinstancesarekeptintheformofRAMslicesuntilafteranalysisandsynthesis,whentheFitterassignsRAM
slicestoM20KRAMblocksorMLABstobalanceouttheresourceusage,orifthedesignspecifiesMLAB.
EachM20Kmemoryblocksupportsthreeclockenablecontrols,whichallowseachinputregisterandcorememorycelltouse
eitherclockenablecontrolsornogatingclockcontrol.Theoutputregistersupportsoneclockenablecontrolornogatingclock
control.Clockmuxingisbalanced,whichpreventsskewbetweenclockpaths.
TheWriteEnable(WE)andReadEnable(RE)controlsareindependentinM20Kmemoryblocks.IndependentWEandRE
controlsallowyoutoreducepowerconsumptionwhendataoutputduringawriteoperationisnotcritical.ByteEnable(BE)signals
allowformorefinegrainedwritecontrol.
ThefollowingtableliststheconfigurablesizesfortheM20Kmemoryblock

OperationMode

M20KMemoryBlockSize

SingleportorROM

16K1
8K2
4k4
4K5
2K8
2K10
1Kx16
1Kx20
512x32*
512x40*

Dualport

WriteM/ReadN
WriteY/ReadZ

M,N=1,2,4,8,16,or32
Y,Z=5,10,20,40

Truedualport

portAM/portBN
AY/BZ

M,N=1,2,4,8,or16
Y,Z=5,10,or20

*Thewidestsingleportmodeissupportedbyemulationthroughtruedualportmode.TheQuartusIIsoftwarepackstwoatoms
(eachwithhalfdatawidth)intruedualportmodetosupportthewidestmode.
ThewidestROMmodeisimplementedthroughsimpledualportmode,insteadofpackedmodeimplementationforsingleport
mode.Thisimplementationisusedmainlytosavepower,becauseROMrequiresonlyoneport(readport)andpowerissavedby
disablingtheactivitiesinotherport(writeport).
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