1

INTRODUCTION.............................................................................................................. 5
TUNER............................................................................................................................... 5
2.1 General description of TDTC-G101D: ........................................................................ 5
2.2 Features of TDTC-G101D: .......................................................................................... 6
2.3 Pin Configuration: ........................................................................................................ 7
3 SAW FILTER ......................................................................................................................... 7
3.1 IF Filter for Audio Applications Epcos K9656M ..................................................... 7
3.1.1 Standarts .................................................................................................................... 7
3.1.2 Features ..................................................................................................................... 7
3.1.3 Pin Configuration ...................................................................................................... 7
3.1.4 Frequency Response.................................................................................................. 8
3.2 IF Filter for Video Applications Epcos K3958M................................................... 9
3.2.1 Standarts .................................................................................................................... 9
3.2.2 Features ..................................................................................................................... 9
3.2.3 Pin Configuration ...................................................................................................... 9
3.2.4 Frequency Response.................................................................................................. 9
4 AUDIO AMPLIFIER STAGE WITH PT2333 .................................................................... 10
4.1 General Description of PT2333: ................................................................................ 10
4.2 Features of PT2333: .................................................................................................. 10
4.3 Pin Configuration of PT2333: ................................................................................... 11
5 MICROCONTROLLER (MSTAR)..................................................................................... 11
5.1 Genaral Description.................................................................................................... 11
5.2 Features ...................................................................................................................... 12
6 INTEGRATED DVB-T RECEIVER (CHEERTEK) ........................................................... 13
6.1 General Description.................................................................................................... 13
6.2 Features ...................................................................................................................... 13
7. 4MX16 BIT SYNCHRONOUS DRAM ( DIGITAL SIDE SDRAM) ................................ 16
7.1 General Description.................................................................................................... 16
7.2 Features ...................................................................................................................... 16
7.3 Pin Configuration ....................................................................................................... 17
8 S25FL016A - 16 Megabit Cmos 3.0 Volt Flash Memory with 50-Mhz (Serial Peripheral
Interface)Bus.18
8.1 General Description.................................................................................................... 18
8.2 Distinctive Characteristics.......................................................................................... 18
9 4M x 16 bit Synchronous DRAM (ANALOG SIDE SDRAM)............................................ 20
9.1 General Description................................................................................................... 20
9.2 Features ...................................................................................................................... 20
9.3 Pinning ....................................................................................................................... 21
10 POWER STAGE ................................................................................................................. 22
10.1 IPS 15 Option ........................................................................................................... 22
11 IC SPECIFICATIONS ........................................................................................................ 23
11.1 8K Smart Serial EEPROM 24C64 ....................................................................... 23
11.2 TL062 ...................................................................................................................... 24
11.3 FSA3157.................................................................................................................. 25
11.4 FDS8878.................................................................................................................. 26
11.5 ST24LC21 (Optional) ............................................................................................. 26
11.6 TDA1308T .............................................................................................................. 27
11.7 STMP2161 .............................................................................................................. 28
11.8 AZ1045.................................................................................................................... 30
11.9 MP1583 ................................................................................................................... 31

11.10 LM1117................................................................................................................. 33
11.11 MP2109 ................................................................................................................. 34
11.12 FDC642P............................................................................................................... 35
11.13 XC5000 (Optional)................................................................................................ 36
12 BLOCK DIAGRAMS ......................................................................................................... 39
12.1 General Block Diagram.......................................................................................... 39
12.2 Integrated DVB-T Receiver Block Diagram.......................................................... 41
12.3 17MB45 Analog Front-End ................................................................................... 42
12.4 17MB45 Digital Front-End .................................................................................... 42
12.5 17MB45 Digital CI ve Smart Card Interface ......................................................... 43
12.6 17MB45 HDMI Inputs ........................................................................................... 43
12.7 17MB45 Analog Interface MSTAR IC ............................................................ 44
12.8 17MB45 Analog Input / Output ............................................................................ 45
12.9 17MB45 LVDS Output .......................................................................................... 45
12.10 17MB45 Power ...................................................................................................... 46

INTRODUCTION

17MB45-2 mainboard is based on MSTAR concept IC. This IC is capable of handling audio
processing, video processing, scaling-display processing, 2D comb filter, OSD and text
processing, 8 bit dual LVDS transmitter.
TV supports PAL, SECAM, NTSC colour standards and multiple transmission standards as
B/G, D/K, I/I, and L/L including German and NICAM stereo.
Sound system is able to supply 2x2.5W (10%THD) audio output power for stereo speakers.
Supported peripherals are:
The analog part of the moard can support DVD module which is connected to mainboard
through a cable.
The USB feature is supported through digital part of the mainboard.
1 RF input VHF1, VHF3, UHF @ 75Ohm(Common)
1 Side AV (CVBS, R/L_Audio) (Common)
1 SCART socket(Common)
1 PC input(Common)
1 Headphone(Optional)
1 Common interface(Optional)
1 Digital USB(Optional)
1 HDMI (Optional)

2 TUNER
A horizontal mounted and Digital Half-Nim tuner is used in the product, which covers 3
Bands(From 48MHz to 862MHz for COFDM, from 45.25MHz to 863.25MHz for CCIR CH).
The tuning is available through the digitally controlled I2C bus (PLL). Below you will find
info on the Tuner in use.

2.1 General description of TDTC-G101D:

The Tuner covers 3 Bands(from 48MHz to 862MHz for COFDM, from 45.25MHz to
863.25MHz for CCIR CH). Band selection and Tuning are performed digitally via the I2C
bus.

Tuner and Main IC connections for analog:

2.2 Features of TDTC-G101D:

Digital Half-NIM tuner for COFDM

Covers 3 Bands(From 48MHz to 862MHz for COFDM,
From 45.25MHz to 863.25MHz for CCIR CH)
Including IF AGC with SAW Filter
Bandwidth Switching (7/8 MHz) possible
DC/DC Converter built in for Tuning Voltage
Internal(or External) RF AGC, Antenna Power Optional

2.3 Pin Configuration:

3 SAW FILTER
3.1 IF Filter for Audio Applications Epcos K9656M
3.1.1 Standarts

B/G
D/K
I
L/L

3.1.2 Features

TV IF audio filter with two channels

Channel 1 (L) with one pass band for sound carriers at 40,40 MHz (L) and 39,75
MHz (L- NICAM)
Channel 2 (B/G,D/K,L,I) with one pass band for sound carriers between 32,35 MHz
and 33,40 MHz

3.1.3 Pin Configuration

1 Input
2 Switching input
3 Chip carrier - ground
4 Output
5 Output

3.1.4 Frequency Response

Frequency Response of Channel 1:

Frequency Response of Channel 2:

3.2 IF Filter for Video Applications Epcos K3958M

3.2.1 Standarts

B/G
D/K
I
L/L

3.2.2 Features

TV IF filter with Nyquist slopes at 33.90 MHz and 38.90 MHz

Constant group delay

3.2.3 Pin Configuration

1 Input
2 Input - ground
3 Chip - carrier ground
4 Output
5 Output

3.2.4 Frequency Response

4 AUDIO AMPLIFIER STAGE WITH PT2333

4.1 General Description of PT2333:
The PT2333 is a Class-D power amplifier designed for audio equipments, maximum
output power can reach up to 2.5W (VDD=5V, RL=4, THD=10%). The PT2333 composed
of exclusively designed Class-D circuitry (patented) by PTC, along with the most advanced
semi-conductor technology. When compared to the traditional Class-AB amplifiers, the
PT2333s has a much higher efficiency (>80%), low heat dissipation, and produces superior
audio quality. PT2333s external circuitry is simple and easily accessible, and consists of
flawless self-protection capabilities. The chips packaging is small, thus it occupies an
insignificant amount of space on the circuit board; therefore, making it the predominant
choice when it comes to audio amplifiers.

4.2 Features of PT2333:

CMOS technology
Operating voltage range from 2.7V up to 5.5V
Differential analog input
Maximum output power 2.5W(4) @ THD=10%
Output low-pass LC filter is not required.
Voltage gain determinate by the external resister
Contains shutdown function
POP noises free in shutdown and power ON/OFF period
Built-in short circuit protection
Built-in overheat protection

10

 High efficiency (8 load >85%), low heat dissipation

Available in MSOP 10-pin and WLCSP 9-pin miniature packages

4.3 Pin Configuration of PT2333:

WLCSP-9 PACKAGE:

5 MICROCONTROLLER (MSTAR)
5.1 Genaral Description
The MST9WB6JS is a high performance and fully integrated IC for multi-function LCD
monitor/TV with resolutions up to UXGA (1600*1200)/WSXGA+ (1680*1050). It is
configured with an integrated DVI/HDCP/HDMI receiver, a multi standard TV video and
audio decoder, a video deinterlacer, a scaling engine, the MSTARACE-3 color engine, an onscreen display controller and a built in output panel interface. By use of external frame buffer,
PIP/POP is provided for multimedia applications. Furthermore, 3D video decoding and
processing are fulfilled for high-quality TV applications. To further reduce system costs, the
MST9WB6JS also integrates intelligent power management control capability for green-mode
requirements and spread spectrum support for EMI management.

11

5.2 Features

12

6 INTEGRATED DVB-T RECEIVER (CHEERTEK)

6.1 General Description
CT216T is a highly integrated single chip for DVB-T compliant STB solution. Compared
with Cheertek's previous generations of STB receiver devices. CT216T further interates
COFDM demodulator USB 2.0 HS host controller, memory card reader, 1/2-bit SPIFlash
interface, audio DAC, PWM in/out and SAR-ADC functions. In additiont special
enhangements are provided such as MPEG-4 video decoding, 16-bit OSD with anti-flickering,
HW JPEG decoding, flesh tone and black-white extensions, and improvement of small video
quality.
CT216T includes COFDM demodulator transport stream de-multiplexer, DVB-CSA
compliant de-scrambler, RISC MPUs, MPEG-1/2/4 AV decoder, digital T\/ encoder, audio
DACs, USB 2.0 HS host controller, memory card reader, smart card reader, CI controller and
other peripherals.
Cli216T is designed in focus on the market of single tuner input product which makes, it a
cost effective solution. Supports include free to air, conditional access for SC (Smart card)
and CI portable devices, PVR, LCD TV, and other DVB-T applications.
Digital Front End Diagram:

6.2 Features
COFDM Demodulator
ETSI EN 300 744 DVB-T NorDig Unified 1.0.3, and D-book compliant
Automatic spectral inversion, detection
Integrated ADC
Direct IF (36.167 MHz or 43.75 MHz) or low IF (4.57 MHz) supported
Single IF AGC or dual RF/lF AGC controls with modulabon
Impulsive noise cancellation
Carrier acquisition range: 400 kHz (extensible to 600 kHz in 8MHz BW)
13

Adjacent channel interference (ACI) filter,for supporting 6, 7, and 8MHz channels

with one 8MHz analog filter
Co-channel interterence (CCl) supression
RF signal strength monitor

MPU
Three 32-bit RISC MPU run up to 166MHz with total 448DMIPS
8KB I-Cache and 8KB D-Cache
Two general purpose timers
Watchdog timer
DSU for source level debug
Memory
6-bit SDRAM controller supports up to 32MB (16MB for l28-pin)
Unified memory architecture
Parallel flash (216-pin only)
1/2-bit SPI flash
Transport De-multiplexing
TS, PES, and ES demultiplexing
OneTS path
CI CAM interface (216-pin only)
32 general purpose PID filters
32 Section filters
CRC-32 accelerator
DVB-CSA de-scramblers
Video Decoding and Processing
MPEG-2 MP@ML
MPEG-4 SP&ASP
PAL/NTSC format conversion
3:2 pull down
Zoom in/out from 1/16X to 16X
HW JPEG decode
4/8/16-bit OSD with anti-flickering
On chip NTSC/PAL TV encoder
CVBS, S-VHS, and component video
VBI insertion for Teletext, CC and WSS
ITU-R BT.601 and ITU-R BT.656 outputs
Flesh tone extension
Black/white extension,
Audio Decoding and Processing
MPEG-1: layer 1/2/3
MPEG-2: layer 1/2
Decode MPEG-2 and MPEG-1 audio at sampling frequency of 16K, 22.05K, 24K,
32K, 44.1K, and 48KHz
Decode CU-DA at sampling frequency of 44.1 KHz
14

SPDIF out for AC-3 by-pass

Embedded 2 channels audio DAC for L/R outputs
Digital mute control and volume adjustment

OSD(On Screen Display)

There are total 9 display planes: border; background. video. RS1 (Rectangle Strip 1),
RS2, OSD, RS3, RS4, and cursor.
4/8l16-bit OSD with anti-flickering and anti-flutter
Support alpha-blending per color
Adjustable brightness control in window
Bitmap OSD
Support horizontal pixel duplication to enlarge bitmap automatically
Support sub-region redraw to facilitate bitmap display.
Digitnal TV Encoder
NTSC-M, PAL-B, D, G, H, I, Nc, M encoding
Four video DACs to provide 6 configuration output: modes
Support CVBS, S-VHS. and component video outs
VBI insertion for Teletext, CC and WSS
Color burst amplitude control
Programmable sync. level
On chip, color-bar generator
High Speed I/O
USB 2.0 HS host controller
Memory card reader with SD, MMC, and MS interfaces
Compliant with SD spec. 1.1 and MMC spec. 4.0 with 1-bit & 4-bit modes.
Compliant with Memory Stick Pro format spec. 1.02 and Memory stick format spec
1.43 with 1-bit and 4-bit modes.
Peripherals
Up to 3 full duplex UART with 16-byte FIFO
2-wire serial (2WS) in master mode .. .
Up to 2 IS0-7816 compliant SC (1 in 128-pin, can also be used as UART)
5 digits 7-Segrnent LED control
5x3 two-dimension key scan
2 SAR-ADC input
4 PWM input/output
1 HW IR command decode
GPIO
Electrical and Physical Characteristics
Capable of using single 27MHz clock input crystal
1.8V and 3.3V dual power supply
Power standby mode
PQFP-128 (CT216T-Z) or LQFP-216 (CT216T-R) package

15

7. 4MX16 BIT SYNCHRONOUS DRAM ( DIGITAL SIDE

SDRAM)
7.1 General Description
The EM638165 SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It
is internally configured as 4 Banks of 1M word x 16 DRAM with a synchronous interface (all
signals are registered on the positive edge of the clock signal, CLK). Read and write accesses
to the SDRAM are burst oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. Accesses begin with the
registration of a BankActivate command which is then followed by a Read or Write
command. The EM638165 provides for programmable Read or Write burst lengths of 1, 2, 4,
8, or full page, with a burst termination option. An auto precharge function may be enabled to
provide a self-timed row precharge that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy to use. By having a programmable
mode register, the system can choose the most suitable modes to maximize its performance.
These devices are well suited for applications requiring high memory bandwidth and
particularly well suited to high performance PC applications.

7.2 Features

Fast access time from clock: 4.5/5/5.4 ns

Fast clock rate: 200/166/143 MHz
Fully synchronous operation
Internal pipelined architecture
1M word x 16-bit x 4-bank
Programmable Mode registers
CAS Latency: 2, or 3
Burst Length: 1, 2, 4, 8, or full page
Burst Type: interleaved or linear burst
Burst stop function
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V 0.3V power supply
Interface: LVTTL
54-pin 400 mil plastic TSOP II package
Pb free and Halogen free
60-ball 6.4mm x 10.1mm VFBGA package
Pb free

16

7.3 Pin Configuration

17

8 S25FL016A - 16 Megabit Cmos 3.0 Volt Flash Memory with

50-Mhz (Serial Peripheral Interface)Bus
8.1 General Description
The S25FL016A is a 3.0 Volt (2.7V to 3.6V), single-power supply Flash memory device.The
device consist of thirty-two sectors, each with 512 Kb memory.
The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output).
The devices are designed to be programmed in-system with the standart 3.0 volt Vcc supply.
The memory can be programmed 1 to 256 bytes at a time, using the Page Praogram
command. The device supports Sector Erase and Bulk Erase commands.
Each device requires only a 3.0 volt power supply (2.7V to 3.6V) for both read and write
functions. Internally generated and regulated voltages are provided for the program
oprerations. This device does not require a Vpp supply.

8.2 Distinctive Characteristics

Architectural Advantages

Single Power supply operation

Full voltage range: 2,7 to 3,6V read and program operations

Memory Architecture

Thirty-two sectors with 512 Kb each

Program

Page program (up to 256 bytes) in 1,4 ms (typical)

Program operations are on a page by page basis

Erase

0,5s typical sector erase time

10s typical bulk erase time

Cycling Endurance

100,000 cycles per sector typical

18

Data Retantion

20 Years Typical

Device ID

JEDEC standart two-byte electronic signature

RES command one-byte electronic signature for backward compatibility

Process Technology

Manufactured on 0,20 m MirrorBit process technology

Package Option

Industry standart pinout

16-pin SO package (300 mils)
8-pin SO package (208 mils)
8-Contact WSON Package (6x8 mm), Pb Free

Performance Characteristics

Speed
50Mhz clock rate (miximum)
Power Saving Standby Mode
Standby Mode 50 A (max)
Deep Power Down Mode 1,3A (typical)

Memory Protection Features

Memory Protection

W# pin works in conjuction with Status Register Bits to protect specified memory
areas
Status Register Block Protection bits (BP2, BP1, BP0) in status register configure
parts of memory as read-only

Software Features
SPI Bus Compatible Serial Interface

19

9 4M x 16 bit Synchronous DRAM (ANALOG SIDE SDRAM)

9.1 General Description
The EM638165 SDRAM is a high-speed CMOS synchronous DRAM containing 64Mbits. It
is internally configured as 4 Banks of 1M word x 16 DRAM with a synchronous interface (all
signals are registered on the positive edge of the clock signal, CLK). Read and write accesses
to the SDRAM are burst oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. Accesses begin with the
registration of a Bank Activate command which is then followed by a Read or Write
command. The EM638165 provides for programmable Read or Write burst lengths of 1, 2, 4,
8, or full page, with a burst termination option. An auto precharge function may be enabled
to provide a self-timed row precharge that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy to use. By having a programmable
mode register, the system can choose the most suitable modes to maximize its performance.
These devices are well suited for applications requiring high memory bandwidth and
particularly well suited to high performance PC applications.

9.2 Features
Fast access time from clock: 4.5/5/5.4 ns
Fast clock rate: 200/166/143 MHz
Fully synchronous operation
Internal pipelined architecture
1M word x 16-bit x 4-bank
Programmable Mode registers
- CAS Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V 0.3V power supply
Interface: LVTTL
54-pin 400 mil plastic TSOP II package
- Pb free and Halogen free
60-ball 6.4mm x 10.1mm VFBGA package
- Pb free

20

9.3 Pinning

21

10 POWER STAGE
MB45 has two power options which is changed according to TV size and number of lambs.

10.1 IPS 15 Option

IPS16 power board is used with 19 MB45TV set (2 lamp panel) and IPS17 power board is
used with 22 MB45TV set (4 lamp panel). These are supplied 12V, 5V_stby and 5V panel
supplies.
Also regulators, step-downs and mosfet generate 3V3, 3V3_Stby, 5V_Tuner and 1,25V_Stby
voltages for other different part of the chassis.
Audio supply is 5V in this case.

22

11 IC SPECIFICATIONS
11.1 8K Smart Serial EEPROM 24C64
General Description
24C64 is a 64Kbit CMOS non-volatile serial EEPROM organized as 8K x 8 bit memory. This
device confirms to Extended IIC 2-wire protocol that allows accessing of memory in excess
of 16Kbit on an IIC bus. This serial communication protocol uses a Clock signal (SCL) and a
Data signal (SDA) to synchronously clock data between a master (e.g. a microcontroller) and
a slave (EEPROM). 24C64 is designed to minimize pin count and
simplify PC board layout requirements.
24C64 offers hardware write protection where by the entire memory array can be write
protected by connecting WP pin to VCC. This section of memory then becomes unalterable
until the WP pin is switched to VSS.
Features

Extended operating voltage: 2.5V to 5.5V

Up to 400 KHz clock frequency at 2.5V to 5.5V

Low power consumption
0.5mA active current typical
10A standby current typical
1A standby current typical (L version)
0.1A standby current typical (LZ version)

Schmitt trigger inputs

32 byte page write mode

Self timed write cycle (6ms typical)

Hardware Write Protection for the entire array

Endurance: up to 100K data changes

Data Retention: Greater than 40 years

Packages: 8-Pin DIP, 8-Pin SO and 8-Pin TSSOP

Temperature range
Commercial: 0C to +70C
Industrial (E): -40C to +85C
Automotive (V): -40C to +125C
Pin Configuration

23

11.2 TL062
It is used as a pre-amplifer for scart audio output on MB45 main board.
General Description
Low-power JFET-input operational amplifier
Features

Very Low Power Consumption

Typical Supply Current . . . 200 A (Per Amplifier)
Wide Common-Mode and Differential Voltage Ranges
Low Input Bias and Offset Currents
Common-Mode Input Voltage Range Includes VCC+
Output Short-Circuit Protection
High Input Impedance . . . JFET-Input Stage
Internal Frequency Compensation
Latch-Up-Free Operation
High Slew Rate . . . 3.5 V/s Typ

Pin Configuration

24

11.3 FSA3157
It is used for switching DVD_Y/C video signal and DVB_Y/C video signal on the MB45
mainboard, also there are two jumpers option for by-passing this switch.
General Description
FSA3157 is a high performance, single-pole/double-throw (SPDT) Analog Switch or 2:1
Multiplexer/Demultiplexer Bus Switch. The device is fabricated with advanced sub-micron
CMOS technology to achieve high speed enable and disable times and low On Resistance.
The break before make select circuitry prevents disruption of signals on the B Port due to both
switches temporarily being enabled during select pin switching. The device is specified to
operate over the 1.65 to 5.5V VCC operating range. The control input tolerates voltages up to
5.5V independent of the VCC operating range.
Features
_ Useful in both analog and digital applications
_ Space saving SC70 6-lead surface mount package
_ Ultra small MicroPak
leadless package
_ Low On Resistance; < 10 on typ @ 3.3V VCC
_ Broad VCC operating range; 1.65V to 5.5V
_ Rail-to-Rail signal handling
_ Power down high impedance control input
_ Overvoltage tolerance of control input to 7.0V
_ Break before make enable circuitry
_ 250 MHz - 3dB bandwidth
Pin Configuration

25

11.4 FDS8878
It is used for providing 5V tuner supply.
General Description
This N-Channel MOSFET has been designed specifically to improve the overall efficiency of
DC/DC converters using either synchronous or conventional switching PWM controllers. It
has been optimized for low gate charge, low rDS(on) and fast switching speed.
Features

rDS(on) = 14m, VGS = 10V, ID = 10.2A

rDS(on) = 17m, VGS = 4.5V, ID = 9.3A

High performance trench technology for extremely low rDS(on)

Low gate charge

High power and current handling capability

RoHS Compliant
Pin Configuration

11.5 ST24LC21 (Optional)

ST24LC21 is an EEPROM which is used for storing the VGA output resolution information.
General Description
The ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM),
organized by 8 Bits.This device can operate in two modes: Transmit Only mode and I2C
bidirectional mode. When powered, the device is in Transmit Only mode with EEPROM data
clocked out from the rising edge of the signal applied on VCLK. The device will switch to the
I2C bidirectional mode upon the falling edge of the signal applied on SCL pin. The
ST24LC21 cannot switch from the I2C bidirectional mode to the Transmit Only mode (except
when the power supply is removed). The device operates with a power supply value as low as
2.5V. Both Plastic Dual-in-Line and Plastic Small Outline packages are available.

26

Features
1 Mllon Erase/Wrte Cycles
40 Years Data Retenton
2.5v To 5.5v Sngle Supply Voltage
400k Hz Compatblty Over The Full
Range Of Supply Voltage
Two Wre Seral Interface I2c Bus
Compatble
Page Wrte (Up To 8 Bytes)
Byte, Random And Sequental Read
Modes
Self Tmed Programmng Cycle
Automatc Address Incrementng
Enhanced Esd/Latch Up
Performances
Pin Configuration

11.6 TDA1308T
TDA1308T is a class AB stereo headphone driver which is used as a headphone amplifier on
MB45 mainboard.
General Description
The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8, DIP8
or a TSSOP8 plastic package. The device is fabricated in a 1 mmCMOS process and has been
primarily developed for portable digital audio applications.
Features
Wide temperature range
No switch ON/OFF clicks
Excellent power supply ripple rejection

27

 Low power consumption

Short-circuit resistant
High performance
high signal-to-noise ratio
high slew rate
low distortion
Large output voltage swing.
Pin Configuration

11.7 STMP2161
STMP2161 is a current limiter which is used for switching the USB interface on MB45
mainboard.
General Description
The STMPS2161 power distribution switches are intended for applications where heavy
capacitive loads and short circuits are likely to be encountered. These devices incorporate 90
m N-channel MOSFET high-side power switches for power-distribution. These switches are
controlled by a logic enable input.
28

When the output load exceeds the current-limit threshold or a short is present, the device
limits the output current to a safe level by switching into a constant-current mode. When
continuous heavy overloads and short circuits increase the power dissipation in the switch,
causing the junction temperature to rise, a thermal protection circuit shuts the switch off to
prevent damage. Recovery from a thermal shutdown is automatic once the device has cooled
sufficiently. Internal circuitry ensures the switch remains off until a valid input voltage is
present.
Features
90 m high-side MOSFET switch
500/1000 mA continuous current
Thermal and short-circuit protection with
overcurrent logic output
Operating range from 2.7 V to 5.5 V
CMOS- and TTL-compatible enable inputs
Undervoltage lockout (UVLO)
12 A maximum standby supply current
Ambient temperature range, -40C to 85C
8 kV ESD protection
Reverse current protection
Fault-blanking
Pin Configuration

29

11.8 AZ1045
It is used for protecting the USB interface on MB45 mainboard.
General Description
AZ1045-04SU is a design which includes ESD rated diode arrays to protect high speed data
interfaces. The AZ1045-04SU has been specifically designed to protect sensitive components
which are connected to data and transmission lines from over-voltage caused by Electrostatic
Discharging (ESD).
AZ1045-04SU is a unique design which includes ESD rated, ultra low capacitance steering
diodes and a unique design of clamping cell which is an equivalent TVS diode in a single
package. During transient conditions, the steering diodes direct the transient to either the
power supply line or to ground line. The internal unique design of clamping cell prevents
over-voltage on the power line, protecting any downstream components. Besides, there is a
back-drive protection design in AZ1045-04SU for power-down mode operation. AZ104504SU may be used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4
(15kV air, 8kV contact discharge).
Features

ESD Protect for Transition Minimized Differential Signaling (TMDS) channels

Protects four I/O lines and one VDD line

Provide ESD protection for each channel to
Revision 2008/01/23 2008 Amazing Micro. 1 www.amazingIC.com
IEC 61000-4-2,(ESD) 15kV (air), 8kV (contact)
IEC 61000-4-5 (Lightning) 4.7A (8/20s)

For below 5V operating voltage

Ultra low capacitance : 0.55pF typical

0.03pF matching capacitance between the TMDS intra-pair

Fast turn-on and Low clamping voltage

Array of ESD rated diodes with internal equivalent TVS diode

30


Solid-state silicon-avalanche and active circuit triggering technology

Back-drive protection for power-down mode

Lead-free version available
Pin Configuration

11.9 MP1583
MP1583 is a step-down regulator which is used for providing 3.3V DC from 12V DC and 5V
Vcc from 12V.
General Description
The MP1583 is a step-down regulator with a built in internal Power MOSFET. It achieves 3A
continuous output current over a wide input supply range with excellent load and line
regulation. Current mode operation provides fast transient response and eases loop
stabilization. Fault condition protection includes cycle-by-cycle current limiting and thermal
shutdown. Adjustable soft-start reduces the stress on the input source at turn-on. In shutdown
mode the regulator draws 20A of supply current.
The MP1583 requires a minimum number of readily available external components to
complete a 3A step down DC to DC converter solution.

31

Features
3A Output Current
Programmable Soft-Start
100m Internal Power MOSFET Switch
Stable with Low ESR Output Ceramic Capacitors
Up to 95% Efficiency
20A Shutdown Mode
Fixed 385KHz frequency
Thermal Shutdown
Cycle-by-Cycle Over Current Protection
Wide 4.75 to 23V operating Input Range
Output Adjustable From 1.22 to 21V
Under Voltage Lockout
Available in 8 pin SOIC Package
3A Evaluation Board Available
Pin Configuration

32

11.10 LM1117
It is a regulator which is used for providing 1.8V from 3.3V for DVB side.
General Description
The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of
load current. It has the same pin-out as National Semiconductors industry standard LM317.
The LM1117 is available in an adjustable version, which can set the output voltage from
1.25V to 13.8V with only two external resistors. In addition, it is also available in five fixed
voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V. The LM1117 offers current limiting and thermal
shutdown. Its circuit includes a zener trimmed bandgap reference to as-sure output voltage
accuracy to within 1%. The LM1117 series is available in SOT- 223, TO-220, and TO-252
D-PAK packages. A minimum of 10F tantalum capacitor is required at the output to improve
the transient response and stability.
Features

Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions

Space Saving SOT-223 Package
Current Limiting and Thermal Protection
Output Current 800mA
Line Regulation 0.2% (Max)
Load Regulation 0.4% (Max)
Temperature Range
LM1117 0C to 125C
LM1117I -40C to 125C

Pin Configuration

33

11.11 MP2109
It is a step-down converter which is used for seting the 1.26V STBY Output and 3.3V STBY
Output.
General Description
The MP2109 contains two independent 1.2MHz constant frequency, current mode, PWM
step-down converters. Each converter integrates a main switch and a synchronous rectifier for
high efficiency without an external Schottky diode. The MP2109 is ideal for powering
portable equipment that runs from a single cell Lithium-Ion (Li+) battery. Each converter can
supply 800mA of load current from a 2.5V to 6V input voltage. The output voltage can be
regulated as low as 0.6V. The MP2109 can also run at 100% duty cycle for low dropout
applications.
Features
Up to 95% Efficiency
1.2MHz Constant Switching Frequency
800mA Load Current on Each Channel
2.5V to 6V Input Voltage Range
Output Voltage as Low as 0.6V
100% Duty Cycle in Dropout
Current Mode Control
Short Circuit Protection
Thermal Fault Protection
<0.1A Shutdown Current
Internally Compensated
Space Saving 10-Pin QFN Package
Pin Configuration

34

11.12 FDC642P
FDC642P is a p-channel mosfet which is used for switching the panel supply.
General Description
This P-channel 2.5V specified MOSFET is produced using advanced PowerTrench process
that has been especially tailored to minimize on state resistance and yet maintain low gate
charge for superior switching performance.
These devices have been design to offer exceptional power dissipation in a very small
footprint for applications where larger packages are impractical.
Features

Fast switching speed.

-4 A,-20V. RDS(on) = 0.065 ohm @ VGS=-4.5V
RDS(on) = 0.100 ohm @ VGS=-2.5V
Low gate charge (7.2nC typical).
High performance trench technology for extremely low RDS(on)
SuperSOT-6 package:small footprint (72% smaller than Standard SO-8;low profile
(1mm thick).

35

Pin Configuration

11.13 XC5000 (Optional)

XC50000 is a RF to Baseband Silicon Tuner and the usage of XC5000 is optional on
MB45TV set.
General Description
The Single-Chip Multi-Standard Tuner + VIF/SIF XC5000 supports all analog TV formats
transmitted worldwide in the 42-864 MHz band on either cable or terrestrial broadcast
channels. It implements on-chip tuning, channel filtering and demodulation, without external
(SAW) filters and has no manually tunable parts. The broadband tuner converts the selected
channel into an Intermediate Frequency (IF), which is then sampled by an internal highresolution analog-to-digital converter (A/D) for further processing. For analog broadcast
standards the video signal is demodulated and output as a composite video base-band signal
(CVBS) through a high-performance smoothing filter. The sound carrier is filtered and output
as a 2nd Sound IF (SIF) or demodulated and output as a mono TV sound. In DTV mode, the
Digital TV signals are filtered using a standard-dependent high-rejection channel fitler and
converted to a user-programmable output frequency. At the output of the D/A converter, the
DTV signal is low-pass filtered using a high-performance smoothing filter and input to a
variable gain amplifier. The amplifier gain can be controlled via an external analog signal on
Vagc.
Features
_ Standard specific digital picture carrier recovery:
Alignment-free
Quartz-stable and accurate
No externally tunable parts
_ Multi-standard RF-to-baseband receiver
_ Integrated RF PLL filter reducing risk of noise pickup on the board
_ Standard specific digital video/audio splitting
_ Integrated DSP for high quality demodulation both in analog and digital modes
_ Integrated smoothing filters for CVBS output (analog mode) and IF-output (digital mode)
_ Supports DDI (digital direct interface) interfacing to the digital demodulator equipped with
DDI, eliminating the quantization noise (from DAC/ADC).
_ Onboard digital processing for the following analog standards: B/G, D/K, I, L/L and M/N
_ Inter-carrier sound output or mono analog sound direct output
36

_ Mono analog sound demodulation for both AM (SECAM L/L') and FM, including de
emphasis
_ Compatible with a wide variety of signal conditions, including video overmodulation,
airplane flutter and nonstandard sound.
_ DTV Mode for operation with external DTV demodulator. XC5000 applies filters and
converts signal to arbitrary output frequency. Supports standards such as ATSC, OpenCable,
DVB-C, DVB-T, ISDB-T, DMB-TH.
_ Excellent adjacent channel rejection
_ Low noise and excellent SNR
_ Dual input capability to address both TV and FM radio reception
_ Controlled via I2C-bus, up to four units on the I2C bus via address select pin
_ 42 to 864 MHz input frequency range
_ Low power dissipation
_ Small footprint, QFN48
_ Lead-free manufacturing
The Single-Chip Multi-Standard Tuner plus VIF/SIF, XC5000 combines both tuning and
demodulation functions for worldwide cable and terrestrial analog TV in one small package.
It also includes high performance filtering and frequency-conversion functions for DTV with
an external demodulator through LOW-IF or DDI. The XC5000s integrated tuner is based on
proprietary tunable wideband active RF filtering technology that eliminates the need for
special external components. The XC5000s high sensitivity, coupled with at least 65 dB
image rejection makes it ideal for antenna and cable reception. The XC5000s integrated
digital demodulation for analog TV performs the entire multi-standard Quasi Split Sound
(QSS) TV IF processing, AGC, video demodulation, generation of the 2nd sound IF (SIF) or
mono TV sound for all worldwide standards. The XC5000 provides two inputs to address
both TV and FM radio reception. Xceive's breakthrough patent-pending technology provides
a powerful combination of high dynamic range with a large tunable range uniquely enabling
superior pictures from off-air and cable applications. Supported formats include NTSC, PAL
and SECAM. The XC5000 also supports most DTV standards including ATSC/8-VSB,
OpenCable DVB-C, QAM64 & QAM256, DVB-T, ISDB-T and DBM-TH, and is compatible
with most digital demodulators on the market today.
Pin Configuration

37

38

12 BLOCK DIAGRAMS
12.1 General Block Diagram

12.2 Integrated DVB-T Receiver Block Diagram

12.3 17MB45 Analog Front-End

12.4 17MB45 Digital Front-End

42

12.5 17MB45 Digital CI ve Smart Card Interface

12.6 17MB45 HDMI Inputs

43

12.7 17MB45 Analog Interface MSTAR IC

12.8 17MB45 Analog Input / Output

12.9 17MB45 LVDS Output

12.10 17MB45 Power

46

SOFTWARE UPDATE DESCRIPTION

1. MB45 Analog Part Software Update With Bootloader
Procedure
1..1

The File Types Used By The Bootloader

All file types that used by the bootloader software are listed below:
1. The Binary File : It has .bin extension and it is the tv application. Its size is 1920 Kb.
2. The Config Binary File : It has .cin extension and it is the config of the tv application.
Its size may be 64 Kb or a few times 64 Kb.
3. The Test Script File : It has .txt extension and it is the test script that is parsed and
executed by the bootloader. It dont have to be any times of 64 Kb.
4. The Test Binary File : It has .tin extension and it is used and written by the test groups.
It is run to understand the problem part of the hardware.
Alltough a file that is used by the bootloader can be had any one of these extensions, its name
has to be VESTEL_S and it has to be located in the root directory of the usb device.

1..2

Usage of The Bootloader

1) The starting to pass through : The chassis is only powered up.

2) The starting to download something : When chassis is powered up the menu key has to
be pushed.Before the chassis is powered up and if any usb device is plugged to the usb
port, the programme is downloaded from usb firstly. Any usb device is plugged to usb
port , user must open hyperterminal in the pc and connect pc to chassis via Mstar
debug tool and any one of scart,dsub9 or I2c connectors.
Serial connection settings are listed below:
Bit per second: 115200
Data bits: 8
Parity: None
Stop bits: 1
Flow control: None
In this case the bootloader sofware puts C character to uart. After repeating C characters
are seen in the hyperterminal user can send any file to chassis by selecting
Transfer -> Send File menu item and choosing 1K Xmodem from protocol section.

Figure 1. The Sample Output Before Sending The File

1..3

EEProm Update

To Update eeprom content via uart scart,dsub9 or i2c with Mstar tool can used.
Serial connection settings are listed below:

Bit per second: 9600

Data bits: 8
Parity: None
Stop bits: 1
Flow control: None

Programming menu item is choosed in the service menu and switch HDCP Key Update
Mode from off to on.

Figure 2. The Programming Service Menu

After then you must see Xmodem menu in the hyperterminal.To download hdcp key press k
or to download eeprom content press w.

Figure 3. Xmodem Menu

If the repeated C characters are seen you can transfer file content via select Transfer>Send File and choose Xmodem protocol and click the Send button.

Figure 4. The Starting To Send

1..4

HDCP Key Upload Procedure

1) Turn on TV set.
2) Open a COM connection using fallowing parameters and select ISP COM Port No

Baud Rate: 9600 bps

Data Bits: 8
Stop Bits: 1
Parity: None
Flow Control: None

3) Enter service menu by pressing 4 7 2 5 consecutively while main menu is open

4) Select 9. Programming
5) Select HDMI HDCP Update Mode yes.
6) On Hyper Terminal Window press k
7) Click on send file under Transfer Tab.
8) Select Xmodem and choose the HDCP key to be uploaded.
9) Press send button
10)Restart TV set

2. MB45 Digital Part Software Update

2..1

MB45 Digital Software Update From VGA

Usage of VGA Pins:

Pin 4: RXD0
Pin 11: TXD0
Pin 8: Ground

Adjusting DTV Download Mode:

1. Power on the TV.
2. Exit the Stby Mode.
Adjusting HyperTerminal:
1. Connect the MB45 VGA Interface to VGA.
2. Also connect the MB45 VGA Interface to PC.
3. Open HyperTerminal.
4. Determine the COM settings listed and showed below.
Bit per second: 115200
Data bits: 8
Parity: None
Stop bits: 1
Flow control: None

Figure 5.COM Properties Window

5. Click OK.
Software Updating Procedure
1. In the HyperTerminal Menu, click the Connect button.
2. Exit the Stby Mode.
3. The Space button on the keyboard must be pressed, when the following window can be
seen.

Figure 6.Selection Window

4. Press the 2 button on the keyboard for choosing 2. Upgrade Application with Xmodem.
5. Repeating C characters are seen in the HyperTerminal menu.

Figure 7. The Sample Output Before Sending The File

6. Click the Send button on the HyperTerminal

7. Select the Filename xxxx_slot1.img using Browse.
8. Choose the 1K Xmodem from Protocol option.

Figure 8. Selection of File

Figure 9. File and Protocol Selection Window

Note: In the Software updating Procedure section, when the first C character is seen, the
filename selection process must be finished before 10 seconds. If the process can not be
finished, the file sending operation will be cancelled. The following figure shows this
situation.
8

Figure 10. Capture of Receving Data Failing

9. When sending the file the following window must be seen.

Figure 11. Capture of Sending Process

10. After the sending process the following HyperTerminal window must be seen.

Figure 12. Capture of End of The Sending Process

11. For sending second program file, the Software Updating Procedure must be repeated from
the step X. Select the Filename xxxx_slot2.img using Browse.
12. After sending the second program file, the Software Updating Procedure will be succesful.
Note: After the File Sending Process,
1. Upgrade Application with FUM
2. Upgrade Application with Xmodem, options must be seen.

Figure 13. End of The Sending Process

10

Checking Of The New Software

1. Turn off and on the TV.
2. Enter the Setup submenu in the DTV Menu.
3. Choose the Configuration option.
4. For controlling new software, check the Receiver Upgrade option.

2..2

MB45 Digital Software Update From USB

Software upgrade is possible via USB disk by folowing the steps below.
1. Copy the bin file, including higher version than the software loaded in flash, into the USB
flash memory root directory. This file should be named up.bin.
2. Insert the USB disk.
3. Digital module performs version and CRC check. If version and CRC check is successful,
then a message prompt appears to notify user about new version. If the user confirms loading
of new version, upgrade.bin file is written into flash
unused slot.
4. Digital module disables the previous software in the flash and then a system reset is
performed.
5. After the reset, digital module starts with new software.
Revert operation:
With revert operation, it is possible to downgrade the software.
Revert operation is very similar to upgrade process. In the revert operation, file name should
be f_up.bin. Also user confirmation is not asked.
1. Copy the bin file into the USB flash memory root directory. This file should be named
force_upgrade.bin.
2. Insert the USB disk.
3. A lower version than the software in flash can be loaded with revert operation. Digital
module performs only CRC check. If CRC check is successful, then force_upgrade.bin file is
written into flash unused slot.
4. Digital module disables the previous software in the flash.
5. A message prompt is displayed to notify user about end of revert process.
6. Power off/on is required to start digital module with the new software.
For controlling new software, check the Receiver Upgrade option.

11

R790
1k

SC1_G

F103

F102
2

600R

R116
100R

C778

SC1_AUD_R_OUT
1

C786
1

SC1_R_OUT

R800
20k

R798
33k

1
2

V+

C134
100n
10V
2

12V_VCC

220p
50V

R797
33k

10V
10u

D105
BAV70

50V

2
1

27p

C107

50V

2
1

27p

SC1_AUD_L_OUT

C775

F
2

3
4

600R

C779

1u
16V

4n7
50V

100p
50V
R794
82k

100n
16V
2

C112

F721
2

C774

4n7
SC1_AUD_R_IN50V

600R
1

SC1_AUD_R_OUT
1

C102

C5V6

D101

10V
10u

3n3

C780

SC1_AUD_L_OUT

C116

50V

2
1

CN101

C106

VGA_R
5
D102
4
NUP4004M5 2

600R

C110
50V

R118
100R

VGA_G

12V_VCC

SCART_AUD_R_IN

33k
R796

DIGITAL SW UPDATE
VGA_B

3
1

SC1_AUD_L_IN

600R

N.C. hindistan opt.

RX/SCL_SC

F105

C784
1u
16V

F104
1

SCART_AUD_L_IN

V+

R795
33k

3n3

100n
10V

TX/SDA_SC

C109

PRE-AMP for SCART

C119

C111
50V

UART0_RXD0

27p

GND

UART0_TXD0

C105

C5V6

R123
4k7

SC1_PIN8

C15V
SC1_B
50V
220p

VGA_HSNC
R761
33R
R760
33R N.C.
1

D104

3n3
50V

100R

R119
22k
D108

R4

C101

RX/SCL_SC

SDA

VGA_VSNC
1

SAV_AUD_R_IN

600R

10u
10V

2
1

A2

R109

SCL

VGA_DDC_5V

SAV_AUD_L_IN

F106

C773

10

RED

3n3

600R

A1

TP105

4
3
1

C118

10

WP

ST24LC21

WHT

75R
R120

A0

U101

F108

12

VCC

TP104
TP103
TP102

6
5
1

11

YEL

50V
220p

13

C113

TX/SDA_SC

75R
R121

11
50V
C103

JK101

R3

R106
2k2
R105
2k2

SC1_R

14

R2

12
1

50V
220p

15

VGA_DDC_5V

R115
100R
1
R1

SC1_FB

R110
10k
R113
10k
R114
10k
8

13

SAV_CVBS
47R
R122

C108
100n
10V

15

SC1_CVBS_OUT

C115

2
1 RED

TP101

2
1

10p
50V

JK604

3
1

220p
50V

C114

3
WHT

SIDE AV INPUT
2

5V_VCC

1n
50V

16

C3

50V
220p
2

VGA INPUT

CVBS0_OUT

R104
33k

R792
1k

5
D103
4
2 NUP4004M5

4
YEL

R126
300R

10u
10V

R101
100R

5
D107
4
2 NUP4004M5

3
1

3
1

5
D106
4
2 NUP4004M5

SC1_CVBS_IN

14

17

47p
50V

R125
75R

SC1_CVBS_OUT

SCART_AUD_R_IN

R117
220R

C104
Q101
BC848B

INDIA OPTION

19

C129
100n
10V

3
3

C117
SC1_CVBS_IN

18

1N4148

C787
1n
50V

SCART_AUD_L_IN

20

100n
10V

TAGC

Q102
BC858B

R791
1k

U707
TL431SAMF2

6V3
100u
C138

B
AVDD_RXV

55

R103
68k

5V_TUN
C135
100n
10V

GND_RXV

54

C120

330R

VIFP

53

5V_TUN

330R
1

12V_VCC

S4

VIFP

D110
1

B0

VIFM

52

330R

GND

FSA3157
A

SIFM

51

R134
5k6

VCC

SIFP

50

100n
10V
R133
12k

GND_RXS

49

F719

R124
470R

12V_VCC

SCART LT1

B1

U1

AVDD_RXS

48

SCART VIDEO OUTPUT AMPLIFIER

R102
390R

10u
10V

SC101

F722

5V_TUN

330R

RF_AGC

5V_VCC

21

3V3_VCC

DVD/IDTV_SW

10u
10V

F111
2

C130

2u2

C1
100n
10V

VIFP

Q716
BSH103

2R1

C132

3
BSN20

R144
10R
1

1 IN1
OUT1 4
K3958M
2 IN2
OUT2 5
GND

330R

SIFM

VIFM

VR27

47

10n
16V

FDS8878

SIFP

5V_TUN

5V_TUN

F109

VIFM

Q1
5V_VCC

330R

Z102

AVDD_MPLL

C126

C122

U102
MST9WB6JS

45

Q103
2

C133

R128
6k8

TH1

C127
220n
10V

46
1

SCL_TUNER

Q104
BF799

10n
16V

SCL

R131
100k

SIF_CTL

39R

L101

3V3_STBY

F113

2
2

0R

ANALOG_IF

SCL_TUN_DVB

R4

R140
56R

R142
1k

R3

R146
47R

RF_AGC
C141
220n
10V

C137
100n
10V

R143
1k2

C142
6

SIFM

1
2

C143
47u
16V

100n
10V
C124
10u
10V 3V3_VCC

R129
22k

SDA

R2

SIFP

SDA_TUN_DVB

D109
5V_TUN

SDA_TUNER
R137
100R
8
1
R1

R141
4k7
C144
100n
10V

5V_TUN

ANT_PWR

330R

1 IN1
OUT1 4
K9656M
2 IN2
OUT2 5
GND

BA782

R145
680R

C136
100n
10V

8
7

12V_VCC

C139
220n
10V

B1

47p
50V

F717

16V
22u
C125
F110

C123
Z101

10n
16V

R139
1k

1u

SCL
RF_AGC

IF_AGC_DVB

L103

B2
SDA

1u
C140

10

NC

N.C.

AS

R138
1k

DIGITAL_IF_P

R136
1k

IF_AGC

11

S714

SIF

C121

TU101 TDTC-G101D

DIF2

390nH
L102

DIF1

12

R127
6k8

DIGITAL_IF_N
AIF

R130
3k3

ANALOG_IF

LG

5V_TUN

5V_TUN

10u
10V

C128

OUT1

VDD

U706
IN1-

OUT2

TL062
IN1+

IN2-

VSS

IN2+

8
7

6
5

100p
50V
R793
82k

V+

R799
20k

C785
2

SC1_L_OUT
1u
16V

VESTEL PROJECT NAME : 17mb45-3

A3

SCH NAME :TUNER & PREPs

SHEET:1 OF:8

DRAWN BY :ULAS DERELI

3-27-2008_13:22

AX M

SW_C_IN

S203

15
1

C244
100n
10V
100n
10V
1

DVD_Y_IN

SW_Y_IN

20

RIN0P

RIN1P

LINE_IN_0R

1u
16V

AVDD_AU

62

BIN0M

LINE_IN_1L

BIN0P

LINE_IN_1R

GIN0M

AUCOM

64

LINE_IN_1L

1u
6V3

C782

22
23

65

R759
10k

LINE_OUT_3L

SOGIN0

LINE_OUT_3R

67

100n
10V

68

DSP_CH3_L

DSP_CH3_R

AVDD_33

R281
47R

31

2
1

Y0

47n
16V

2
1

Y0

32

C0

33
34

CVBS2

CVBS2

35

CVBS1

SILICON TUNER CVBS INPUT

36
75R
R772

R764
47R

C767
2
1

47R
R225

R226
470R

37
38
2

47n C230
40
C215

LINE_OUT_1R

VSYNC2

LED1

TX/SDA_DIG
TX/SDA_SC

72

RX/SCL_SC
RX/SCL_DIG

DSP_CH1_R

CVBS4

R237 16V
1k

CVBS0_OUT

41

CVBS1

42

47n
16V

N.C.

3V3_STBY

3V3_STBY

3V3_STBY

NVM_WP
3V3_STBY

SDA_NVM
3V3_STBY

R242
100R

3V3_STBY
2

C233

33n

R232
470R

R205
22k

1
2

10n
16V

100R
R216

C213
100n
10V

TP712

10n
16V

C208
100n
10V

KEYBOARD_STBY

VOL2

C214
100n
10V

R206
270R

F201
SC1_L_OUT

3V3_VCC

R244
100R

AVDD_AU

330R
2

C207
100n
10V

C209
100n
10V

F
DSP_CH3_R

VOL+

R217
47R

2
1

R245
100R

SC1_R_OUT

2
1

PSW202

C205
100n
10V

SW201

10n
16V
R807
22k

VESTEL PROJECT NAME : 17mb45-3

100n
10V

SAV_AUD_R_IN

1n
50V

RIN1P

C797

C202

SAV_AUD_L_IN

DSP_CH3_L

1u
16V
R203
10k

HP_R

P+

47n
16V

GPIOM[1]

33n
2

50V R241
22k

LINE_IN_1R

C201
2

R204
22k

R202
47R

R212
4k7

GPIOM[0]

200

C226

1n
50V
1

R240
22k

C229
1

VDDP

75R
R201

DSP_CH2_R

R811
100R

1n

VGA_R

HWRESET

201

GIN1P

SOGIN1

33n

C222
2

169

POWER_CTRL

C228

C231

C221
2

R218
4k7

HP_L

SC1_AUD_R_IN

LINE_IN_1L
1u
16V
R235
10k

R247
22k

75R
R224

R812
100R

1u
16V
R234
10k

1n
50V R239
22k

C225
BIN1P

47n
16V

DSP_CH2_L

C794

GPIOT[1]

157

VGA_G

168

SC1_AUD_L_IN

C227

47n
16V
R231
47R

C
VDDP_3

R808
22k

R273 VDDP
4k7

MAIN_R

33n
2

C224

C220
1

GND_8

167

C211
22u
16V

1u
16V
R233
10k

R243
100R

10n
16V

RIN0P

R238
22k

DSP_CH1_R

C223

1n
50V

PWM3

170

R230
47R

1k
R207

MAIN_L

C234

AUDIO INPUTs

GIN0P

PC RGB&YPbPr

4k7
R268

TP713

R223
75R

CVBSOUT0
GND_5

PWM2

166

CVBSOUT1

IRIN

165

STBY_ON/OFF_NOT
3V3_STBY
R209
3V3_STBY
4k7
SCL_NVM

VCOM0

INT

163

DVB_IRQ

Mono Opt.

LINE_IN_0R

VGA_B

DDCA_SCL

162

CVBS0

BIN0P

47n
16V

R267
100R

3V3_VCC

10n
16V

VCOM1

DDCA_SDA

161

CVBS1

DSP_CH1_L

C219
2

DDCR_SCL

160

7 R2 2
TP201
R1
8
1
TP202
100R
R803

3V3_STBY

C232

SC1_R

R229
47R

DDCR_SDA

159

6 R3 3

SAR3

C212

LINE_IN_0L
75R
R222

SOGIN0

47n
16V

75R
R221

SAR2

158

BACKLIGHT_DIM

154

5 R4 4

D201

SAR1

N.C.

AUDIO OUTPUTs

C218
2

4k7
R262
4k7
R264
4k7
R266

1N4148

R228
47R

4k7
R258
4k7
R260

SCL

47n
16V

SC1_G

R7
4k7

SAR0

CVBS2

S719

VDDC_2

153

DVD_IR_ON/OFF

C217
2

IR_IN

GND_7

152

CVBS3

C216
2

VDDP_1

151

3V3_STBY
DVD_SENSE

R246
22k

R779
47R

SC1_B

R778
47R

DSP_CH1_L

D
R227
47R

N.C.

U102
MST9WB6JS

1n
50V
75R
R220

PROTECT
3V3_STBY

5V_STBY

GPIOD[2]

76

155

SDA

16V
1

SCART RGB&CVBS
SC1_CVBS_IN

47n

CVBS0

CVBS0

47n
16V

R219
75R

VSYNC0

R256
4k7

3V3_STBY

DSP_CH2_R

71

4k7
R271

C247
1

TUNER_CVBS

LINE_OUT_1L

SC1_PIN8

BC858B

C238
16V
47n

SC1_FB

HSYNC0

70

75

VDDC

C240
2

SAV CVBS INPUT

75R
R278

30

LINE_OUT_2R

DSP_CH2_L

R280
47R

VGA_VSNC

AVDD_33_3

69

29

VGA_HSNC

LINE_OUT_2L

10n
16V

SW_Y_IN

C241

C239

R277
270R

SAV_CVBS

C0

39
100n
10V

R276
270R

RIN0P

GPIOD[1]

26

RIN1P

GPIOD[0]

77

R253
220R

25

GIN0P

BC858B
Q711
BC848B

73

4k7
R270 VDDP

3
XIN

74

R275
4k7

KEYBOARD_STBY

66

XOUT

44

SW_C_IN

16V
47n
2

R255
10k

3V3_STBY

Q203
Q202

R251
220R

R279
47R

24

SOGIN1

IDTV/DVD YC

VIDEO INPUTs

47n
16V

R758
10k

3V3_STBY

GIN1P

X201

LINE_IN_1R
C248

3V3_VCC

27p
50V

Q204
BC848B

LED1

47n
16V
C246

BIN1P

LINE_IN_0R

43

LED1

3V3_VCC

DVB_TXD

R210
47R
R211
47R

21

5V_SW

R274
4k7

3V3_STBY
Q201
BC848B

LINE_IN_0L

63

DVB_RXD

330R

LINE_IN_0L

61

27p
50V

5V_TUN

S204

GIN1P

C245

F718
1

AVDD_AU_2

C251

60

R254
10k

19

GIN0P

SOGIN1

C250

IR_IN

18

SOGIN0

5V_SW

AUVAG

R252
220R

FSA3157
B0

BIN1P

VCC

DVD/IDTV_SW

17

600R

C235

R250
220R

GND

59

U203

AUVRP

16

R249
10k

DVB_Y

B1

AUVRM

REFM

5V_STBY
F202

BIN0P

REFP

58

R272
47R

10V
10u C252

C237

SW204

S202

57

U102
MST9WB6JS

R215
2k7

GND_6

C243

100n
10V

AVDD_AU_1

REXT
VCLAMP

R213
10k

14.31818MHz
R269
1M

14
1

100n 10V
10V 10u

SW203

5V_SW

56

B0

11

R214
1k2

VCC

FSA3157

R286
390R

AVDD_33
C242

27p
50V

DVB_C

U202
GND

DVD/IDTV_SW

8
C236

R208
10k

LED

C249
CN201

B1

DVD_C_IN

R248
10k

S201

1u
6V3

AVDD_AU

2
C781

A3

SCH NAME :A/V INTERFACE

SHEET:2 OF:8

DRAWN BY :ULAS DERELI

4-28-2008_15:57

AX M

81

DVD_SPDIF

82

DVB_RESET

83

1u
6V3

SIF_CTL

R318
4k7

TP310
TP309
TP308
TP307

TP714

TP303

TP306

2
MDATA[0]

4 R4 5

MDATA[1]

3 R3 6

MDATA[2]

VDD_DMC

4
5

2 R2 7

MDATA[3]

R1
8
100R
R325

7
8

MDATA[4]

4 R4 5

MDATA[5]

VDD_DMC

10

3 R3 6

MDATA[6]

11

2 R2 7

MDATA[7]

12

R1
8
100R
R326

13
14

VDD_DMC
LDM

WEZ

CASZ

RASZ

R307
100R
R308
22R
R309
22R
R310
22R

15

16

17
18

19

BADR[0]

BADR[1]

R311
22R
R312
22R

20

21

22
MADR[0]

5 R4 4

MADR[1]

6 R3 3

MADR[2]
MADR[3]

23
24
25

7 R2 2
8

26

R1
1
100R
R306 VDD_DMC

27

VDD1

VSS3

DQ0

DQ15

VDDQ1

VSSQ4

DQ1

DQ14

DQ2

DQ13

VSSQ1

VDDQ4

DQ3

DQ12

DQ4

DQ11

VDDQ2

VSSQ3

DQ5

DQ10

DQ6

DQ9

VSSQ2

VDDQ3

DQ7

DQ8

VDD2

VSS2

DQML

NC2

WE#

DQMH

CAS#

CLK

RAS#

CKE

CS#

NC1

BA0

A11

BA1

A9

A10

A8

A0

A7

A1

A6

A2

A5

A3

A4
VSS1

VDD3

R323
100R

PANEL_ON/OFF

84

3V3_VCC

3V3_VCC

3V3_VCC

R319
4k7
R320
4k7
R321
4k7

85

BADR[1]

86

BADR[0]

87

U301
MT48LC4M16A2TG8E
VDD_DMC

RASZ

88

VDDC

89
90

54
91

VDDM

53
52
51
50

4 R4 5

MDATA[15]

3 R3 6

MDATA[14]

2 R2 7

49

VDD_DMC 1 R1 8
100R
R328

48

4 R4 5

45

3 R3 6

44

2 R2 7

43

VDD_DMC 1 R1 8
100R
R329

42

38
37

MCLK
R314
100R

36
35

94

MADR[10]

95

MADR[9]

96

MADR[8]

97

MADR[7]

98

MADR[6]

99

MADR[5]

100

MADR[4]

101

MADR[3]

102

MADR[2]

103

MADR[1]

104

MADR[0]

105

MDATA[10]
MDATA[9]
MDATA[8]

R315
100R
1
8
R1

33

4
1
2

30

29

28

R2
R3
R4
R1
R2
R3
R4
100R
R316

7
6
5
8
7
6
5

DQS0

AD[2]

AVDD_MI_4

AD[3]

MDATA[0]

WRZ

MDATA[1]

AVDD_AU
2

MADR[10]

MDATA[2]

BADR[1]

MDATA[3]

BADR[0]

AVDD_MI_5

RASZ

MDATA[4]

VDDC_3

MDATA[5]

GND_9

MDATA[6]
MDATA[7]
AVDD_MI_6

WEZ

MDATA[8]

WADR[11]

MDATA[9]

WADR[10]

GND_15

WADR[9]

MDATA[10]

WADR[8]

MDATA[11]

WADR[7]

AVDD_MI_7

WADR[6]

MDATA[12]

WADR[5]

MDATA[13]

WADR[4]

MDATA[14]

WADR[3]

MDATA[15]

WADR[2]

AVDD_MI_3

WADR[1]

DQS1

WADR[0]

DQM1

GND_17

MCLKZ

AVDD_MI_2

108

MADR[11]

GND_16

ALE

CASZ

107

MCLKE

RDZ

AVDD_MI_1

106
VDDM

34

31

MADR[11]

UDM

32

WEZ

93

MDATA[11]

40
39

92

MDATA[12]

41

R313
100R

CASZ

MDATA[13]

47
46

DQM0

AD[0]
AD[1]

R324
4k7

109

VDD_DMC

LDM

110
117

VDDM

112

MDATA[0]

113

MDATA[1]

MCLK

AVDD_MIPLL

MCLKE

C307
100n
10V

MVREF
SPI_SCK

MADR[9]
SPI_SDI
MADR[8]
SPI_SCZ
MADR[7]
SPI_SDO
MADR[6]
GND_13
MADR[5]
VDDC_4

114
115

MDATA[2]

116

MDATA[3]

122

VDDM

118

MDATA[4]

119

MDATA[5]

120

MDATA[6]

121

MDATA[7]

128

VDDM

123

MDATA[8]

124

MDATA[9]

125
126

MDATA[10]

127

MDATA[11]

133

VDDM

129

MDATA[12]

130

MDATA[13]

131

MDATA[14]

132

MDATA[15]

111

VDDM
R303
4k7

134

135

VDD_DMC

UDM

136
137

138

R301
100R

MCLK

MCLKE

139
146

147

148

149

R302
100R
1
R1
R2
R3
R4

D
SCK

SDI

SCZ

SDO

150
171

VDDC

100p
50V

8MB SDRAM
B

Q301
BC848B

SDI

C738

S301

BACKLIGHT_ON/OFF

3V3_STBY
NVM_WP
SCL_NVM
SDA_NVM

3V3_VCC
R322
4k7

8
VCC
7
WC
6
SCL
5
SDA

N.C.

79
80

N.C.

R317
4k7

100n
10V

SCK

R801
1k

HDMIA_5V

10u
10V

1
E0
2
E1
3
E2
4
VSS

8
VCC
7
HOLD#
6
SCLK
5
SI

C330
100n
10V

U303
24C32

1
1

3V3_STBY

CS#
2
SO
3
WP#
4
GND
TP711

R327
4k7

U302
MX25L512

330R

SCZ
SDO
3V3_STBY

C332

F308
1

3V3_VCC

8
U102
MST9WB6JS

DVB_SPDIF

C331

TP302
1

TP710

TP301

FLASH

C316

R802
2k2

TP305

N.C.

MADR[4]

E
1

C301

10u
10V

330R

F306
VDDM

F304

F301
3V3_STBY

VDD_DMC

60R
1

C321
220u
6V3

C323
100n
10V

C325
100n
10V

C328
100n
10V

3V3_VCC

VDDP

VDDM

60R

C304
100n
10V

10u
10V

DATA SIGNALS

C308

WARNING!!!DON'T USE VIA FOR MCLK AND

C309
100n
10V

C310
100n
10V

C312
100n
10V

C315
100n
10V

C317
100n
10V

C318
100n
10V

F302
1

10u
10V

330R

C302

1V26_STBY

VDDC
2

VDDC

C305
100n
10V

C311
100n
10V

C313
100n
10V

F303

C326
100n
10V

C327
100n
10V

3V3_STBY

C329
100n
10V

330R

10u
10V

C324
100n
10V

C303

AVDD_33

VESTEL PROJECT NAME : 17mb45-3

1

A3

SCH NAME :MEMORY INTERFACE

SHEET:3 OF:8

DRAWN BY :ULAS DERELI

4-28-2008_15:57

AX M

HDMI

U102
MST9WB6JS

CN404

10R
R422

R416
10R

10R
R425

R417
10R

HDMIA_1HDMIA_0+

10R
R423

R419
10R

HDMIA_C-

10R
R420

HDMIA_HPD

HDMIA_SCL
HDMIA_SDA

Q402
BC848B

HDMIA_5V
HDMIA_HPD

R410
1k

HDMIA_0+

4
5

HDMIA_1-

HDMIA_1+

HDMIA_2-

HDMIA_2+

9
10

27

AVDD_33

HDMIA_0-

R413
47k
R414
47k

28

10R
R424

HDMIA_C+

AVDD_33

R411
4k7

R418
10R

HDMIA_0HDMIA_C+

HDMIA_2HDMIA_1+

HDMIA_5V

HDMIA_5V

R415
10R

HDMIA_C-

HDMIA_2+

R409
1k

R421
10R

HDMI1

21
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

HDMIA_SDA

12

HDMIA_SCL
R412
910R

13

140

198

VDDP

C409

30

29

28

27

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

C410
100n
10V

26

S401

RX_A_3_P

RX_A_3_N

RX_A_CLK_P

RX_A_CLK_N

RX_A_2_P

RX_A_2_N

RX_A_1_P

RX_A_1_N

RX_A_0_P

RX_A_0_N

RX_B_3_P

RX_B_3_N

PANEL_VCC

PANEL_VCC

TP717

S407

TP736

TP730

TP718

TP726

TP728

TP722

TP724

TP720

TP732

TP733

TP721

TP725

S408

RX_B_CLK_P

RX_B_CLK_N

R762
4k7

213

AMP_MUTE

156

DVD/IDTV_SW

214
2

PANEL_VCC

RXA2N
RXA2P
HPLUGA
AVDD_33_2

DDCDA_SDA
DDCDA_SCL
USB2_REXT

GND_2
VDDP_5
GND_3
VDDP_6

C
VDDP_4
VDDC_1
RXBCKN
RXBCKP
RXB0N
RXB0P
AVDD_33_4
GND_10
RXB1N

RXB1P
GND_4
RXB2N
RXB2P
PM_CEC
HPLUGB
DDCDB_SDA
DDCDB_SCL

C401
100n
10V

C403
100n
10V

C406
100n
10V

C402
100n
10V

C404
100n
10V

C407
100n
10V

PANEL_VCC

R401
10k
2

S409

RX_A_0_N
R405
10k
2

RX_A_0_P

RX_A_1_N

RX_A_2_N

RX_A_1_P

RX_A_2_P

RX_A_CLK_N

GND_1

F
1

CN403

RXA1P

RX_A_CLK_P

CN402

RX_A_3_N

R805
10k

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

RXA1N

RX_A_3_P

PANEL_VCC

PANEL_VCC

PANEL_VCC

215

R402
10k
R806
10k

PANEL_VCC

R765
4k7

VESTEL PROJECT NAME : 17mb45-3

SINGLE LVDS OUTPUT SOCKET

2

AVDD_33_1

AVDD_33
1

10

13

21

22

23

11

S404

12

S403

24

25

26

27

28

14

RX_B_0_N

15

RX_B_0_P

197

16

RX_B_1_N

196

17

RX_B_1_P

195

18

RX_B_2_N

194

19

193

A
RXA0P

VDDP

RX_B_2_P

R404
10k

192

216

RX_B_CLK_N

20

RX_B_CLK_P

191

190

S406

RX_B_3_N

189

RX_B_3_P

S405

188

29

LVB0M

211

187

30

LVB0P

TP723

TP729

186

LVB1M

185

LVB1P

210

5V_VCC
VDDP

S402

LVB2M

209

RX_A_0_N

LVB2P

208

RX_A_0_P

LVBCKM

205

AVDD_33

3V3_STBY

LVBCKP

For 16:9 19LG N.C.

207

RX_A_1_N

LVB3M

204

212

R403
10k

LVB3P

RX_B_2_P

LVB4M

RX_A_1_P

184

TP727

LVB4P

RX_A_2_N

183

RX_B_2_N

GND_12

RX_A_2_P

180

182

RX_B_1_P

VDDP_2

RX_A_CLK_N

179

181

TP719

LVA0M

LVA0P

178

TP731

LVA1M

LVA1P

177

RX_A_CLK_P

RX_B_1_N

LVA2M

78

206

RX_A_3_N
RX_B_0_P

LVA2P

176

TP737

LVACKM

175

RX_A_3_P

RX_B_0_N

LVACKP

174

TP735

LVA3M

173
TP734

LVA3P

LVA4M

203

172
1

LVA4P

VDDC

VDDP

145

PANEL_VCC

202

164

VDDC

CN401

VDDC_5

VDDP

100n
10V

199

U102
MST9WB6JS

RXA0N

AVDD_USB
C405
142
USB20_DM
100n
10V
143
USB20_DP
144

DUAL LVDS OUTPUT SOCKET

1
RXACKP

141

AVDD_AU

RXACKN

A3

SCH NAME :HDMI&LVDS OUT

SHEET:4 OF:8

DRAWN BY :ULAS DERELI

4-28-2008_15:57

AX M

33p
50V

C557

33p
50V

33p
50V

C558

33p
50V

C553

R540
220R

Y/C Video
Outputs

10u
10V

C559

C550
100n
10V

C566
100n
10V

C563
100n
10V

C565
100n
10V

C567
100n
10V

UART0_TXD0

C515

100R
R502

C516
100n
10V

F507

UART0_RXD0
R505
2M2

3V3D_DVB

X501

22p
50V
2

1M
R541

RF_AGC

27MHz

100R
R538

3V3_SDRAM_DVB

27p
50V

TX/SDA_DIG
2

S711

330R
1

16V
22u
C529

3V3A_PLL_DVB
C535
100n
10V

F508
1

3V3_SDRAM_DVB

3V3A_ADC_DVB

330R
1

IF_AGC_DVB

C518
100n
10V

BC848

F503
1

3V3_SDRAM_DVB

3V3D_DVB

330R

DVD/IDTV_SW

RESET_DVB

33R
R510

C536
100n
10V

C539
100n
10V

3V3A_DVB

330R
C531
100n
10V

C537
100n
10V

C540
100n
10V

F505
1V8_VCC

1V8D_DVB

330R

C526

C530
100n
10V

F504
3V3_SDRAM_DVB

DVB_RESET

C525

DVB RESET

C524
100n
10V

10u
10V

Q501

10u
10V

2 2

10u
10V

BC847B
R507
4k7

C507
100n
10V

C506
100n
10V

C534
100n
10V

220n
10V

C522

10V

220n

C521

10k
R514

2
1

C523

10k
R513

3V3D_DVB

C509
3V3A_PLL_DVB
1n
50V* Layout Req.
1n
3V3A_ADC_DVB
50V

R509
1k2

R508
100R
SDA_TUN_DVB
SCL_TUN_DVB

R506
1k2

R503
100R

R501
100R
C510

16V
22u
C528

C532
100n
10V

C538
100n
10V

C541
100n
10V

22p
50V

TP716

10u
10V

DIGITAL_IF_N

C527

330R

C508
100n
10V

C546
100n
10V

1V8_VCC

CI_PWR
C533
100n
10V

VESTEL PROJECT NAME : 17mb45-3

3V3_VCC

10u
10V

330R

C564
100n
10V

F501

10u
C502
10V

<==
2

<==

TP502
TP501

C561
100n
10V

F506

330R
F502

MPEG DEC TS INPUT

3V3_SDRAM_DVB

5V_PNL

C501

10u
10V

C543

TP506
TP505

MPEG DEC TS OUTPUT

DIGITAL_IF_P

TP715
1

TP507
1

TP504
1

SF_DIO

C562
100n
10V

C549

SF_CLK

3V3_VCC

1n
50V

C548
100n
10V

330R

MDQM
MCLK_SDRAM
3V3_SDRAM_DVB
MA12
MA11
MA9
MA8
MA7
MA6
MA5
MA4

F509
1

1n
50V

MD10
MD9
3V3_SDRAM_DVB
MD8

MPEG_TS_IN_D7
MPEG_TS_IN_D6
MPEG_TS_IN_D5
MPEG_TS_IN_D4
MPEG_TS_IN_D3
MPEG_TS_IN_D2
MPEG_TS_IN_D1
MPEG_TS_IN_D0
MPEG_TS_IN_CLK
MPEG_TS_IN_VALID
MPEG_TS_IN_SYNC
MPEG_TS_OUT_D7
MPEG_TS_OUT_D6
MPEG_TS_OUT_D5
MPEG_TS_OUT_D4
MPEG_TS_OUT_D3
MPEG_TS_OUT_D2
MPEG_TS_OUT_D1
MPEG_TS_OUT_D0
MPEG_TS_OUT_CLK
MPEG_TS_OUT_VALID
MPEG_TS_OUT_SYNC

R518
10k

8
VCC
7
HOLD#
6
SCLK
5
SI

10V
100n
C542

RX/SCL_DIG

R516
10k

R515
10k

1
CS#
2
SO
3
WP#
4
GND

SF_DO

C545

CI DATA BUS

F SF_CS

C547
1

U501
MX25L512

3V3D_DVB

SERIAL FLASH

C505

MD14
MD13
3V3_SDRAM_DVB
MD12
MD11

1V8D_DVB

C511
100n
10V
10V
10u

C504
100n
10V

3V3D_DVB

C503
108
100n
107 10V
106
105
104
103
102
R532
101
5k6
100
USB_DIG_DP
99
USB_DIG_DM
98
97
96
95
94
93
R531
92
33R
RESET_DVB
91
DSU_TXD0
90
DSU_RXD0
89
88
87
86
85
84
83
82
81
80
R530
79
33R
1 R1 8
78
2 R2 7
77
3 R3 6
76
R529
4 R4 5
75
33R
74
1 R1 8
73
2 R2 7
72
3 R3 6
R528
71
4 R4 5
33R
1 R1 8
70
2 R2 7
69
3 R3 6
68
R527
4 R4 5
67
3V3D_DVB33R
1 R1 8
66
SF_DIO
2 R2 7
65
SF_DO
3
6
64
R3
SF_CLK
R526
63
33R 4 R4 5
SF_CS
1 R1 8
62
CI_D0
2 R2 7
61
CI_D1
3 R3 6
60
CI_D2
R525
4
5
59
R4
33R
CI_D3
1 R1 8
58
CI_D4
2 R2 7
57
CI_D5
3 R3 6
56
CI_D6
4 R4 5
55
CI_D7

MD15

3V3_SDRAM_DVB
C560
100n
10V

CI ADDRESS BUS

R524
33R
1
8
R1
2
7
R2
3
6
R3
4
5
R4

MPEG DECODER

ADC_VMID
VREFP
VREFN
VINN
VINP
USB_AVD18
USB_AVSS_2
USB_REF
USB_DP
USB_DN
USB_AVSS_1
USB_AVD33
OSCO1
OSCI1
GPA2/CS2#/TX1/VSYN/PCMCLK
GPA1/CS1#/RX1/HSYN/SD_CD#
RESET#
DSU0_TX/UART0_TX/GPD1
DSU0_RX/UART0_RX/GPD0
TSI_D7/PD7
TSI_D6/PD6
TSI_D5/PD5
TSI_D4/PD4
TSI_D3/PD3
TSI_D2/PD2
TSI_D1/PD1
TSI_D0/PD0
TSI_CLK/CLKO
TSI_VLD/VSYN
TSI_SYN/HSYN
GPD15/TSO_D7
GPD14/TSO_D6
GPD13/TSO_D5
GPD12/TSO_D4
GPD11/TSO_D3
GPD10/TSO_D2
GPD9/TSO_D1
GPD8/FUM/TSO_D0
GPD5/FUM/TSO_CLK
GPD7/FUM/TSO_VLD
GPD6/FUM/TSO_SYN
VDD33_2
SF_DIO/HA20/GPOD2
SF_DO/HA21/GPOD3
SF_CLK/HA22/GPOD4
SF_CS#/FCS#
HAD0/GPOE0
HAD1/GPOE1
HAD2/GPOE2
HAD3/GPOE3
HAD4/GPOE4
HAD5/GPOE5
HAD6/GPOE6
HAD7/GPOE7

R521
33R
1
8
R1
2
7
R2
3
6
R3
4
5
R4

R523
33R
1
8
R1
2
7
R2
3
6
R3
4
5
R4

C554
22u
16V

R520
33R
1
8
R1
2
7
R2
3
6
R3
4
5
R4

R522
33R

C551
100n
DVB_SPDIF 10V

R519
33R
1
8
R1
2
7
R2
3
6
R3
4
5
R4

R535
100R

VSS3
DQ15
VSSQ4
DQ14
DQ13
VDDQ4
DQ12
DQ11
VSSQ3
DQ10
DQ9
VDDQ3
DQ8
VSS2
NC2
DQMH
CLK
CKE
NC1
A11
A9
A8
A7
A6
A5
A4
VSS1

330R

3V3A_DVB

VDD1
DQ0
VDDQ1
DQ1
DQ2
VSSQ1
DQ3
DQ4
VDDQ2
DQ5
DQ6
VSSQ2
DQ7
VDD2
DQML
WE#
CAS#
RAS#
CS#
BA0
BA1
A10
A0
A1
A2
A3
VDD3

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

F510
1

3V3_VCC
R537
2k7

C517

R517
33R
1
8
R1
2
7
R2
3
6
R3
4
5
R4

==>

27p
50V

MCAS
MRAS
MBS0
MBS1
MA10
MA0
MA1
MA2
MA3
CI_A14
CI_A13
CI_A12
CI_A11
CI_A10
CI_A9
CI_A8
CI_A7
CI_A6
CI_A5
CI_A4
CI_A3
CI_A2
CI_A1
CI_A0

R551
33R
1
8
R1
2
7
R2
3
6
R3
4
5
R4
1V8D_DVB

AV1_Y
3V3A_DVB

N.C.

CHEERTEK
U503
CT216T-R

RAM ADDRESS BUS

10p
50V

R552
33R

AV2_C

R504
1k2

3V3D_DVB
R546
33R
1
8
R1
2
7
R2
3
6
R3
4
5
R4

MA12
MA11
MA9
MA8
MA7
MA6
MA5
MA4
MWE

MBS0
MBS1
MA10
MA0
MA1
MA2
MA3
3V3_SDRAM_DVB

N.C.

10u
10V

R554
150R

3V3A_DVB

DVB_C

N.C. N.C.

33R
R553

2u2

USB_ENABLE

C514

R545
33R
1
8
R1
2
7
R2
3
6
R3
4
5
R4

162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109

GPG0
AVSS_3
AVO3
AVD33_3
AVO2
AVSS_2
AVO1
AVD33_2
AVO0
AVSS_1
FSADJ
VREF
AVD33_1
AUDIO_DAC_VMID
AUDIO_DAC_L
AUDIO_DAC_R
GPC15/SPDIF
GPA0/CLKO/PCMACK
HAD8/PD0/GPOE8
HAD9/PD1/GPOE9
VDD18_2
HAD10/PD2/GPOE10
HAD11/PD3/GPOE11
HAD12/PD4/GPOE12
HAD13/PD5/GPOE13
HAD14/PD6/GPOE14
HAD15/PD7/GPOE15
HA19/VSYN/GPOF19
HA18/HSYN/GPOF18
GPA7/PWM3/PCMSD/SCXO
GPA6/PWM2/PCMWS/SCXI
GPA5/PWM1/PCMCLK/TX2
GPA4/PWM0/PCMACK/RX2
UART0_TX/GPOC0
UART0_RX
SAR_ADC_IN1
SAR_ADC_IN0
VDD33_3
VSS_2
OSCI
OSCO
GPC1/COFDM_ERR
GPA12/AGC_RF
GPA11/AGC_IF
GPA15/SDA
GPA14/SCL
AVSS_PLL_2
VLFQ
AVD33_PLL
VLFM
AVSS_PLL_1
VCCA
VSSA
VCCAX

R550
33R
1
8
R1
2
7
R2
3
6
R3
4
5
R4

MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MDQM
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MCLK
VDD33_1
VSS_1
MA12/GPOC11
MA11/GPOC10
MA9
MA8
MA7
MA6
MA5
MA4
MWE#
VDD18_1
CAS#
RAS#
BS0
BS1/GPOC12
MA10
MA0
MA1
MA2
MA3
HA14/GPOF14
HA13/GPOF13
HA12/GPOF12
HA11/GPOF11
HA10/GPOF10
HA9/GPOF9
HA8/GPOF8
HA7/PD7/GPOF7
HA6/PD6/GPOF6
HA5/PD5/GPOF5
HA4/PD4/GPOF4
HA3/PD3/GPOF3
HA2/PD2/GPOF2
HA1/PD1/GPOF1
HA0/PD0/GPOF0

C512
22u
16V

RAM DATA BUS

R544
33R
1
8
R1
2
7
R2
3
6
R3
4
5
R4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54

MD7
3V3_SDRAM_DVB
MDQM
MWE
MCAS
MRAS

L502
1

AV2_C

R549
33R
1
8
R1
2
7
R2
3
6
R3
4
5
R4

5V_VCC

C513
100n
10V

MPEG_TS_OUT_VALID

opt

22u

R536
4k7

R542
10k
1
1

R543
4k7
2

DSU_TXD0

3V3_VCC

C568

L708

3V3_VCC

MD3
MD4
3V3_SDRAM_DVB
MD5
MD6

N.C.

3V3A_DVB

N.C.

GPG1
GPG2
GPG3
GPG4/SD_PWE
GPG6/MS_INS
GPC13/SD/MMC_PWE
GPA10/SD/MMC_WP
GPB13/SD/MS_D1
GPB12/SD/MMC_DAT
GPC14/SD/MMC_CLK
GPB11/SD/MMC_CMD
GPB15/SD/MS_D3
GPB14/SD/MS_D2
GPC2/UART1_TX/SC0CLK
GPC3/UART1_RX/SC0DAT
GPC5/SC0PWR
GPC4/SC0RST
GPA3/SC0CD
GPC6/TX2/SC1CLK
GPC7/RX2/SC1DAT
GPC9/SC1PWR
GPC8/SC1RST
GPA13/SC1CD
VDD18_3
GPB7/IR
GPB5/DSPLYDAT
GPB6/DSPLYCLK
VDD33_4
GPB0/TX1/DSPLYCM0
GPB1/RX1/DSPLYCM1
GPB2/DSPLYCM2
GPB3/DSPLYCM3
GPB4/USB_DRVVBUS
GPB8/USB_DRVVBUS
GPB9/HSYN/KEYDET1
GPB10/VSYN/KEYDET2
HALE/GPOF20
HA17/CI1OE#/GPOF17
HA16/CI1IORD#/GPOF16
HA15/GPOF15
HWR#/CIWE#
HRD#/CI0OE#/GPOF21
HWAIT/GPF22
GPF26/CI1CD#
GPF24/CI0CD#
GPF27/CI1CE#
GPF25/CI0CE#
GPF30/CI0IORD#
GPF31/CIIOWR#
GPA9/CI1INT#
GPA8/CI0INT#
GPF23/CIREG
GPF29
GPF28

3V3D_DVB

N.C.

R548
4k7

MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MDQM
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MCLK_SDRAM

S501

N.C. N.C.
2

DVB_Y

2u2

163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216

10k
R763

R533
4k7

MPEG_TS_OUT_CLK

3V3_VCC

AV1_Y

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

3V3_SDRAM_DVB
MD0
3V3_SDRAM_DVB
MD1
MD2

L501

DSU_RXD0

TP519

SDRAM

opt

C519

TP514

8
U502
MT48LC4M16A2TG8E

22u

UART0_RXD0

TP518

7
L707

R512
10k
C520
100n
10V

DSU_TXD0

TP513

C552

TP517

USB_DIG_OCD

TP512
UART0_TXD0

1
8
R1
2
7
R2
3
6
R3
4
5
R4
R555 R556
33R
33R
1
8
R1
2
7
R2
3
6
R3
4
5
R4
R557
33R
8
1
R1
7
2
R2
6
3
R3
4
5
R4

FUM_EN

FUM_EN

TP516

5V_VCC

1V8D_DVB

TP511

MPEG_TS_OUT_SYNC

R558
4k7

3V3D_DVB
DVB_RXD
DVB_TXD

TP515

MPEG_TS_OUT_D0

CI_WE
CI_OE

TP709

CI_WAIT
CI_RST
CI_CD
CI_CE

CI_IORD
CI_IOWR
CI_IREQ
CI_REG

FUM Interface (bottoma 2.54X2.54 yerlestirilecek)

4
CI CONTROL SIGNALS

R539
220R

SIL_TUNER_RESET

DVB_IRQ

A3

SCH NAME :DVB MPEG DECODER & SDRAM

SHEET:5 OF:8

DRAWN BY :ULAS DERELI

4-28-2008_15:57

AX M

4
OUTA

U708

INAN
VDD

TDA1308T
OUTB

INAP
INBN

VSS
INBP

C799
2

C791
10u
10V
1

C790
10u
10V
1

C798
2

1
1

C801 100u
33p
16V
C792
50V
R813
47k
2

220n
10V
2

1N4148

D715
5V_VCC
2
3

C805
2n2
50V
22R
R6

HP_L

4
5

44
45
46
47
48
49

10
11
12
13
14
15

CI_OE
CI_A11
CI_A9
CI_A8
CI_A13
CI_A14
CI_WE
R605
4k7
CI_IREQ
CI_PWR
R607
3V3D_DVB
4k7

C803
2n2
50V

6
7

58
59
60
61
62
63
64
65
66
67
68

24
25
26
27
28
29
30
31
32
33
34

CI_A5
CI_A4
CI_A3
CI_A2
CI_A1
CI_A0
CI_D0
CI_D1

CI_D2

R4
R612
47R

MPEG_TS_IN_D2

MPEG_TS_IN_D1

MPEG_TS_IN_D0

IN

R3

GND
STMP2161
4
FAULT
EN

U603

R2

1n
50V

C618

C3

C2

C1

B3

B2

B1

A3

A2

A1

OUTP

SDB

INN

GNDB

VDD1

VDDA

OUTN

GNDA

INP

VDD_AUDIO

USB

MPEG_TS_IN_SYNC

R1

MPEG_TS_IN_VALID

10u
10V

C610

AMP_SHDN

CI_REG

D
MPEG_TS_IN_CLK

OUT

R611
33R

3V3D_DVB

MPEG_TS_OUT_D7
R609
150R
3V3D_DVB C601
15p
50V
CI_RST
CI_WAIT

R_AUDIO_P

57

R620
47k

56

R621
4k7

USB_DIG_OCD

23

IO3

22

F707
5V_VCC

IO2

MPEG_TS_OUT_D6

VDD

MPEG_TS_OUT_D5

GND

CI_A6

55
21

AZ099-04S

MPEG_TS_OUT_D4

IO4

CI_A7

54
20

U602

CI_A12

53
19

IO1

MPEG_TS_OUT_VALID

3V3D_DVB

CI_PWR

PT2333

52

MPEG_TS_OUT_D3

MPEG_TS_OUT_D2

MPEG_TS_OUT_D1

MPEG_TS_OUT_D0

MPEG_TS_OUT_SYNC

CI_IOWR

CI_IORD

3V3D_DVB

MPEG_TS_IN_D7

MPEG_TS_IN_D6

MPEG_TS_IN_D5

N.C.

18

51

43
9

CI_A10

R4
R603
33R

R3

33R

R618
10R

17

42
8

CI_CE

MPEG_TS_IN_D4

USB_DIG_DM
2

41
7

CI_D7

MPEG_TS_IN_D3

R624
15k

CN602

50

40
6

CI_D6

BC848B
Q601

R2

3V3D_DVB

100n
10V

C617

R617
10R

16

39
5

CI_D5

R602
47R
8
R1

HEADPHONE AMPLIFIER
1

AMP_SHDN
2

38
4

CI_D4

JK603
37

1
36

R5
22R
3

OUTP

SDB

INN

GNDB

VDD1

1n
50V

C3

C2

C1

B3

VDDA

L_AUDIO_N

2
2

3V3D_DVB

60R
C609

L_AUDIO_P

CI_D3

CI_CD

AMP_SHDN

R613
15k
2

35

R614
15k

100n
10V
1

R_AUDIO_N

B2

R_AUDIO_P

CN601

C607
10V
100n

USB_DIG_DP

C800
33p
50V
2

B1

C795
10n
16V

R615
10k
OUTN

VDD_AUDIO

C796
10n
16V

100n
10V

60R

R816
200k

VDD_AUDIO
C608

F709

R610
4k7

GNDA

U601

R814
47k
1

A3

BC848B
Q718
A2

R_AUDIO_N
2

L_AUDIO_P

100u
16V
F708

R608
4k7

60R

F
2

AMP_MUTE
1

C616
100n
10V
60R

C602
1n
50V

1
2

R606
4k7

1
2

L_AUDIO_N

PT2333
60R 10V
220u
C615

100n
10V

C793

5V_VCC

R604
4k7

220n
10V
F710

R809
100k

S1
R623
15k

C612

R810
100k

HP_R
C802
2n2
50V
2

INP

3V3_VCC

3V3_STBY

C
BC848B
Q719

R785
10k

R616
10k

A1

S2

1n
50V

C613

C603

R817
100R

R815
200k

VDD_AUDIO

U604

R619
100k

R818
100R

A
3

R601
4k7

C804
2n2
50V

MAIN_R

MAIN_L

1
8

F720
10V
220u
C783
VDD_AUDIO

USB INTERFACE
4

CN603

1N5819
D711
5V_VCC

USB_ENABLE

CI SOCKET

33R

E
E

MPEG_TS_OUT_CLK

VESTEL PROJECT NAME :17mb45-3

A3

SCH NAME :AUDIO AMP & CI & DIG.USB

SHEET:

DRAWN BY :ULAS DERELI

3-27-2008_13:22
6
8

OF:

AX M

DVD_IR

12V_VCC

R730
4k7

C721
10n
16V

F711

1
BS
2
IN
3
SW
4
GND

60R

C719
22u
16V

C718
22u
16V

C736
100n
10V

R789
100k

15

18

17

20

19

1
2

C735
STBY_ON/OFF

220p
50V

STBY_ON/OFF_NOT

220p
50V

14

13

C5V6

D707

1V8 DVB

1V26 & 3V3 STBY

U704
LM1117

F706
1

3V3_VCC

60R

IN

OUT

GND
1

TP705

1V8_VCC

VOUT
4

C724
100u
16V

9.1K

C712

17IPS16 CONNECTOR

GND2

F701
1

9
10

SW1

C709

5V_STBY
C706
10n
16V

F712
12V_VCC

60R
C705
22u
16V

C704
22u
16V

C737
100n
10V

U701
MP1583

1
BS
2
IN
3
SW
4
GND

STBY_ON/OFF_NOT

100n
10V

8
SS
7
EN
6
COMP
5
FB

C710
R707
10k

1
1

R711
3k9

D
2

5n6
50V

9.1K
0R

2u2

5V SYSTEM

60R

GND1

SW2

R703
100k

IN1

MP2109

L703

CN703

1V26_STBY

10u
10V

IN2

60R

19

FB2

U702

FB1

390k
R704

C703

5V_STBY

EN2

L701

F702

17

EN1

2u2

300K

15

R710
47R

330K

R723
180k

3V3_STBY

R702
82k

270K

5V_PNL

11

R708
15k

12

10

R4

DIMMING

Q707
BC848B

C716

R3

5V_PNL

R2

100u

12V_VCC

R756
4k7

6V3
C720

1
3

Q709
BC848B

R731
100R
8
R1

R804
10k

12V_VCC

20

BACKLIGHT_ON/OFF

18

TP704

1
2

R753
1k

R788
10k
1

BACKLIGHT_DIM
2

N.C.

C5V6

C5V6
D710
1

1
2

16

R741
4k7
R742
4k7
R743
4k7

R752
4k7

R721
56k

1
2

10u
10V

DIMMING

R725
100k

100u
6V3
D708

C729

CN702
1

3V3_VCC
C722C723
22u 22u
16V 16V

16

15u

R734
100R

13

14

C715
1

11

Q708
BC858B

220p
50V

12

10u
10V

C717

R755
4k7

10

5V_PNL

7
1

C728
47u
16V

DVD_IR
TP706
12V_VCC
TP707
5V_PNL
TP708
5V_STBY
R737
4k7

C733

SS33

27p
50V

12V_VCC

L704

D706
1

3V3_VCC
1

R735
3k9
R736
10k

S716

N.C.

R733
15k

DIMMING CIRCUIT

Q717
BC848B

5n6
50V

1
2

10V
100n
C734

D709

C15V

DVD_SPDIF
3

DVD_IR_ON/OFF

R786
10k

N.C.

CN701
2

R787
10k

DVD_SENSE

STBY_ON/OFF_NOT
C726

R1
75R

R744
1k

100n
10V

8
SS
7
EN
6
COMP
5
FB

DVD_Y_IN

3V3_VCC

R754
47k

R2
75R

R749
180R

3V3_VCC

3V3_VCC

2
1

U703
MP1583

IR_IN

C725
R729
4k7

R732
2k

DVD_C_IN

R748
180R

BC848B
Q710

R719
33k
R717
22k

F703
1

Q701
FDC642P

R706
4k7

R728
47R

3V3_STBY

R726
33k

R715
10k

C713

60R

5V_VCC

Q705
BC858B

470n
25V

PROTECT

60R
F705
12V_VCC

STBY_ON/OFF

R713
10k

R727
22k

Q703

PANEL_VCC
4

2
2

STBY_ON/OFF_NOT

R705
22k

R3
4k7

AMP_SHDN

5V_PNL

5V_VCC

F704

3V3_VCC

TP703

R716
10k

C707C708
22u 22u
16V 16V

PANEL SUPPLY SWITCH

60R

D704
BAW56

3V3_STBY

12V_VCC

3V3_VCC

15u

TP701

C5V6

2
1

SHORT CCT PROTECTION

SS33
D703
BAW56

L702

D701
1

5V_PNL

R709
33k

DUMMY SOCKET

16V
22u
C702

TP702

3V3_STBY
16V
22u
C714

D702

1V26_STBY

BC848B
1

Q702
BC848B

3
1

Q704

2 1

R712
10k

R714
10k

PANEL_ON/OFF

R4
10k

R724
10k
C701
100n
Q2
10V
BC848B
2

3
2

BC848B

S3

Q706
BC848B

VESTEL PROJECT NAME : 17mb45-3

A3

SCH NAME :POWER

SHEET:7 OF:8

DRAWN BY :ULAS DERELI

4-28-2008_15:57

AX M

5V_TUN
1

R781
680R
2

S713
DIGITAL_IF_N

X502 must be 32Mhz

1

R782
680R

BC858B

Q715

33p
50V

C765

33p
50V
C766

1V8_C

S715

1V8_D

X502
27MHz

5V_TUN

3V3_A

R775
33R
R776
33R

SCL_TUNER

SDA_TUNER

VDDC_7

DDI_1

25

26
VDDC_6

DDI_2

27

28
ADDRESS_SEL

29

GND_7

X2

30

31
X1

32
EXT_REF

33
VDDD_2

34
SCL

VI2C

39

1V8_C

SDA

36

3V3_A

TESTMODE
VDDD_1

24
1V8_D
1

GND_6

SIF

23

BC858B
R770
680R

Q712

22

5V_TUN

38

GND_8

RESET

R768
680R

37

SIL_TUNER_RESET

35

10V
100n
C772

C752

VDDA_6
GND_9

47

V_AGC

VDDC_3

VDDC_4

TUNER_CVBS

17

3V3_A

16

BC858B
R771
680R

Q713

R780
1k

15
14

3V3_A

13

1V8_C

IF_AGC_DVB
C749
100n
10V

12

VDDC_2

GND_4
11

VDDA_0
9

10

VDDA_2
8

GND_3

EXTCHO
6

IN_2

GND_2
5

VDDA_7

48

VDDA_3
GND_1

VDDC_10

18

5V_TUN

3V3_A

VIF

1V8_C

19

10n
16V

45

VDDA_4

1V8_C

SIF

R_EXT

46

GND_5

3V3_A

20

C771

VDDC_9

44

IN_1

3V3_A

U705
XC5000

VDDC_8

43

must be 4.99K

VDDC_5

VDDA_1

V_REF_P

21

1V8_C
R766
4k7

VDDA_5

R769
680R

1V8_C

42

V_REF_N

40
C751
100n
41
10V

C753
100n
10V
100n
10V

1V8_C

1V8_C

3V3_A

3V3_A

330R

F714

R784
680R

3V3_A

must be 820nH

S712

DIGITAL_IF_P
3V3_A

JK602

BC858B
R783
680R

Q714

C769

D714
BAV99

120p
50V

must be 390nH

5V_TUN

C770

must be 270nH

1u

L706

56p
50V
1u

56p
50V

L705

C754
100n
10V

C768

F713
3V3_VCC

3V3_A

330R

C741
100n
10V

C742
100n
10V

C743
100n
10V

C745
100n
10V

C748
100n
10V

E
F715
1V8_VCC

330R

C760
100n
10V

C758
100n
10V

C763
100n
10V

C764
100n
10V

C762
100n
10V

C757
100n
10V

1V8_C
C761
100n
10V

F716
1

1V8_D

330R

VESTEL PROJECT NAME : 17mb45-3

1

A3

SCH NAME :SILICON TUNER

SHEET:8 OF:8

DRAWN BY :ULAS DERELI

3-27-2008_13:22

AX M

C778

R793
C779
C780

R797

R623

C612
R624
U604

C617
R614

F710
F707

F708

L706

F714

L705

S719

R248

C608

F716

C743

C758

R812

R811

C136

C236

D101

C133

L101
C126
C139

C409
S713

S712

C225

C226

CN603

R319

C311

C805

Q104

R144

Q716

C754
C770

C211

R216

C213

R792

C787

R809
C800

R815

C724
C214

C772
R136

C520

R510
R512

C138
U707

R139

C803
C796

C801
C792

R816

U708

CN602

R813

R810

C804

R514

C522

U1

R506

R504

R531

S4

C504

R501

C511

C513

R508

R503

C505
C506

C503

R532

C508
C507

C521

R217

C547

C514

SW201

R206

F501

R603

C501

C519

R522

SW202

R208

U704

C548

C601

R609

R541

C530

R517
C541

SW203

R214

C212

D201
R207

C502

F502

R611

R525

C560

C517

X501

C515

U503

R551

R546

U502

C568

S711

C562

R545

C561

C554

C565

R553

R550

C563

L501
C552

R539

C537

L707

L502

L708

R778

R779

R533

F505

C526

C532

C536

R210

R211

C567

R2

R741

C738

S202

C558

R554
R535

C557

R540

C553

C538

C551

C540

C516

C531

C529

C509

C510

C512
Q501

R509

R513

C518

R507

C1

F306
F720
C720

U301

R138
R791
R536

R143

R621

U603

R275

R274

L102

C140

C404
C125

F111

C123

R420
C237

R781
X502

F713

C102

R783
C745

U705

R780

C741

R244

R799

TH1

JK604
SC101
F106

C535

F507

C528

C534

F508

C525

F504

F718

R748

R555

SW204

R215

R313
R213

Q704

D711

Q1

R273

R763

S501

R543

C542

R527

R526

R519

R523

C549

R542

R619

R790

F706

R516

R518

U501

R515

R524

R520

R505

R620

C610

C705

C704

R521

C550

R618

L103

C615

U602

R141

R137
C144

C134
R142

C326

R140

R710
R734

R711
C710
R707

C543

F509

C523

F510

C559

R537

R617

C142

F722

D702

JK603

C752

C141

C135

L702

U701

R709

C737

C709

R601
R604

F503

JK101

C753

C766

C137

R766

C765

F717

C708

C707

L704

F711

R538

R502

C802

TU101

C250

R328

C718

C719

C524

R552

C793

F108

R771

R133

C103

C757

C129

R235

F715

D110

R240

C760

R770

C143

C101

C249
R145

C252

C328

R241

R782

R784
C763

R768

R134

C251

C771

C207

F113

R306

R307

C764

F201

R321

S715

F109

R309

C762

R234
R239

C132
C209

R316

R329

R736

C564

C795

U601
F709

C128

R238

R315

R326

F308

C202

C234
R769

C545

R6

R205

R233

R320

R325

R733
R732

R608

R814

R800

D701

C749

R146

R528

R808

C231

C228

R324

C736

U703

C726

R706

R708

C794

R247

C232

C227

C318

Q702

CN601

R606

R317
R322

R557

R807

R119

F110

C315

C307

C722

C723

D707

C706

C546

C797

R204

C223

R612

C229

R245

R310

R776

C401

C313

C310
C224

R775

C248

R312

C748

R801
Q715

C127

C317

F712

R602

C761

R202

R311

R529

C742

Q712

C130

R712

R713

C321

C728

C539

R203

R231

R230
C769

R760
Q714

S714

C124

R327

C702

L701

R548

R607
R558
D709

R605

C527
C533

R556

R5

C798

C233
C122

R544

C791

F202
R246

C325

C751

D109

Z101

R308

C799

R117
C768

D104
Q713

C121

C324

R530

D714

C221
Z102

C316

C703

U702

F701

CN702

R549

D715

C222
R201

R130

R127

R314

R705

Q708

CN701

D708

C790

C201

R270

JK602

C220
R224

Q103

C785

C105
R232

C120

R223

C312

C309

C327

C603

R221

R220
C106

D102

R412

C405

R301

L703

C714

R704

R787
R789

F702

D706

C609

R228

R227
C107

CN404

C329

C613

C218

C217
D106

R122

C114

C241

C786

R269

R237

R323

R243

R222

C118

R128

C407

C216

C238
C247

C230

C767

U102

R818

D108

C323

R613

D105
R229

R131

R226

R281

C246

C245

R714

Q705

Q707

C717

R786

C716

R756

R753

C712

Q717

Q709

C566

C618

CN201

R303

C602

C219

D107

CN101

R121

R109

C607

R249
R219

R120

R424
C243

R764

R762

R242

R419

R414
C242

R272

R271

C402

R286

R278

R302

C215

R7

C721

S1

C115

R413

C330

R616

Q706

C701

Q703

R772

R3
R724

R256

Q718

R113
R225

S407

C725

S2

C113

C104

S406

R735

C109

X201

U302

C331

R129

R218

R258

R260

S3

C111

R803
C410

D704

C403

F304

Q719

R110

C308

C119

C208

R785

R421

Q710

C733

C715

R755

R742

C735

R752

R702

C783

R798

C302

R123

R410
R415

R716
R715

R267

F104

R417

R615

R425

Q601

C244

R4

R717

C235

R409
R416

S408

F302

R422

R262

R264

R743

R703

C616

R794
R423

R266

S401

C205

R268

Q2

R411

C305

R726

C713

D703

F301

C110

C406

R728

R727

F704

F703

R729

R105

CN703

S402

D103

C240

C239

Q701

F705

R610

R817

F721

R723

R725

C108

R761

R418

R403
R404

F303

F103

R212
R280

U303
R279

S405

R277

CN402

S404

R802

CN401

CN403

S403

R276

R805

R806

R405

S716

R730

R721

R804

R118

C3
Q402

R402

R401

S409

R737

C775

R114

C332

R788

R754

R106

R765

C304

C116

R254
R209

R115

F719

R124

C301

F105

C117

R719

F102

R125

R103

Q102

R102

R126

D710

R116

R255

C303

C774

R101

Q101

C729

C112

R104

R731

U202
S201

U706

R759

U101

Q202

R744

Q301

S204

S203
U203

R795

Q201

F506

C773

R758

R1

R796

Q711

R251

R250

R749

C784

Q204

R318

R252

C734

Q203

R253

S301

C781
C782