Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
second edition
Volnei A. Pedroni
6 5 4
3 2 1
Contents
Preface
xv
CIRCUIT-LEVEL VHDL
Introduction
1.1 About VHDL
1.2 VHDL Versions
1.3 Design Flow
1.4 EDA Tools
1.5 Translation of VHDL Code into a Circuit
1.6 Circuit Simulation
1.7 VHDL Syntax
1.8 Number and Character Representations in VHDL
3
3
3
5
5
6
7
8
8
Code
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
Structure
Fundamental VHDL Units
VHDL Libraries and Packages
Library/Package Declarations
ENTITY
ARCHITECTURE
GENERIC
Introductory VHDL Examples
Coding Guidelines
VHDL 2008
Exercises
11
11
11
13
14
16
17
18
24
27
28
Data
3.1
3.2
3.3
Types
Introduction
VHDL Objects
Data-Type Libraries and Packages
31
31
31
36
viii
Contents
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
Type Classications
Standard Data Types
Standard-Logic Data Types
Unsigned and Signed Data Types
Fixed- and Floating-Point Types
Predened Data Types Summary
User-Dened Scalar Types
User-Dened Array Types
Integer versus Enumerated Indexing
Array Slicing
Records
Subtypes
Specifying PORT Arrays
Qualied Types and Overloading
Type Conversion
Legal versus Illegal Assignments
ACCESS Types
FILE Types
VHDL 2008
Exercises
39
41
47
51
54
59
60
62
65
66
70
71
72
73
74
78
79
80
80
81
91
91
91
98
99
104
106
111
112
114
115
Concurrent Code
5.1
Introduction
5.2
Using Operators
5.3
The WHEN Statement
5.4
The SELECT Statement
5.5
The GENERATE Statement
5.6
Implementing Sequential Circuits with Concurrent Code
121
121
122
123
124
129
134
Contents
5.7
5.8
5.9
5.10
5.11
ix
135
140
143
143
144
Sequential Code
6.1
Introduction
6.2
Latches and Flip-ops
6.3
PROCESS
6.4
The IF Statement
6.5
The WAIT Statement
6.6
The LOOP Statement
6.7
The CASE Statement
6.8
CASE versus SELECT
6.9
Implementing Combinational Circuits with Sequential Code
6.10 VHDL 2008
6.11 Exercises
151
151
152
153
154
159
161
165
168
169
171
172
177
177
177
178
180
185
187
190
193
II
SYSTEM-LEVEL VHDL
199
201
201
201
203
208
211
213
216
218
219
Contents
221
221
221
223
230
233
233
237
238
10
241
241
243
245
248
251
253
257
258
261
261
262
264
267
271
III
275
11
277
277
279
289
291
292
298
312
312
313
12
319
319
322
Contents
12.3
12.4
12.5
12.6
12.7
12.8
xi
327
330
337
340
345
346
13
351
351
352
353
357
362
368
371
14
375
375
376
380
388
399
409
419
419
15
423
423
424
425
426
428
429
430
430
431
435
438
441
441
xii
Contents
16
445
445
446
448
449
450
451
452
464
464
17
467
467
468
470
472
479
490
491
APPENDICES
493
495
503
515
ModelSim Tutorial
525
537
545
Using Macrofunctions
547
551
555
563
Package std_logic_arith
577
Package std_logic_signed
583
585
Contents
xiii
589
593
Bibliography
Index
595
597