Chip Design Made Easy

what is our Design ow and EDA tools and methodology involved?

In this book Chip Design we tell how to build an integrated circuit (chip) by integrating billions of transistors to achieve an application. An Application could
be suiting a particular requirement like Microprocessor,Router,cell phone,etc. An Integrated circuit designed
for a specic application is called as ASIC(Application
Specic Integrated Circuits).

What is the estimated Chip Cost?

Above all the bottom line of any business model is
money. What is our Prot model? What is our estimated ROI(Return of investment)?

Todays ASIC Chips are pretty complex packed with

larger chunk of transistors targeted to a specic manufacturing process for fabricating the integrated circuits,
in a sub nanometer regime, involving many of challenges,
like knowledge of various protocols, architectures, models, formats, standards, knowledge about CMOS logic,
Digital Design concepts, taming the EDA tool for the
various design requirements like area, timing, power,
thermal, noise, routability, lithography aware, knowledge
about various variabilities like channel length, Vt, line
width variations, lens aberrations, IR drop eects, interdie, intra die-variations, eects, and various noise-eects
like Package noise, EMI noise, power grid noise,crosstalk noise, and ability to test and validate and know to
model and characterize all these eects upfront in the
design-phase,steps to increase yield to increase protability curve, with short span of time-to market to minimize
the risk and maximize the predictability and an modular
approach to Success. Now lets delve in to the Art of
Chip Designing

2 Analogy of Chip Design Architecture Vs Building Architecture.

Why an Analogy with Building Architecture? To understand the concepts of Chip designing in a better way, as
we are very familiar with Building Architecture, then it
will be easy for us to map Chip Design architecture.
VLSI(Very large scale Integration) ow was evolved similar to the ow involved in Building Construction. Now
let us delve in to the construction ow to better understand
the VLSI Chip design ow development.

When ever we start to construct a building, we will have

an architecture, how the building should look like , the
exterior looks and all, similar to that we will be designing
an architecture in the chip-design, based on the requireThat is a lot of technical jargon, but there is nothing to
ment of the product, what the product is addressed for
worry about. You will soon learn what that means, and
and whom to serve what needs, the so called specicaunderstand the concepts behind chip designing.
tion, will having the modules.

Now lets go in to the implementation part of both the

Building & Chip.

Before Designing a Chip? Need

to Brain Storm

We at rst come with the oorplan of the building, similarly we come with the oorplan of the Chip, Based on the
connectivity/accessibility/vaasthu we place our rooms,
What market is the Chip targeted for?
similarly we have the constraints to place the blocks. Like
we build the building with bricks, for Chip Design we
What are the Protocols involved in the Chip?
have libraries, which are like pre-designed bricks, for a
What is going to be our Processor/Bus Architec- specic functionality.
tures?
Now let us try to understand the power-structure or electrical connectivity in our Building. Initially we have an
what is the power/IR-drop/timing/Area/Yield/ tarElectrical plan for our building, where we have a requiregets and how to budget it in the Chip?
ment that all our electrical gadgets needs to get power.
What is the process in which the Chip going to be Similar to that we have a Chip power requirement, The
required power is supplied through the power-pads, over
manufactured?
a ring like topology to have a uniform distribution across
what are the various third party IPs/Memory re- all corners of the chip, and the supply has to reach all the
quirements?
standard-cells(bricks for Chip-Designing).,this is called
1

VLSI DESIGN FLOW

as power-grid topology in the Chip-Design, now the requirement is how well we design our Power-grid, to reduce the IR-drop so that our standard-cells get proper
power requirement.

connected together creating a scan-chain and test-input

values are passed from the scan-chain input of the chip
and expected data is visualized in the scan-chain output
of the chip, then the assumption is the chip is free from
I would not make justice, if I don't discuss about clock manufacturability issues like stuck-at faults(stuck-at one
and clock-tree in the Chip-Design ow. We have syn- or stuck at zeros).
chronous way of designing and asynchronous way of designing(dicult to verify). Majority of chips follow Synchronous way of coding, for which Static Timing Analy- 3 VLSI Design Flow
sis is possible. For the relevancy of the ops the clock to
those ops should reach at the same time from the crys- Step 1: Prepare a Requirement Specication
tal, with in some skew targets with in the chip.In order to
Step 2: Create a Micro-Architecture Document.
make this happen, a step called as clock-tree is performed
Step 3: RTL(Register Transfer Level) Design & Develafter power-grid is created.
opment of IPs(Intellectual Property)
Let us try to visualize the concept behind Place & Route
in Chip Design. We need to undergo lot of modelling Step 4: Functional verication all the IPs/Check whether
concepts, to understand the process of Chip-Designing. the RTL is free from Linting Errors/Analyze whether the
To have a better understanding of this concept of place RTL is Synthesis friendly.
and route, let us assume a society where people who are Step 4a: Perform Cycle-based verication(Functional) to
speaking dierent languages are living , and let us visu- verify the protocol behaviour of the RTL
alize that people talking of the same languages are living
in a community, then the communication is much eas- Step 4b: Perform Property Checking , to verify the RTL
ier , similar way in the chip-designing, the standard-cells implementation and the specication understanding is
who are having design relation-ships, are placed closer matching.
in the Placement ow this concept is called as regioning. Step 4c: Perform Clock Domain Crossing check, to verNow with in the regioning, of the groups of the standard- ify that proper synchronization of control/data is there to
cells, the cells which are really sharing data, has to placed ensure reliable cross domain data transfers.
close-by so that there timing is achieved and well optimized.This step is called placement, Connectivity across Some people use logical eort to estimating the latency
and hence the maxthe standard-cells is called as routing, the challenge is in the critical path of a CMOS circuit,
[1]
imum
possible
speed
of
the
circuit.
having optimized or reduced wire-lengths.
Now let us try to try to understand the concept behind Step 5: Prepare the Design Constraints le (clock denisignal integrity in the Chip-Design , often called us SI tions(frequency/uncertainty/jitter),I/O delay denitions,
Eect. As our process is shrinking day by day, and our Output pad load denition, Design False/Multicyclesilicon-realestate is costly, we try to accommodate more paths) to perform Synthesis, usually called as an SDC
and more standard-cells in the limited area, so the cells le(Synopsys constraint le, specic to Synopsys syntheare placed in very close proximity, so the switching of one sis Tool (Design Compiler))
can have an impact over the others behaviour, which can
make the path to be faster or slower, this issue is called as
signal-integrity. So similar way in our construction in order to maintain the integrity with in the house(neighbour
free-zone), within the limited zone of modurality, we try
to create fences, across buildings, similarly we can think
of a concept called as Shielding, the high frequency signal net with the power-nets running across. We perform
spacing across the buildings, similar way we can perform
spacing across the nets, which are in close proximities.

Step 6: To Perform Synthesis for the IP, the inputs to

the tool are (library le(for which synthesis needs to be
targeted for, which has the functional/timing information
available for the standard-cell library and the wire-load
models for the wires based on the fanout length of the
connectivity), RTL les and the Design Constraint les,
So that the Synthesis tool can perform the synthesis of
the RTL les and map and optimize to meet the designconstraints requirements. After performing synthesis, as
a part of the synthesis ow, need to build scan-chain conIn order to validate the silicon from the manufacturabil- nectivity based on the DFT(Design for Test) requirement,
ity issues, the concept in the Chip Designing is Design for the synthesis tool (Test-compiler), builds the scan-chain.
Test(DFT). One of the DFT techniques is scan-chain. To Step 7: Check whether the Design is meeting the requireunderstand the concept of the scan-chain, we can visual- ments (Functional/Timing/Area/Power/DFT) after synize that we have a front-door entry and a back-door exit, thesis.
and a person passes from the front-door and exits from the
Step 7a: Perform the Netlist-level Power Analysis, to
back-door exit of the building, that we are sure that there
know whether the design is meeting the power targets.
is no blocking within the rooms in the building, to make
that person stuck , similar to this analogy the ip-ops are Step 7b: Perform Gate-level Simulation with the Synthesized Netlist to check whether the design is meeting the

3
functional requirements.

not altered the functionality.

Step 7c: Perform Formal-verication between RTL vs Step 12d: Perform STA(Static Timing Analysis) with the
Synthesized Netlist to conrm that the synthesis Tool has SPEF le and routed netlist le, to check whether the Denot altered the functionality.
sign is meeting the timing-requirements.
Step 7d: Perform STA(Static Timing Analysis) with the
SDF(Standard Delay Format) le and synthesized netlist
le, to check whether the Design is meeting the timingrequirements.

Step 12e: Perform Scan-Tracing , in the DFT tool, to

check whether the scan-chain is built based on the DFT
requirement, Perform the Fault-coverage with the DFT
tool and Generate the ATPG test-vectors.

Step 7e: Perform Scan-Tracing , in the DFT(Design for Step 12f: Convert the ATPG test-vector to a tester unTest) tool, to check whether the scan-chain is built based derstandable format(WGL)
on the DFT requirement.
Step 12g: Perform DRC(Design Rule Check) verication
Step 8: Once the synthesis is performed the synthesized called as Physical-verication, to conrm that the design
netlist le(VHDL/Verilog format) and the SDC (con- is meeting the Fabrication requirements.
straints le) is passed as input les to the Placement and Step 12h: Perform LVS(Layout vs Schematic) check, a
Routing Tool to perform the back-end Activities.
part of the verication which takes a routed netlist conStep 9: The next step is oor-planning. Floor-planning
means placing the IPs based on the connectivity,placing
the memories, Create the pad ring (also called the pad
frame),[2][3][4][5] placing the Pads (Signal/power/transfercells(to switch voltage domains/Corner pads(proper accessibility for Package routing), meeting the SSN requirements (Simultaneous Switching Noise) that when
the high-speed bus is switching that it doesn't create any
noise related activities, creating an optimised oorplan,
where the design meets the utilization targets of the chip.

verts to spice (call it SPICE-R) and convert the Synthesized netlist(call it SPICE-S) and compare that the two
are matching.

Step 11: After performing Routing then the routed Verilog netlist, standard-cells LEF/DEF le is taken to the
Extraction tool (to extract the parasitics(RLC) values
of the chip in the SPEF format(Standard parasitics Exchange Format), and the SPEF le is generated.

power-drops with in the design and the IR-drop is with-in

the target limits.

Step 12i : Perform the ERC(Electrical Rule Checking)

check, to know that the design is meeting the ERC requirement.

Step 12j: Perform the ESD Check, so that the proper

back-to-back diodes are placed and proper guarding is
there in case if we have both analog and digital portions
in our Chip. We have separate Power and Grounds for
Step 9a : Release the oor-planned information to the both Digital and Analog Portions, to reduce the Substratepackage team, to perform the package feasibility analysis
noise.
for the pad-ring .
Step 12k: Perform separate STA(Static Timing AnalStep 9b: To the placement tool, rows are cut, blockages ysis) , to verify that the Signal-integrity of our Chip.
are created where the tool is prevented from placing the To perform this to the STA tool, the routed netlist and
cells, then the physical placement of the cells is performed SPEF le(parasitics including coupling capacitances valbased on the timing/area requirements.The power-grid is ues), are fed to the tool. This check is important as
built to meet the power-targets of the Chip .
the signal-integrity eect can cause cross-talk delay and
Step 10: The next step is to perform the Routing., at cross-talk noise eects, and hinder in the functionalrst the Global routing and Detailed routing, meeting the ity/timing aspects of the design.
DRC(Design Rule Check) requirement as per the fabriStep 12l: Perform IR Drop analysis, that the Power-grid
cation requirement.
is so robust enough to with-stand the static and dynamic

Step 13: Once the routed design is veried for the design constraints, then now the next step is chip-nishing
activities (like metal-slotting, placing de-coupling caps).

Step
12:
Check
whether
the
De- Step 14: Now the Chip Design is ready to go to the Fabsign
is
meeting
the
requirements rication unit, release les which the fab can understand,
(Functional/Timing/Area/Power/DFT/DRC/LVS/ERC/ESD/SI/IRGDS le.
Drop) after Placement and Routing step.
Step 15: After the GDS le is released , perform the
Step 12a: Perform the Routed Netlist-level Power AnalyLAPO check so that the database released to the fab is
sis, to know whether the design has met the power targets. correct.
Step 12b: Perform Gate-level Simulation with the routed Step 16: Perform the Package wire-bonding, which conNetlist to check whether the design is meeting the func- nects the chip to the Package.
tional requirement .
Step 12c: Perform Formal-verication between RTL vs
routed Netlist to conrm that the place & route Tool has

Deeper to Chip Architecture

This article assuming you are an Architect and What all

questions will come to your thought process before Architecting and making the Chip as a rst-pass success. Chip
Design is an Integration Challenge.

DEEPER TO CHIP ARCHITECTURE

What are the various Synchronous Mechanisms for

data-transfers
How many clock-domains required for the Chip
How many PLLs are required or single PLL sucient for all the clocks required

What is the targeted market for this Chip.

What is the thought process behind PADs Is

LVTTL/SSTL pads

What are the competitors to this Chip and Market

Requirement and ROI

Is the package going to wire-bond or Flip-chip

What is the Fabrication Unit the Chip is targeted

for?
What is the Success rate and Yield numbers
achieved in the Fabrication Unit
What is the technology Process targeted for

Methodology for Optimal Power-grid design

What are the noise reducing Mechanisms in case of
analog integration
Is there any requirement of speed monitors or process checking blocks

What is the correlation of the library models w.r.t.

Silicon

What is the type of fuses used laser fuse or euses

What are the various Protocols the Chip is going to

address

What are the mechanisms used to handle ESD

Hardware & Software Parti-tioning.

what is the reliability target of the Chip and how it

is addressed

What is the processor/micro-controller suitable for

this application.
What is the bus-architecture targeted

Is there any requirement of Fib Cells in the Design

What are the Mechanisms used for Yield improvement

Is the chip tested at at-speed test

What are the performance targets for this bus architecture

How much Memory-map is allocated for the IPs

What are the various Interfaces the Chip is having

What is the metric for spare-gates in the Chip for

ECOs

Is the design going to be in single Vt or with MultiVt design

Are repairable memories required

Is using Embedded macros right choice or Memory

Macros
What are the IPs are going to be Re-used
What are the IPs going to Hard-macros
What is the Verication Status and corner-case coverage of the I.Ps

What is the tester targeted and the requirement to

the Chip in terms of Scan-chain
Is test-vector compression mechanisms a requirement
What is the PLL(Phase Locked Loop) performance
in terms of Jitter

What is the Die-size targeted/Estimated for the Chip

What is the Interrupt handling mechanism within

the Chip.

What are the Power targets

What is the ROM-Code for the Chip.

Is Power Management Unit a requirement in the chip

to reduce Dynamic power

What are the Chip utilization targets

What are the mechanisms followed to reduce the

leakage power
Is Module enables/clock-gating a part of the
Methodology
Are resets going to synchronous or asynchronous

Will the chip be routable or any requirement for special libraries with dierent routing tracks.
What is the Methodology for tools and versions
What is the Version control mechanism planned for
data handling across multi Geographical Environments.

5
What are the sign-o criteria for the Chip
What are the frequency targets for the Chip.

6 Implementation Challenges and

Solutions

Is there room for further revisions of the Chip.

The metric for todays ASIC Design is on one side of

If the Chip has DDR/SDR interface is there any re- the coin is the maximum number of devices integrated,
quirement for DLL.
reduced die-size,optimal power,speed,thermal perfor What are the limitations of the Tools in mance, addressing signal integrity, addressing reliability,
terms
of
Complexity/run-times/turn-around enhanced yield techniques, reducing PLL jitters for
reliable functionality, testability,integration of analog
times/Computation Power requirements.
and digital in single SoC, Lithography friendly DRC,
What is the Mechanisms/Steps taken for the various Functionality met, high speed interfaces to memories,
Variability in the Chip IR drop/Power ground the IO fabric, IO buer analysis and selection, implenoise/inductance
eects/EMI
noise/Package mentation to validate the silicon, ability to in-corporate
noise/Crosstalk
noise/Simultaneous
Switch- last minute spec changes/functional & timing bugs
ing noise/Channel length variation/On chip Engineering Change Orders, Optimized package feasiVariation/Inter die variations/Intra die Process ble, development phases involving multi-geographical
variations.
multi-site, complex database handling, various models/abstractions/standards/formats/Protocols, advanced
process, library characterization modelling silicon, higher
5 Thought Process Involved in Bus- degree of EDA tools, design re-use standards, building
designs robust enough to deal with EMI noise/package
Architectures
noise/power-ground noise/cross-talk noise/substratenoise/clock-jitter/process uncertainties/IR-drop/On-chip
what are various parameters to be looked in to for an op- variation and on other side of the coin, how to address all
timal System bus architecture in an SoC, in order to have these issues right from the design stage is the challenge
maximum performance possible.
of todays Chip Design Industry.
System speed is not only dependent on the This tight bonding of integration across the doProcessor/Micro-controller but also on the Bus mains/abstractions/tools/designers/process/protocols/standards/design
re-use/decision in optimal trade-os/design knowspeed the system operates.
hows/cross-culture design community needs a modular
Contention Prevention mechanisms across multiple uniform approach , to bring rst pass silicon success.
drivers.
Now lets deal with the Implementation challenges and
Bus Splitters: Hierarchical Bus structures, based steps to achieve it in the design-phase.
on the speed targets {for example the AMBA bus Complex Database Handling/Multi-site Design & Develfrom ARM, has two bus hierarchy levels : Advanced opment As now the designs are development in multiHigh Performance Bus[AHB] & Advanced Periph- site environment, as each site has some domain expertise
eral Bus[APB]. Split bus architectures has energy and to use to the fullest it needs multi-site design and deecient transactions and concurrent data transac- velopment stages, in order to maintain the database hantions over the conventional buses.
dling a proper version control management System (e.g.,
Reducing latency and crossbar utilization mecha- clearcase) is required to proper align the database , tag it
with labels to know the database and nally after designnisms.
ing go through with proper reviews and checklist process
Optimum Bridging Mechanisms for cross data to assure the quality of the delivery.
Transfers among the Buses.
Designing an Optimal Padring Steps involved in design Performance Enhancers by having Pipeline mecha- ing an optimal padring
nisms and steps to prevent Stalling.
Make sure you have corner-pads, across all the corners of
Arbitration Protocol schemes for shared buses the padring This is mainly to have the power-continuity as
{Fixed Priority Schemes, Round Robin Scheme, * well as the resistance is less Ensure that the Padring fullls
Time Division Multiplexing Schemes}.
the ESD requirement, Identify the power-domains,split
the domains, Ensure common ground across all the do Mechanisms to reduce bus waiting time.
mains. Ensure that the design has sucient core power Synchronization mechanisms across the bus
pads. Choose the Drive-strength of the pads based on the
current requirements, timing. Ensure that there is sepa Scheduling based on power-proling.
rate analog ground and power pads. A No-Connection
Trac based Dynamic Voltage and frequency scal- Pad is used to ll out the pad-frame if there is no requireing techniques for meeting power-targets.
ment for I/Os.Extra VDD/GND pads also could be used.

6 IMPLEMENTATION CHALLENGES AND SOLUTIONS

Ensure that no Input/output pads are used with unconnected inputs, they consume power if the inputs oat. Ensure that oscillator-pads are used for clock inputs. In-case
if the design requirement for source synchronous circuits
make sure that the clock and data pads are of same drivestrength. Breaker-pads are used to break the power-ring,
and to isolate the power-structure Ensure that the metalwire connected to the pin can carry sucient amount of
the current, check if more than one metal-layer is necessary to carry the maximum current provided at the pin.
Ensure that few pad-ller cells are placed near the corner pads to ease the substrate routing requirements. In
case of source synchronous pads, like clock and data going out, Ensure that these pads are on the centre, as the
leads at the center of the package is short compared to the
leads on the corners of the package, which can reduce the
impact of EMI.

optimal clock-gating cells, in the design and controlling

them by the module enables gives a lot of power-savings.
As clock-trees always switch making sure that most number of clock-buers are after the clock-gating cells, this
reduces the switching there by power-reduction. Incorporating Dynamic Voltage & Frequency scaling (DVFS)
concepts based on the application , there by reducing the
systems voltage and frequency numbers when the application does not require to meet the performance targets.
Ensure the design with IR-Drop analysis and groundbounce analysis, is with-in the design specication requirement. Place power-switches, so that the leakage
power can be reduced.

Designing for Optimized Area As silicon real-estate is

very costly and saving is directly proportional to the companys revenue generation lot of emphasize is to design
which has optimal utilization in the area-front. The steps
to reduce area are

Using logic restructuring for the areas to be timing

met, Use the useful skew , if permissible by meeting
the hold-time requirements. Use register retiming/timeborrowing concepts to meet the design timing requirements Use faster ip-ops for the timing-paths which are
timing hungry. Use Low-Vt cells for the paths to meet
the timing. Ensuring the design meets the frequency targets by performing STA, across all the functional and
test modes , across all the corners, including the derating
factors. Make sure that there exists common clock-tree
paths and bifurcation happens only at the last-stage, so
that the common clock-path can be removed in the delay
calculation as over-head in the pessimism removal during
de-rating. Incorporate programmable DLL(Delay locked
loop) based design, for memory-controller designs, which
involves round-trip delays.

If the path is not timing-critical, then optimize the cells to

use the low-drive strength cells so that there will saving
in the area. Abut the VDD rows Analyzing the utilization numbers with multiple oor-planning versions which
brings up with optimized area targets.
Designing an Optimized oorplan Study the data-ow
graph of the design and place the blocks accordingly, to
reducing the weighted sum of area, wire-length. Minimize the usage of blocks other-than square shapes,
having notches Place the blocks based on accessibility/connectivity, thereby reducing wire-length. Abut the
memory, if the pins are one-sided, there-by area could
be reduced. If the memory communicates to the outside world more frequently, then placing at the boundary
makes much of a sense. Study the number of pins to be
routed, with the minimum metal width allowed, estimate
the routability issues. Study the architecture and application , so that the blocks which will be enabled should be
scattered, to reduce the power-ground noise.
Designing for Achieving Power-targets As Todays IC design power plays a major-role in the design win, achieving
power-targets are the major concern. Some of the design
best-practices are Design with Multi-VDD designs, Areas
which requires high performance, goes with high VDD
and areas which needs low-performance are working with
low Vdds, by creating Voltage-islands and making sure
that appropriate level-shifters are placed in the crossvoltage domains Designing with Multi-Vts(threshold
voltages), areas which require high performance, goes
with low Vt, but takes lot of leakage current, and areas
which require low performance with high Vt cells, which
has low leakage numbers, by incorporating this design
process, we can reduce the leakage power. As in the
design, clocks consume more amount of power, placing

Designing for Achieving Frequency targets. As ASIC designs are today rated by the clock frequency the design can
achieve, brings with lot of performance within. The few
design strategies to achieve the frequency targets.

Designing for Meeting Signal-integrity targets As more

and more devices are getting packed, results in more congested areas, and coupling capactiances dominating the
wire-capacitance, creates SI violations. Lets see now by
what are all the measures we can reduce/solve it.
As clock-tree runs across the whole chip, optimizing the
design for SI, is essential route the clock with doublepitch and triple spacing. In-case of SI violation, spacing
the signal nets reduces cross-talk impacts. Shield the nets
with power-nets for high frequency signal nets to prevent
from SI. Enable SI aware routing , so that the tool takes
care for SI Ensure SI enabled STA runs, and guarantee
the design meeting the SI requirements Route signals on
dierent layers orthogonal to each other Minimize the
parallel run-length wires, by inserting buers.
Designing for Better Yield(DFY/DFM) Better yield
could be achieved by reducing the possibility of manufacturability aws. Guaranteeing the circuit performance, by
reducing parametric yield, with process variations playing
a major role is a big-challenge.
Create more powerful stringent runset les with pessimistic spacing/short rules. Check for the areas where
the design is prone to lithographic issues, like sharp cuts

7
and try to re-route it. For via-reliability issues, use redundant vias, to reduce the chances for via-breakage. In order
to design for yield-enhancement , design systems, which
could have optimal redundancy, like repairable memories. Optimal placing of decoupling capacitances, reduces the power-surges. Doubling the width of the noncritical nets, clock-nets can increase the yield parameter.
Ensure that the poly-orientation are maintained.
Designing for Optimal integration of Analog and Digital
As todays IC has analog components also inbuilt , some
design practices are required for optimal integration. Ensure in the oorplanning stage that the analog block and
the digital block are not siting close-by, to reduce the
noise. Ensure that there exists separate ground for digital
and analog ground to reduce the noise. Place appropriate guard-rings around the analog-macros. Incorporating
in-built DAC-ADC converters, allows us to test the analog portion using digital testers in an analog loop-back
fashion. Perform techniques like clock-dithering for the
digital portion.

Verication Static Timing Analysis Physical Verication

Power Simulation Thermal Simulation Noise Simulation
Test Simulation Emulation Hardware prototype Hardware Software co-simulation Transistor level Simulation
Now lets Venture in to each area and insure it
Functional Verication:
TLM(Transaction Level Modeling) Linting RTL Simulation (Environment involving : stimulus generators, monitors, response checkers, transactors) Gate level Simulation Mixed-signal simulations Regression How Much Did
I cover in the functional part - What is my Coverage Metric? and what are the methodologies used?
Is the verication tests covered pin-pointed tests or tests
with random seeds to cover all the corner-cases. Codecoverage Line coverage Functional coverage
Formal Verication:

Equivalence checkers RTL versus Gate Pre-layout versus post-layout Net list Assertion based property checkers(Mathematical techniques to allow larger state space
Designing for Engineering Change Order As more and coverage)
more complex the IC design is , and with lot of rst time
application , is more prone to last minute changes, there Timing Verication:
should be provision in the design-ow to accommodate With whom the Chip is talking to (To know the Interface
the functional and timing bugs. The step to perform this Timings) What is the Timing-budgets with in the chip,
called as Engineering change order(ECO).
and how to constrain it within each I.P. and nally anaEnsure that the design has spare functional gates well lyzing and signing for Timing-targets How to address the
distributed across the layout. Ensure that the selection timing targets with varying process parameters(on-chip
the spare gates, has many avours of gates and universal variation) what is the optimal de-rating number to be set
so that variations are addressed. Steps to minimize the
gates, so that any functionality could be achieved.
clock-jitter.
Designing an Lithography friendly Design Designing for
Manufacturability requires validating the design full- Physical Verication:
lling lithography rules
Is my design manufacturing process friendly ?
Checking the layout conrming the design rules DRC (Design Rule Check) LVS Antenna Checks ERC
(spacing,trace-width,shorts).
Check for the less- ESD checks
congested areas and increasing the spacing of the
Noise Simulation:
nets.
How Noisy is my design so need to perform noise simulations addressing these areas

Chip Verication methodologies

-"Anything that can go wrong - Will"-Murphy

What is my next step to be performed?
Now Lets start with an assumption that anything may go
wrong
What are the various areas can things go wrong?
List down the areas in the ow that things can go wrong
and derive a methodology to verify at each and every
stage. List down all your uncertainties that could potentially happen and how to model it and how to constrain
and verify up-front. Explore and re-visit each and every
area in the Design ow to cover potential risk
Functional Verication (RT L level , Gate level) Formal

Simultaneous Switching Noise (SSN) Package Noise

EMI Noise Power-ground noise Cross-talk noise Analog
Noise Substrate noise Power Simulations:
When a digital logic gate switches, it pulls a surge of current through the power and ground pins connected to it.
The inductance of those pins (and their bond wires) converts that surge to an internal drop in supply voltage and
rise in ground voltage on-chip (relative to a PCB ground
plane). Those voltage uctuations may not be enough to
interfere with digital logic, but they can seriously interfere
with the performance of analog circuits. There are several tricks to reduce the electromagnetic interference
(EMI) of these surges.[6]
An independent set of I/O power supply pins that
is only connected to the output drivers on the I/O

EXTERNAL LINKS

pads, separate from the core power supply pins

that power internal digital logic. This helps prevent
switching noise in a processor core from leaking out
through the output pins, radiating o PCB traces
like an antenna, and interfering with radio and television (and failing FCC testing).

There are also more subtle problems, such as thermal gradients causing nonlinearity in analog chips. Computer
simulations often leave out such subtle eects, creating
a simulations never fail problem when the actual chip
performs much worse than the simulations. Mask Designers carefully lay out ampliers, placing critical components with symmetry and common-centroid layouts, in
An independent set of analog power supply pins order to reject thermal gradients.[7]
that power the on-chip analog components (ADC,
DAC, etc.) and analog output pads, separate from Test Simulations
the digital power supply pins. This helps prevent Is my design testable once chip comes out, methodologies
switching noise in a processor core from interfering to identify the problematic areas
with the analog components.
Boundary Scan Memory BIST simulations Tester speI/O bus pins (address and data) that only toggle on cic vector generation and simulations Tester vector comI/O bus cycles, independent from memory bus pins. pression techniques to reduce tester time At-speed testA single common bus for all external memory and ing mechanisms Scan-shift and scan-capture methodoloI/O devices forces each memory access to toggle ad- gies IDDQ testing Wafer Level Burn-in Tests to know
dress and data lines all over the PCB connected to Known Good Dies(KGD) Wire pull tests DC parameter tests AC parameter tests Path-delay tests Delay tests
every I/O device, radiating much more noise.
Transition fault testing
spread spectrum clock
Addressing DSM and Yield Issues
internal clock doubler or more general clock PLL - Redundant vias Spacing non critical areas to be lithogra- this allows internal processor core to run at a high phy friendly Wire widening Metal Filling Metal Slotting
clock rate, without that high frequency being directly
Emulation:
connected to any PCB traces.
Emulates the functional behavior of the design. SynthePut some internal memory on-chip; clock only intersizable assertions are mapped to emulators to perform at
nal memory (cache RAM or ash memory) at high
system speeds.
speeds; use a slower pace to read and write external
Hardware prototype:
memory devices.

Drive output pins with slower rise and fall times

to reduce radiated EMI (even though the pins still
have the same number of transitions/second); tolerate slower rise and fall times on input pins.

Prototyping the system requirements in a programmable

FPGAs
In spite of all the Verication Methodologies and Strategies if things goes wrong, how to address that in the design
- Methodologies to reduce cost & time

Prefer dierential communication buses -FireWire, USB, XDR DRAM, low-voltage dier- Spare-gates Redundant rows/columns in the memories
ential signaling, etc. -- rather than inherently noisier Redundant vias Built-in self repair memories Focused
single-ended buses -- RS-232, IEEE 1284, the ISA Ion Beam Methodologies
bus, etc.
Is my design meeting power-targets
IR drop analysis Dynamic power simulations
Power related methodologies
Optimum location for De-caps Multiple Voltage domains
Multi Vt design DVFS (Dynamic Voltage and Frequency
scaling) Clock-gating Techniques Power Management
Unit (to shut-o when not required) Level-Shifters across
cross-voltage domains
Thermal Simulations
Study the thermal targets and mechanism to reduce thermal problems.
The largest and most obvious thermal problem is permanent failure caused by overheating. One way to avoid that
is ...

8 Internal Links
Programmable Logic
Microprocessor Design
Nanotechnology/Nanoelectronics
Semiconductors

9 External Links
[1] Bit permutation instructions: architecture, implementation, and cryptographic properties": Chapter 4: Hardware
Implementation by Zhijie Jerry Shi 2004
[2] ARM Limited. IO pad ring design. 2007.

[3] EDA board. Analog IC Design and Layout: why do we

need pad rings?". 2010.
[4] Erik Brunvand. Pads and Pad Rings. quote: A chip
consists of a core and a pad ring. Core is the guts. Pad
ring (or pad frame) connects the guts to the outside world.
[5] Dan Clein. CMOS IC Layout: Concepts, Methodologies, and Tools. 1999. Section 5.3 Pad cells, starting
on p. 114.
[6] Killing the EMI Demon by Norman Rogers 2002
[7] National Semiconductor: AN-1485 The Eect of Heavy
Loads on the Accuracy and Linearity of Operational Amplier Circuits (or, Whats All this Output Impedance
Stu, Anyhow?" by Bob Pease 2008

All about VLSI design

Knowledge and Concept of Chip Designing - http:
//vlsichipdesign.com/
VLSI: designing electronic chips
Digital VLSI Wiki
Learn how to suppress the noise coupling in integrated circuits
Practical Electronics/PCB Layout describes some
issues that eect both chip designers and PCB designers, such as EMI
Wikiversity: Very Large Scale Integration
Wikiversity: Electric VLSI Design System
Wikiversity: DNA integrated circuit
Wikiversity: Nanomedicine#BIOSENSOR_CHIPS
Wikiversity: MEMS design

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