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Project Objectives:
The objective of this project is to design 8-bit signed number digital
multiplier using Booth Multiplier Algorithm in VHDL.
Introduction:
In this report, we will write about the project planning: first of all, we
include the project scope and then Gantt chart that illustrates the schedule
of this project. Then, we present an overview of booth multiplier and its
algorithm in VHDL.
Next, we include the overall design of 8-bit booth multiplier project including
block diagram, step by step operation flow chart, list of inputs and outputs
signal.
1. Gantt chart
Table 1: Gant chart of project planning
Week
Week 10
Week 11
Week 12
Week 13
Week 14
Task
Project planning
Overview of
booth multiplier
Flow chart of project
Overall
design
block
diagram
Booth Multiplier
VHDL design
Booth Multiplier
VHDL Testbench
Functional Simulation
LCD driver design
Testing on FPGA board
Displaying result on LCD
(X * Y)= C
1
2. Project Scope
The input will be in 8 bits multiply by 8 bits which will produce 16 bits of
accurate multiplied answer.
The input and output of the system will only process and produce fixed point
value.
The system also accepts negative value which is called signed number.
VHDL (Very high speed integrated circuit Hardware Description Language) is
used as the language for the system.
All the process will be running using Quartus II 9.1 sp2 Web Edition then
implement it on Altera DE1 FPGA board to display the multiplication result.
Start
Project
Introduction
Booth Algorithm
VHDL
Design VHDL
Booth multiplier
VHDL
LCD Driver
design
NO
Yes
Display results on
LCD
End
4.
that
can
operate
as
multiplier
operation
that
would
be
Table 2 show that the Booth Multiplier Algorithm Rules, that is very
important for this project. The algorithm rules give a procedure for
multiplying binary integers in signed 2s complement representation.
Table 2: Booth Multiplier Algorithm Rules
Xi
0
0
1
1
Xi-1
0
1
0
1
OPERATION
SHIFT ONLY
ADD (Y) & SHIFT
ADD (-Y )& SHIFT
SHIFT ONLY
The table above shows the rules of booth Multiplier where X and Y
are 8-bits inputs to be multiplied. [1]
Start
Input
Identify
Operation
N
Ye
s
O
i + 1,
0 i 7
Xi =
Xi-1=1
Shift
Xi =
O Xi-1=0
Add -Y
then Shift
Xi = 1
Xi-1=0
Add Y
then Shift
5
Output
END
Y(0-7)
Data Path Unit
Shifter
X(0-7)
Control
Unit
Adder
Negative
Output(0-15)
9. References
1. Meyer-Baese, U. and U. Meyer-Baese, Digital signal processing with field
programmable gate arrays. Vol. 65. 2007: Springer.
2. Akanksha Sharma, Akriti Srivastava, Anchal Agarwal, Divya Rana and Sonali
Bansal, Design and Implementation of Booth Multiplier and Its Application Using
VHD,IJSET, vol. 3 Issue No.5, pp : 561-563, 1 May 2014.
3. Brown, S.D. and Z.G. Vranesic, Fundamentals of digital logic with VHDL design.
Vol. 70125910. 2000: McGraw-Hill New York.