RC Phys

Design with RTL Compiler Physical
Product Version 10.1

August 2011
2007-2011 Cadence Design Systems, Inc. All rights reserved.

Used by permission. Printed in the United States of America.
Cadence Design Systems, Inc. (Cadence), 2655 Seely Ave., San Jose, CA 95134, USA.
Open SystemC, Open SystemC Initiative, OSCI, SystemC, and SystemC Initiative are trademarks or
registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and are
used with permission.
Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. contained in this document
are attributed to Cadence with the appropriate symbol. For queries regarding Cadences trademarks,
contact the corporate legal department at the address shown above or call 800.862.4522. All other
trademarks are the property of their respective holders.
Restricted Permission: This publication is protected by copyright law and international treaties and
contains trade secrets and proprietary information owned by Cadence. Unauthorized reproduction or
distribution of this publication, or any portion of it, may result in civil and criminal penalties. Except as
specified in this permission statement, this publication may not be copied, reproduced, modified, published,
uploaded, posted, transmitted, or distributed in any way, without prior written permission from Cadence.
Unless otherwise agreed to by Cadence in writing, this statement grants Cadence customers permission to
print one (1) hard copy of this publication subject to the following conditions:
1. The publication may be used only in accordance with a written agreement between Cadence and its
customer.
2. The publication may not be modified in any way.
3. Any authorized copy of the publication or portion thereof must include all original copyright,
trademark, and other proprietary notices and this permission statement.
4. The information contained in this document cannot be used in the development of like products or
software, whether for internal or external use, and shall not be used for the benefit of any other party,
whether or not for consideration.
Patents: Cadence Product Encounter RTL Compiler described in this document, is protected by U.S.
Patents [5,892,687]; [6,470,486]; 6,772,398]; [6,772,399]; [6,807,651]; [6,832,357]; and [7,007,247].
Disclaimer: Information in this publication is subject to change without notice and does not represent a
commitment on the part of Cadence. Except as may be explicitly set forth in such agreement, Cadence does
not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or
usefulness of the information contained in this document. Cadence does not warrant that use of such
information will not infringe any third party rights, nor does Cadence assume any liability for damages or
costs of any kind that may result from use of such information.
Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth
in FAR52.227-14 and DFAR252.227-7013 et seq. or its successor.
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Physical Information in Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Special Files for Physical Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Physical Information in the Design Information Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . 10
2
Simple PLE Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Attributes Affecting the PLE Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reading the LEF Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loading the Capacitance Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reviewing Consistency Between the LEF and Capacitance Table File . . . . . . . . . . .
Checking the Physical Layout Estimation Information . . . . . . . . . . . . . . . . . . . . . . . .
Setting the Appropriate Synthesis Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reading the Floorplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analyzing the Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exporting Files for Place and Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Script for Simple PLE Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
15
16
16
18
19
19
21
22
25
27
28
3
Spatial Flow
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Attributes Affecting the Spatial Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting up the Spatial Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
August 2011
30
31
32
32
33
34
35

Synthesizing with Rapid Placement Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Script for Spatial Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
36
38
41
42
44
45
4
RC-P Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Attributes Affecting the RC-P Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting up the RC-P Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loading the Encounter Configuration File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synthesizing, Estimating, and Optimizing for Silicon . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Script for RC-P Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
50
52
52
53
55
56
56
57
57
59
62
63
65
66
A
Terminology
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
August 2011
73
1
Introduction
Using Physical Information in Synthesis on page 6
Special Files for Physical Flows on page 8
Physical Information in the Design Information Hierarchy on page 10
August 2011

Introduction
Using Physical Information in Synthesis

Traditional synthesis tools use vendor-supplied wire-load models based on fanouts, which do
not provide accurate wire delay information especially for designs where a significant portion
of the delays are contributed by the wires. Consequently, you can see relative big differences
in performance, area, and power between the logic and physical designs.
Custom wire-load models are considered to be the starting point for synthesis, as they are
more accurate than the vendor-supplied wire-load models. But the disadvantage is that you
need to place the design to create custom wire-load models. In addition, placement depends
on an initial pass of gate generation done with ad hoc methods. Furthermore, custom wireload models represent a static view of the design and depend on the netlist used to generate
the placement. As the RTL and constraints change over the design cycle, the custom wireload models become increasingly inaccurate.In many cases, the custom wire-load models
generated at the start of the design can be worse than the vendor-supplied wire-load models
at the end of the project.
Physical layout estimation (PLE) uses physical information to model the effects of placement
based on the current state of the RTL and the constraints, and provides you with a level of
analysis and optimization that would not be available with a traditional synthesis methodology.
Furthermore, using physical information gives a level of down-stream predictability that is
superior to using vendor supplied wire-load models. Predictability will enable you to better
gauge how the design will perform after place and route and help to reduce frontend to
backend hand-off iterations. Ultimately, using physical information in synthesis gives you the
opportunity to develop a smaller, faster design in less time than with traditional synthesis.
Table 1-1 summarizes the differences between performing synthesis using physical layout
estimation or wire-load models.
Table 1-1 PLE versus WLM
Physical Layout Estimation (PLE)
Wire-load Models (WLM)
Uses actual design and physical library

information.
Wire-load models are statistical.
Dynamically calculates wire delays for

different logic structures in the design.
Wire-load models are calculated based on

the nearest calibrated area.
Selection of appropriate wire-load models for
a design is tedious.
Correlates better with place and route.
August 2011
Correlation is difficult even with custom wireload models.

Introduction
RTL Compiler offers three physical-related flows. They provide increasing accuracy in
predicting the wire lengths.
The simple PLE flow uses technology information and cell areas from the LEF libraries
instead of from the synthesis technology libraries. The PLE flow uses parasitic resistance and
capacitance values from the LEF libraries or the capacitance tables (if available) when
estimating the wire lengths. This flow works with all standard RTL Compiler licenses.
The RC-Spatial flow uses in addition a rapid placement to better estimate long wires in your
design. This helps deliver more accuracy to the core synthesis optimization engine during
RTL-to-gate synthesis. This flow works with all standard RTL Compiler licenses, but requires
access to Encounter Digital Implementation System.
The RC-Physical flow uses in addition a complete placement and considers congestion
and legal placement as a cost function during the RTL-to-gates phase, to create a better
netlist. This flow requires an RTL Compiler Physical license and requires access to Encounter
Digital Implementation System.
You do not need a deep, technical knowledge of physical design to use physical information
in RTL Compiler. The usage model is kept simple on purpose and the physical data is as
abstract as possible. Reading through this document should be sufficient to becoming
effective in using physical information in synthesis.
August 2011

Introduction
Special Files for Physical Flows

Figure1-1 shows the data flow for the physical flows.
Figure 1-1 Physical Information Files
DEF
Floorplan
File
Synthesis
Libraries
Encounter
Configuration
File
RTL
Files
Constraint
File
RTL Compiler
LEF
Libraries
SDC
Constraints
Capacitance
Table File
Gate-Level
Netlist
Files
DEF
File
Encounter
Database
Files added
for physical
Optional file
The following file is required for the three physical-related flows.
LEF The LEF libraries are the physical libraries that contain information such as layer,
via, placement site type, routing design rules, process information, and standard cell and
macro cell definitions.
The following file is optional but recommended for the three physical-related flows.
Capacitance Table Capacitance tables contain the same type of parasitic

information as the LEF files but the resistance and capacitance information in the
capacitance table is more detailed and therefore more accurate than in the LEF file. The
August 2011

Introduction
values in a capacitance table comes from the same process definition files that drive sign
off extraction as well as the various other extractors used in Cadence tools.
The following file is optional but recommended in the RC-PLE and RC-Spatial flow, and is
required for the RC-Physical flow:
DEF DEF files are ASCII files that contain information that represent the design at any
point during the layout process. In RTL Compiler, the DEF is primarily used for floorplan
information.
The following file is optional and can be only used in the RC-Physical flow:
Encounter Configuration The Encounter configuration file contains Tcl variables

that describe design information such as the netlist, technology libraries, LEF
information, constraints, capacitance tables, resistance scaling factors, capacitance
scaling factors, and floorplan parameters. The ability to import the settings from an
Encounter Configuration file provides a way for existing Encounter users to quickly get
up and running. The preferred methodology is to specify the settings using native RTL
Compiler commands.
August 2011

Introduction
Physical Information in the Design Information Hierarchy

RTL Compiler stores the original design data along with additional information in the physical
files in the design information hierarchy in the form of attributes. Figure 1-2 shows the design
information hierarchy.
Figure 1-2 Design Information Hierarchy
(rc/>)
root
designs
dex
messages
design_name
object_types
ENC
operating_conditions
PLC
dft
wireload_models
wireload_selections
instances_comb
libcells
instances_hier
physical_cells
instances_seq
nets
operating_conditions
physical
blockages
port_busses_in
gcells
port_busses_out
hdl_libraries
library_name
PHYS
constants
libraries
wireload_models
wireload_selections
libcells
groups
layers
ports_in
pcells
ports_out
pdomains
subdesigns
timing
regions
rows
tracks
August 2011
10

Introduction
The root directory contains the root attributes which apply to all designs that you read in. The
root directory has six main directories.
The designs directory can have several subdirectories each representing a design in
memory.
The dex directory contains information for design exploration.
The hdl_libraries directory contain information about the ChipWare and third party
libraries, and about the Verilog modules and/or VHDL architectures and entities that
were read using the read_hdl command.
The libraries directory can have several subdirectories each representing a

technology library in memory. The physical_cells contain information about the
physical cells that are present in the LEF files (have a LEF MACRO definition), but not in
synthesis libraries.
The messages directory contains all information for all messages that can be displayed
during an RTL Compiler session. Physical-related messages are stored in the ENC,
PHYS, and PLC subdirectories.
The object_types directory lists all attributes for all database objects (designs,
subdesigns, pins, and so on) in the design hierarchy.
As shown in Figure 1-2 on page 10, each design also has several objects. The physical
engine uses and updates physical-specific attributes on the following object types:
Root
Design
Pin
Note: These attributes apply to objects in the pins_in and pins_out directories
subdirectories of objects in the instances_comb, instances_hier, and
instances_seq directories.
Net
Port
Subdesign
Instance
Note: These attributes apply to objects in the instances_comb, instances_hier,
and instances_seq directories.
August 2011
11

Introduction
Each design also has a physical directory with the following subdirectories:
blockages contain information about the blockages defined in the DEF file.
gcells contain information about the global routing cells (gcells). Gcells are derived
from the GCELLGRID statements in the DEF file.
groups contain information about the groups defined in the DEF file.
layers contain information about the metal layers defined in the LEF or capacitance
table file.
pcells contain information about the physical cells (pcells) instantiated in the
COMPONENTS section of the DEF file. Pcells are not instantiated in the netlist.
pdomains contain physical information about the power domains defined in the DEF file.
regions contain information about regions defined in the DEF file.
rows contain information about the rows defined in the DEF file.
tracks contain track (or routing grid) information for each layer. The information is
based on the TRACKS statements in the DEF file.
August 2011
12
2
Simple PLE Flow
Overview on page 14
Attributes Affecting the PLE Flow on page 15
Tasks on page 16
Reading the LEF Libraries on page 16
Loading the Capacitance Information on page 18
Reviewing Consistency Between the LEF and Capacitance Table File on page 19
Checking the Physical Layout Estimation Information on page 19
Setting the Appropriate Synthesis Mode on page 21
Reading the Floorplan on page 22
Analyzing the Results on page 25
Exporting Files for Place and Route on page 27
Sample Script for Simple PLE Flow on page 28
August 2011
13

Simple PLE Flow
Overview
The simple PLE flow does not differ much from the generic flow except that you will be using
LEF files and capacitance tables to drive synthesis. Any steps that overlap with the generic
flow will not be covered in this chapter. Refer to Using Encounter RTL Compiler for more
information on the generic flow.
Figure 2-1 Simple PLE Flow
Start
Target
libraries
LEF
libraries
Capacitance
file
Read timing libraries

Read LEF libraries
Load capacitance table
Review consistency between
LEF and cap table files
HDL
files
Read HDL files and elaborate

design
Modify source
Check physical layout

estimation information
Set synthesis mode
Change physical constraints
DEF
file
Read floorplan
SDC
constraints
Apply constraints
Change SDC constraints
Synthesize
Task added for
Physical
Optional task
August 2011
Analyze
Export design
14
No
Meet
constraints?
Yes

Simple PLE Flow
Attributes Affecting the PLE Flow

Attribute Name
Object
Type
Default
aspect_ratio
design
float
1.0
cap_table_file
root
string
interconnect_mode
root
string
lef_library
root
string
lef_stop_on_error
root
boolean
false
lib_lef_consistency_check_enable
root
boolean
true
number_of_routing_layers
design
integer
shrink_factor
root
float
use_area_from_lef
root
boolean
utilization
layer
float
August 2011
15
wireload
true

Simple PLE Flow
Tasks
The tasks below list only those that are different from the generic flow or illustrate a new step.
Reading the LEF Libraries

LEF files are ASCII files that contain physical library information such as layer, via, placement
site type, routing design rules, process information, and standard cell and macro cell
definitions. The technology information and the cell definitions are usually available in
separate LEF files for easier management.
In the simple PLE flow, the cell area defined in the LEF libraries is used instead of the cell
area defined in the timing library (.lib).
The timing library area will be used if
The physical libraries do not contain any cell definitions.
You only read in the technology LEF file (containing only the metal routing layer
information without the standard cell/macro definitions).
For best results, always use all available LEF files (standard cell, macro and technology LEF).
To import LEF files, use the lef_library attribute. Specify all LEF files, the technology
library and the cell libraries. It is a good practice to specify the technology LEF file first.
The following example imports a technology and cell library LEF files.
rc:/> set_attribute lef_library {tech.lef cell.lef}
August 2011
16

Simple PLE Flow
Use the get_attribute command to confirm the list of imported LEF files:
rc:/> get_attribute lef_library
tech.lef
cell.lef
RTL Compiler will check whether the following definitions are in the LEF file:
CAPACITANCE CPERSQ
EDGECAPACITANCE
RESISTANCE RPERSQ
SITE
WIDTH
If any of these definitions are missing, RTL Compiler will issue a warning message.
If there is at least one MACRO definition in the LEF file, RTL Compiler checks if all the cells in
the timing library have a corresponding definition in the LEF library. Any cells that are defined
in the timing library but not in the LEF will be marked as avoid (they will not be used during
synthesis) and a warning message will be issued. To turn off this consistency checking, set
the lib_lef_consistency_check_enable attribute to false:
rc:/> set_attribute lib_lef_consistency_check_enable false /
The resistance and capacitance information can be found in the capacitance table file.
RTL Compiler supports LEF 5.3 and above. Refer to the LEF/DEF Language Reference
for more information on LEF files.
Troubleshooting Tips
Only one LEF file seems to be imported
Check if the lef_library attribute was set more than once or was part of a loop.
In the following example, the existing LEF file is replaced because it specifies the files
separately with two set_attribute commands as opposed to a Tcl list with one
set_attribute command.
rc:/> set_attribute lef_library tech.lef
rc:/> set_attribute lef_library cell.lef
August 2011
17

Simple PLE Flow
Loading the Capacitance Information

Capacitance tables files contain the same type of parasitic information as the LEF files but
the resistance and capacitance information in the capacitance table has a finer granularity.
The capacitance in a LEF comes from a foundry and is generated by whatever process it sees
as appropriate. The capacitance info in a capacitance table comes from the same process
definition files that drive sign off extraction as well as the various other extractors used in
Cadence tools. The process definition files define layer thicknesses, compositions, and
spacings.
To load the capacitance information, use the cap_table_file attribute:
rc:/> set_attribute cap_table_file my.cap
It is recommended to specify both LEF and capacitance table files. However, you can specify
the LEF files only, if the capacitance table files are not available.
Scaling factors are used to align a design with a particular process. A capacitance table is
process specific where as a scaling factor is design specific. The scaling factors are provided
to be consistent with Encounter. Only use a scaling factor if it will also be used in the backend.
RTL Compiler will check if the following definitions are in the capacitance table file:
PROCESS_VARIATION
BASIC_CAP_TABLE
width
Cc
Carea
Cfrg
If any of these definitions are missing, RTL Compiler will issue a warning message. It will
purposely disregard the EXTENDED_CAP_TABLE section because the PLE is intended to
synchronize with a view of the design where fast extractors are typically used.
Tip
For best results, the corner for the capacitance table file used should match the
corner for the timing library. That is typically max or worst.
August 2011
18

Simple PLE Flow
Reviewing Consistency Between the LEF and Capacitance Table File

After you load both your LEF and capacitance table files, RTL Compiler will perform
consistency checks between the two files. This happens automatically, much like the check
between the LEF and timing library files.
Number of Layers RTL Compiler will check to determine if the number of layers
defined in the LEF and the capacitance table files are equal.
If the LEF has more layers than the capacitance table, then an error message will be
issued and you will need to manually check both of the files to resolve the inconsistency.
If the capacitance table has more layers than the LEF, a warning message will be issue
and the number of routing layers will be set to the number specified in the capacitance
table.
Width of Layers RTL Compiler will check to determine if the width of the layers
defined in the LEF and the capacitance table files are equal. A warning will only be issued
if the width difference defined in the two files is greater than 10%.
RTL Compiler reports the inconsistencies in the log file. You should review the log file. For
example, check for messages PHYS 24 through 27.
Checking the Physical Layout Estimation Information

After loading the LEF libraries, the capacitance information, and the design information, you
can check the physical layout estimation information for the design.
To report the physical layout estimation information for the design, once all physical data
has been read in, use the following command:
report ple
As shown in Figure 2-2 on page 20, this command reports information like aspect ratio, shrink
factor, site size, layer names, direction of layers, capacitance, resistance, and area. It also
shows the source that it used to extract the physical information.
The report header contains an Interconnect mode line which indicates that you are
running in PLE mode. In this case, the value is set to global because you run the report before
the design is synthesized.
August 2011
19

Simple PLE Flow
Figure 2-2 Example of Report PLE
rc:/> report ple
============================================================
Generated by:
Encounter(R) RTL Compiler 10.1.100
Generated on:
Apr 30 2010 03:29:32 pm
Module:
DTMF_CHIP
Technology libraries:
tsmc18 1.0
tpz973g 230
pllclk 4.3
ram_128x16A 1.1
ram_256x16A 1.1
rom_512x16A 1.1
physical_cells
Operating conditions:
slow
Interconnect mode:
global
Area mode:
physical library
============================================================
Aspect ratio
Shrink factor
Scale of res/length
Scale of cap/length
Net derating factor
Site size
:
:
:
:
:
:
1.00
1.00
1.00
1.00
1.00
5.70 um (from lef [tech+cell])
Capacitance
Layer
/ Length
Name
Direction Utilization (pF/micron)
-----------------------------------------------M1
H
1.00
0.000274
M2
V
1.00
0.000242
M3
H
1.00
0.000242
M4
V
1.00
0.000242
M5
H
1.00
0.000242
M6
V
1.00
0.000304
Resistance
Layer
/ Length
Name
Direction Utilization (ohm/micron)
------------------------------------------------Metal1
H
1.00
0.439130
Metal2
V
1.00
0.360714
Metal3
H
1.00
0.360714
Metal4
V
1.00
0.360714
Metal5
H
1.00
0.360714
Metal6
V
1.00
0.102273
Area
Layer
/ Length
Name
Direction Utilization
(micron)
------------------------------------------------Metal1
H
1.00
0.230000
Metal2
V
1.00
0.280000
Metal3
H
1.00
0.280000
Metal4
V
1.00
0.280000
Metal5
H
1.00
0.280000
Metal6
V
1.00
0.440000
Data source:
cap_table_file
Data source:
lef_library
Data source:
lef_library
rc:/>
August 2011
20

Simple PLE Flow
Setting the Appropriate Synthesis Mode

RTL Compiler has two synthesis modes: wireload and ple. These modes are set using the
interconnect_mode attribute.
In wireload mode (default), you use wire-load models to drive synthesis.
In ple mode, you use Physical Layout Estimation (PLE) to drive synthesis. PLE is the
process of using physical information, such as LEF libraries, to provide better closure
with back-end tools
When you read in LEF libraries, the interconnect_mode attribute is automatically set to
ple.
Note: If you want to use wireload mode, you must manually set the interconnect_mode
attribute to wireload after loading the LEF libraries.
For this flow, do not change the setting.
August 2011
21

Simple PLE Flow
Reading the Floorplan

Similar to providing timing and design constraints for the logic design, you should provide
physical constraints in the form of a floorplan when you use PLE.
In RTL Compiler, you provide floorplan information through a DEF file.
The die or block bounding box determines the placement area and therefore influences
the net length.
Pin and macro locations influence the standard cell placement and thus the net length.
RTL Compiler supports DEF 5.3 and above. Refer to the LEF/DEF Language Reference
for more information on DEF files.
To import a DEF file, use the read_def command.

rc:/> read_def def_file
RTL Compiler will perform a consistency check between the DEF and the Verilog netlist and
issue relevant messages if necessary. For example:
Parsing DEF file...
Warning : A DEF component does not exist in the netlist. [PHYS-171]
: The component IOPADS_INST/Pcornerll does not exist.
: This message has a default max print count of 25, which can be
changed by setting the max_print attribute.
: The component IOPADS_INST/Pcornerlr does not exist.
...
Done parsing DEF file.
The DEF file must define the die size. For better synthesis results, you should also have the
pin, macro locations, and standard cell placement specified in the DEF, although it is not
required.
Figure 2-3 on page 23 shows an example of DEF statistics printed after the DEF file has been
processed.
August 2011
22

Simple PLE Flow
Figure 2-3 Example of DEF Statistics
Summary report for DEF file /xxx/floorplan/fplan_mp.def
Components
---------Cover: 0
Fixed: 71
Physical: 0
Placed: 0
Unplaced: 1
TOTAL: 72 (1 is class macro)
There are 4 components that do not exist in the netlist.
Pins
---Cover: 0
Fixed: 0
Placed: 0
Unplaced: 57
TOTAL: 57
Fences: 0
Guides: 1
Regions: 0
Done processing DEF file.
Done reading and processing DEF file (time: 2s).
Table 2-1 Component Types

Type
Explanation
Tip
Cover
A component that has a location and is a part of A large number of cover cells can indicate that
a cover macro. A COVER component cannot be the DEF file is not a floorplan but instead
moved.
could be the DEF for a fully placed design.
Fixed
A component that has a location and that cannot All components in a floorplan DEF should be
be moved by automatic tools.
set as fixed to avoid unwanted movement
during placement
Physical
A component that is instantiated in the DEF but A large number of physical components can
not in the netlist.
indicate that the DEF is not a floorplan DEF.
Placed
A component that has a location and that cannot These components are not expected in a
floorplan.
Unplaced
A component that has no location.
These components are not expected in a

floorplan.
class macro A large component. For example, a memory.
August 2011
23
The number of class macros should be less

than or equal to the number of fixed
components.

Simple PLE Flow
Table 2-2 Pin Types
Type
Explanation
Tip
Cover
A pin that has a location, orientation, and that is

part of the cover macro. A COVER pin cannot
be moved
Fixed
A pin that has a location, orientation and that

cannot be moved by automatic tools.
Placed

can be moved by automatic tools.
Unplaced
A pin that has no location.
It is recommended to have all pins fixed.
There is also a summary of the blockages defined in the DEF file:

Fences: 0
Guides: 1
Regions: 0
For more information on these terms, refer to the Glossary on page 69

To check which DEF is loaded in the tool, use the def_file attribute:
rc:/> get_attribute def_file /designs/design
August 2011
24

Simple PLE Flow
Analyzing the Results
To print an area report, use the report area command.

rc:/> report area
============================================================
Generated by:
Encounter(R) RTL Compiler version
Generated on:
date
Module:
DTMF_CHIP
library1
library2
...
physical_cells
slow
Interconnect mode:
global
Area mode:
physical library
============================================================
Instance
Cells Cell Area Net Area
------------------------------------------------------DTMF_CHIP
4983
1218171
74724
IOPADS_INST
67
721450
0
DTMF_INST
4916
496721
71135
TDSP_CORE_INST
2887
75922
42639
MPY_32_INST
829
22776
11393
M16X16_INST
646
19859
9970
EXECUTE_INST
631
21445
9196
ALU_32_INST
584
8858
9875
TDSP_CORE_GLUE_INST
458
8073
5268
DECODE_INST
157
5279
3265
PORT_BUS_MACH_INST
57
2635
759
DATA_BUS_MACH_INST
55
2644
695
PROG_BUS_MACH_INST
57
2628
498
TDSP_CORE_MACH_INST
36
1221
383
ACCUM_STAT_INST
17
316
1278
RAM_256x16_TEST_INST
17
113630
132
17
100778
132
ARB_INST
22
69455
609
RESULTS_CONV_INST
1737
44963
23431
SPI_INST
45
2415
509
DMA_INST
45
1943
507
DATA_SAMPLE_MUX_INST
28
659
1546
ULAW_LIN_CONV_INST
58
1207
592
DIGIT_REG_INST
10
725
146
TDSP_DS_CS_INST
22
446
123
TDSP_MUX
17
439
12
TEST_CONTROL_INST
8
126
49
The Interconnect mode in the report header is still set to global because in the simple
PLE flow the design is synthesized without placement information.
The report shows the total count of cells mapped against the hierarchical blocks, the
combined cell area in each of the blocks and the top level design. The Cell Area numbers
are based on the information in the LEF libraries. The Net Area refers to the estimated postroute net area and is based on the minimum wire widths defined in the LEF and capacitance
table files and the area of the design blocks.
August 2011
25

Simple PLE Flow
To get an overall report containing slack information, instance count, area information,
cell power, runtime, and host name information, use the report qor command.
rc:/> report qor
============================================================
Generated by:
...
Interconnect mode:
global
Area mode:
physical library
============================================================
Timing
-------Clock Period
-------------vclk01 5000.0
vclk02 6000.0
vclk1 5000.0
vclk2 5000.0
Cost
Critical
Violating
Group
Path Slack
TNS
Paths
-------------------------------------default
No paths
0
vclk01
No paths
0
vclk02
No paths
0
vclk1
-543.9
-615
2
vclk2
2021.0
0
0
-------------------------------------Total
-615
2
Instance Count
-------------Leaf Instance Count
Sequential Instance Count
Combinational Instance Count
Hierarchical Instance Count
4983
546
4437
26
Area & Power

-----------Total Area
Cell Area
Floorplan Utilization
Leakage Power
Dynamic Power
Total Power
1292895.607
1218171.484
39.53%
4527.609 nW
151413275.127 nW
151417802.736 nW
Max Fanout
Min Fanout
Average Fanout
Terms to net ratio
Terms to instance ratio
Runtime
Hostname
540 (scan_enI)
0 (n_3)
2.5
3.5
3.9
202.34 seconds
rcae005
Since you performed physical synthesis and started with a floorplan, the report also contains
the floorplan utilization in %.
August 2011
26

Simple PLE Flow
Exporting Files for Place and Route

The final part of the physical flow involves exporting the data for place and route processing.
This is done through the write_design -encounter command.
The write_design -encounter command generates the following files:
Netlist (.v)
Encounter configuration file (.conf),
SDC constraints (.sdc)
Tcl script (.enc_setup.tcl)
Mode file (.mode)
DEF file (.def)
Timing derate file (.derate.tcl) generated when RTL Compiler changed the default
timing derate values
August 2011
27

Simple PLE Flow
Sample Script for Simple PLE Flow

set_attribute source_verbose true /
set_attribute information_level 9 /
suppress_message "xxx "
set_attribute enc_temp_dir rc_enc /
set_attribute lib_search_path path /
set_attribute library "library_list" /
set_attribute lef_library "lef_list" /
set_attribute cap_table_file file /
read_hdl DESIGN/dtmf_chip.v
elaborate DTMF_CHIP
report ple
read_sdc dtmf.sdc
read_def DESIGN/floorplan/dtmf.def
synthesize -to_mapped
report area
report qor
write_design -encounter
August 2011
28
3
Spatial Flow
Overview on page 30
Attributes Affecting the Spatial Flow on page 31
Tasks on page 32
Setting up the Spatial Flow on page 32
Synthesizing with Rapid Placement Input on page 41
Sample Script for Spatial Flow on page 45
August 2011
29

Spatial Flow
Overview
In addition to using technology information and cell areas from the LEF libraries, and parasitic
resistance and capacitance values from the LEF libraries or capacitance tables, the RC-Spatial
flow uses a rapid placement to better estimate long wires in your design. This improves the
accuracy of the core synthesis optimization engine during RTL-to-gate synthesis.
This flow is useful for blocks or chips with simple floorplans.
Figure 3-1 Spatial Flow
Start
Target
libraries
LEF
libraries
Read LEF libraries
Capacitance
file

HDL
files

design
Modify source
Set synthesis mode

DEF
file
Read floorplan
SDC
constraints
Apply constraints
Synthesize with rapid

placement input
Task added for
Physical
Analyze
Optional task
August 2011
Export design
30
No
Meet
constraints?
Yes

Spatial Flow
Attributes Affecting the Spatial Flow

Attribute Name
Object
Type
Default
aspect_ratio
design
float
1.0
cap_table_file
root
string
encounter_executable
root
init_core_utilization
design
float
interconnect_mode
root
string
lef_library
root
string
lef_stop_on_error
root
boolean
false
root
boolean
true
design
integer
pqos_ignore_msv
root
boolean
false
pqos_ignore_scan_chains
root
boolean
false
qos_report_power
root
boolean
false
scale_of_cap_per_unit_length
root
float
1.0
scale_of_res_per_unit_length
root
float
1.0
shrink_factor
root
float
use_area_from_lef
root
boolean
utilization
layer
float
August 2011
31
wireload
true

Spatial Flow
Tasks
The tasks below list only those that are different from the generic flow or illustrate a new step.
Setting up the Spatial Flow on page 32
Synthesizing with Rapid Placement Input on page 41
Setting up the Spatial Flow
To specify the Encounter executable that you want to use for the
synthesize -spatial command, set the following root attribute:
set_attribute encounter_executable path_to_soc_executable /
If this attribute is not set, the following (default) search order is used:
1. ENCOUNTER environment variable
2. PATH environment variable
3. CDS_SYNTH_ROOT environment variable
August 2011
32

Spatial Flow

In the spatial flow, the cell area defined in the LEF libraries is used instead of the cell area
defined in the timing library (.lib).
tech.lef
cell.lef
CAPACITANCE CPERSQ
EDGECAPACITANCE
RESISTANCE RPERSQ
SITE
WIDTH
August 2011
33

Spatial Flow
The resistance and capacitance information can be found in the capacitance table file.

spacings.
to be consistent with Encounter. Only use a scaling factor if it will also be used in the backend.
August 2011
34

Spatial Flow
PROCESS_VARIATION
BASIC_CAP_TABLE
width
Cc
Carea
Cfrg
Tip

If the capacitance table has more layers than the LEF, a warning message will be issue
table.
August 2011
35

Spatial Flow

with back-end tools
ple.
For this flow, do not change the setting.

report ple
August 2011
36

Spatial Flow
rc:/> report ple
============================================================
Generated by:
Generated on:
Apr 30 2010 03:29:32 pm
Module:
DTMF_CHIP
tsmc18 1.0
tpz973g 230
pllclk 4.3
ram_128x16A 1.1
ram_256x16A 1.1
rom_512x16A 1.1
physical_cells
slow
Interconnect mode:
global
Area mode:
physical library
============================================================
Aspect ratio
Shrink factor
Scale of res/length
Scale of cap/length
Net derating factor
Site size
:
:
:
:
:
:
1.00
1.00
1.00
1.00
1.00
Capacitance
Layer
/ Length
Name
-----------------------------------------------M1
H
1.00
0.000274
M2
V
1.00
0.000242
M3
H
1.00
0.000242
M4
V
1.00
0.000242
M5
H
1.00
0.000242
M6
V
1.00
0.000304
Resistance
Layer
/ Length
Name
------------------------------------------------Metal1
H
1.00
0.439130
Metal2
V
1.00
0.360714
Metal3
H
1.00
0.360714
Metal4
V
1.00
0.360714
Metal5
H
1.00
0.360714
Metal6
V
1.00
0.102273
Area
Layer
/ Length
Name
(micron)
------------------------------------------------Metal1
H
1.00
0.230000
Metal2
V
1.00
0.280000
Metal3
H
1.00
0.280000
Metal4
V
1.00
0.280000
Metal5
H
1.00
0.280000
Metal6
V
1.00
0.440000
Data source:
cap_table_file
Data source:
lef_library
Data source:
lef_library
rc:/>
August 2011
37

Spatial Flow

Similar to providing timing and design constraints for the logic design, you should provide
physical constraints in the form of a floorplan when you use a physical flow.
In RTL Compiler, you provide floorplan information through a DEF file.
The die or block bounding box determines the placement area and therefore influences
the net length.
Pin and macro locations influence the standard cell placement and thus the net length.

Parsing DEF file...
...
required.
processed.
August 2011
38

Spatial Flow
Components
---------Cover: 0
Fixed: 71
Physical: 0
Placed: 0
Unplaced: 1
Pins
---Cover: 0
Fixed: 0
Placed: 0
Unplaced: 57
TOTAL: 57
Fences: 0
Guides: 1
Regions: 0

Type
Explanation
Tip
Cover
moved.
Fixed
during placement
Physical
not in the netlist.
Placed
floorplan.
Unplaced

floorplan.
August 2011
39

components.

Spatial Flow
Table 3-2 Pin Types
Type
Explanation
Tip
Cover

be moved
Fixed

Placed

Unplaced

Fences: 0
Guides: 1
Regions: 0

August 2011
40

Spatial Flow
Synthesizing with Rapid Placement Input

After you have set the logical and physical constraints for your design, you can proceed with
synthesizing your design.
To improve the modeling of the long wires and thus add more physical reality to the cost
functions used for optimization, use the following command:
sythesize -to_mapped -spatial
Important
You must have access to the Encounter place and route tool to run this command
option.
This command performs a fast coarse-grained placement to get a better estimate of the long
wires.
For a verification-friendly flow, you can break up the synthesis steps as follows:
synthesize -to_generic
synthesize -to_mapped -no_incremental
synthesize -to_mapped -incremental
synthesize -to_mapped -spatial
synthesize -to_mapped -spatial -incremental
August 2011
41

Spatial Flow
To print an area report, use the report area command.
rc:/> report area

============================================================
Generated by:
Generated on:
date
Module:
DTMF_CHIP
library1
library2
...
physical_cells
slow
Interconnect mode:
spatial
Area mode:
physical library
============================================================
Instance
------------------------------------------------------DTMF_CHIP
5720
1220743
123052
IOPADS_INST
67
721450
311
DTMF_INST
5653
499293
122741
TDSP_CORE_INST
3609
83409
70264
MPY_32_INST
1041
24512
15298
M16X16_INST
777
20763
13663
EXECUTE_INST
720
22094
12903
ALU_32_INST
889
13079
15493
TDSP_CORE_GLUE_INST
518
8243
7212
DECODE_INST
172
5525
5968
PORT_BUS_MACH_INST
57
2668
5212
DATA_BUS_MACH_INST
80
2854
4718
PROG_BUS_MACH_INST
56
2658
556
ACCUM_STAT_INST
21
349
2415
TDSP_CORE_MACH_INST
47
1321
489
17
113630
2061
17
100778
2415
ARB_INST
24
69452
6252
RESULTS_CONV_INST
1711
39967
25442
27
662
11334
SPI_INST
48
2425
1189
DMA_INST
59
1976
836
DIGIT_REG_INST
12
738
1526
ULAW_LIN_CONV_INST
82
1194
574
TEST_CONTROL_INST
6
160
417
TDSP_DS_CS_INST
22
449
91
TDSP_MUX
17
439
46
The Interconnect mode in the report header is now set to spatial because the design
was synthesized using fast placement information.
are based on the information in the LEF libraries. The Net Area refers to the estimated postroute net area and is based on the minimum wire widths defined in the LEF and capacitance
table files and the area of the design blocks.
August 2011
42

Spatial Flow
rc:/> report qor
============================================================
Generated by:
...
Interconnect mode:
spatial
Area mode:
physical library
============================================================
Timing
-------Clock Period
-------------vclk01 5000.0
vclk02 6000.0
vclk1 5000.0
vclk2 5000.0
Cost
Critical
Violating
Group
Path Slack
TNS
Paths
-------------------------------------default
No paths
0
vclk01
No paths
0
vclk02
No paths
0
vclk1
-1731.7
-3672
19
vclk2
2273.9
0
0
--------------------------------------Total
-3672
19
Instance Count
5720
546
5174
26
Area & Power

Cell Area
Leakage Power
Dynamic Power
Total Power
1343795.081
1220742.791
41.16%
4306.242 nW
154232405.582 nW
154236711.824 nW
Max Fanout
Min Fanout
Average Fanout
Terms to net ratio
Runtime
Hostname
540 (scan_enI)
0 (DTMF_INST/n_197)
2.6
3.6
4.0
77 seconds
rcae005
August 2011
43

Spatial Flow
Note: Comparing the results with the results of the simple PLE flow, you may notice some
apparent degradation in some of the metrics. This degradation is to be expected since spatial
mode incorporates placement information, and thus more accurate wire lengths and delays
are used. Therefore, the results are a better indicator of the results that will be achieved once
you have performed place and route.

Netlist (.v)
Mode file (.mode)
DEF file (.def) of the floorplan
Timing derate file (.derate.tcl) generated when RTL Compiler changed the
default timing derate values
An encrypted file containing placement information (.spl.etf)

To reload this file, use the decrypt command.
August 2011
44

Spatial Flow
Sample Script for Spatial Flow

set_attribute encounter_executable path_to_soc_executable
elaborate DTMF_CHIP
report ple
read_sdc dtmf.sdc
synthesize -to_mapped -spatial
synthesize -to_mapped -spatial -incremental
report area
report qor
August 2011
45

Spatial Flow
August 2011
46
4
RC-P Flow
Overview on page 48
Attributes Affecting the RC-P Flow on page 50
Tasks on page 52
Setting up the RC-P Flow on page 52
Loading the Encounter Configuration File on page 57
Synthesizing, Estimating, and Optimizing for Silicon on page 62
August 2011
47

RC-P Flow
Overview
In addition to using technology information and cell areas from the LEF libraries, and parasitic
resistance and capacitance values from the LEF libraries or capacitance tables, the RC-P
flow uses a complete placement and considers congestion and legal placement as a cost
function during the RTL-to-gates phase, to create a better netlist. This flow ensures both the
best accuracy and the most predictable closure with back-end tools.
Specifically, the physical flow will:
Use physical process information along with areas and fanout to dynamically derive wire
length
Calculate load and delay using average resistance (in OHMs per micron) and
capacitance (in pF per micron) per unit length. The resistance and capacitance are
derived from the process technology information.
Alternatively, extracted resistance and capacitance parasitic information is used when
available.
Calculate wire area in microns using the average net width from the process technology
information
Use a Silicon Virtual Prototype to predict the physical effects on the quality of silicon
Perform physically-aware optimization
This flow is useful for blocks or chips with complex floorplans.
August 2011
48

RC-P Flow
Figure 4-1 RC-P Flow
Start
Target
libraries
LEF
libraries
Read LEF libraries
Capacitance
file

HDL
files

design
Modify source
Set synthesis mode

DEF
file
SDC
constraints

Read floorplan
Apply constraints
Synthesize, estimate, and
optimize for silicon with
synthesize
-to_placed
Analyze
Task added for

Physical
Perform incremental
optimization with
synthesize
-to_placed
-incremental
No
Meet
constraints?
Yes
Optional task
Export design
August 2011
49

RC-P Flow
Attributes Affecting the RC-P Flow

Attribute Name
Object
Type
Default
aspect_ratio
design
float
1.0
auto_super_thread
root
boolean
true
cap_table_file
root
string
congestion_avoid
libcell
boolean
false
congestion_effort
root
string
off
def_output_escape_multibit
root
boolean
true
def_output_version
root
string
5.7
enc_assign_buffer
root
string
none
enc_assign_removal
root
boolean
false
enc_force_place_incr
root
boolean
false
enc_gzip_interface_files
root
boolean
true
enc_in_place_opt
root
boolean
false
enc_launch_servers
root
string
enc_module_plan
root
boolean
true
enc_opt_drv
root
boolean
false
enc_pre_place_opt
root
boolean
false
enc_temp_dir
root
string
enc_timing_driven_place
root
boolean
enc_user_contsraint_file
root
string
enc_user_mode_file
root
string
encounter_executable
root
init_core_utilization
design
float
interconnect_mode
root
string
lef_library
root
string
lef_stop_on_error
root
boolean
August 2011
50
true
wireload
false

RC-P Flow
Attribute Name
Object
Type
Default
root
boolean
true
design
integer
phys_fix_multi_height_cells
root
boolean
false
phys_ignore_special_nets
design
boolean
false
pqos_ignore_msv
root
boolean
false
pqos_ignore_scan_chains
root
boolean
false
pqos_placement_effort
root
string
no_value
qos_report_power
root
boolean
false
scale_of_cap_per_unit_length
root
float
1.0
scale_of_res_per_unit_length
root
float
1.0
shrink_factor
root
float
use_area_from_lef
root
boolean
utilization
layer
float
August 2011
51
true

RC-P Flow
Tasks
The tasks below list only those that are different from the generic synthesis flow or illustrate
a new step.
Setting up the RC-P Flow on page 52
Loading the Encounter Configuration File on page 57
Synthesizing, Estimating, and Optimizing for Silicon on page 62
Setting up the RC-P Flow
To specify the Encounter executable that you want to use for the RC-P flow, set the
following root attribute:
set_attribute encounter_executable path_to_soc_executable /
If this attribute is not set, the following (default) search order is used:
1. ENCOUNTER environment variable
2. PATH environment variable
3. CDS_SYNTH_ROOT environment variable
August 2011
52

RC-P Flow

In the RC-P flow, the cell area defined in the LEF libraries is used instead of the cell area
defined in the timing library (.lib).
tech.lef
cell.lef
CAPACITANCE CPERSQ
EDGECAPACITANCE
RESISTANCE RPERSQ
SITE
WIDTH
August 2011
53

RC-P Flow
August 2011
54

RC-P Flow

spacings.
to be consistent with Encounter. Only use a scaling factor if it will also be used in the
back-end.
PROCESS_VARIATION
BASIC_CAP_TABLE
width
Cc
Carea
Cfrg
Tip
August 2011
55

RC-P Flow

If the capacitance table has more layers than the LEF, a warning message will be issued
table.

with back-end tools
ple.
Do not change the setting for the RC-P flow.
August 2011
56

RC-P Flow
Loading the Encounter Configuration File

The Encounter configuration file contains Tcl variables that describe design information such
as the RTL or netlist, technology libraries, LEF information, constraints, capacitance tables,
resistance scaling factors, capacitance scaling factors, and floorplan parameters.
Load the Encounter configuration file through the read_encounter command. If you load
an Encounter configuration file, the only other input you need to load is the DEF file (for the
floorplan).
rc:/> read_encounter config my_design.conf
Tip
If you load an Encounter configuration file, you do not need to load the timing library,
LEF library, capacitance table file, RTL or netlist, and constraints.
set_attribute library
set_attribute lef_library
set_attribute cap_table_file
read_hdl
set SDC
read_encounter config

report ple
August 2011
57

RC-P Flow
rc:/> report ple
============================================================
Generated by:
Generated on:
June 30 2010 03:29:32 pm
Module:
DTMF_CHIP
tsmc18 1.0
tpz973g 230
pllclk 4.3
ram_128x16A 1.1
ram_256x16A 1.1
rom_512x16A 1.1
physical_cells
slow
Interconnect mode:
global
Area mode:
physical library
============================================================
Aspect ratio
Shrink factor
Scale of res/length
Scale of cap/length
Net derating factor
Site size
:
:
:
:
:
:
1.00
1.00
1.00
1.00
1.00
Capacitance
Layer
/ Length
Name
-----------------------------------------------M1
H
1.00
0.000274
M2
V
1.00
0.000242
M3
H
1.00
0.000242
M4
V
1.00
0.000242
M5
H
1.00
0.000242
M6
V
1.00
0.000304
Resistance
Layer
/ Length
Name
------------------------------------------------Metal1
H
1.00
0.439130
Metal2
V
1.00
0.360714
Metal3
H
1.00
0.360714
Metal4
V
1.00
0.360714
Metal5
H
1.00
0.360714
Metal6
V
1.00
0.102273
Area
Layer
/ Length
Name
(micron)
------------------------------------------------Metal1
H
1.00
0.230000
Metal2
V
1.00
0.280000
Metal3
H
1.00
0.280000
Metal4
V
1.00
0.280000
Metal5
H
1.00
0.280000
Metal6
V
1.00
0.440000
Data source:
cap_table_file
Data source:
lef_library
Data source:
lef_library
rc:/>
August 2011
58

RC-P Flow

Similar to providing timing and design constraints for the logic design, you must provide
physical constraints in the form of a floorplan in the physical flow.
In RTL Compiler, you provide floorplan information through a DEF file. DEF files can contain
both logical information and physical information.
Logical information includes grouping information and physical constraints
Physical information includes
The die or block bounding box

The die determines the placement area and therefore influences the net length.
Pin and macro locations

These influence the standard cell placement and thus the net length.

Parsing DEF file...
...
required. After reading the DEF you can view the floorplan in the GUI.
processed.
August 2011
59

RC-P Flow
Components
---------Cover: 0
Fixed: 71
Physical: 0
Placed: 0
Unplaced: 1
Pins
---Cover: 0
Fixed: 0
Placed: 0
Unplaced: 57
TOTAL: 57
Fences: 0
Guides: 1
Regions: 0

Type
Explanation
Tip
Cover
moved.
Fixed
during placement
Physical
not in the netlist.
Placed
floorplan.
Unplaced

floorplan.
August 2011
60

components.

RC-P Flow
Table 4-2 Pin Types
Type
Explanation
Tip
Cover

be moved
Fixed

Placed

Unplaced

Fences: 0
Guides: 1
Regions: 0

August 2011
61

RC-P Flow
Synthesizing, Estimating, and Optimizing for Silicon

After you have set the logical and physical constraints for your design, you can proceed with
synthesizing your design.
To synthesize the design while using the full power of Silicon Virtual Prototyping (SVP),
use the following command:
synthesize -to_placed
The synthesize -to_placed command generates a Silicon Virtual Prototype (SVP) to

gauge the quality of silicon of the design. The steps in the SVP creation process include:
Placement
Trial route
Parasitic extraction
The detailed placement information and the resistance and capacitance parasitics are then
used for delay calculation and annotation of physical delays.
The synthesize -to_placed command will operate in incremental mode if the standard
cells are placed. Virtual buffering will be performed by default.
The synthesize -to_placed command will not work with encrypted netlists.Therefore,
decrypt your netlist before using this command.
Important
You will need an RC 400 license to execute the command and access to an
Encounter executable of version 8.1 or later. However, it is highly recommended that
you use the same versions of Encounter and RTL Compiler.
For a verification-friendly flow, you can break up the synthesis steps as follows:
synthesize -to_placed -incremental
See Attributes Affecting the RC-P Flow for a list of attributes that affect the result of the
synthesize -to_placed command.
August 2011
62

RC-P Flow
To print an area report, use the report area report.
rc:/> report area

Computing net loads.
============================================================
Generated by:
Generated on:
date
Module:
DTMF_CHIP
library1
library2
...
physical_cells
slow
Interconnect mode:
placement
Area mode:
physical library
============================================================
Instance
------------------------------------------------------DTMF_CHIP
5699
1220490
120193
IOPADS_INST
67
721450
313
DTMF_INST
5632
499040
119880
TDSP_CORE_INST
3604
83386
67203
MPY_32_INST
1043
24489
14093
M16X16_INST
782
20797
12688
EXECUTE_INST
720
22094
11388
ALU_32_INST
887
13116
16376
TDSP_CORE_GLUE_INST
515
8256
6962
DECODE_INST
172
5522
5539
PORT_BUS_MACH_INST
57
2668
4661
DATA_BUS_MACH_INST
81
2854
4400
PROG_BUS_MACH_INST
56
2658
556
ACCUM_STAT_INST
21
349
2715
TDSP_CORE_MACH_INST
48
1327
512
17
113630
1983
17
100778
2236
ARB_INST
22
69442
5806
RESULTS_CONV_INST
1707
39750
28387
27
662
9789
SPI_INST
48
2428
708
DIGIT_REG_INST
12
738
1928
DMA_INST
58
1979
559
ULAW_LIN_CONV_INST
75
1198
510
TDSP_DS_CS_INST
20
436
104
TEST_CONTROL_INST
6
160
336
TDSP_MUX
17
439
39
The Interconnect mode in the report header is now set to placement because the
design is synthesized using detailed placement information.
are based on the information in the LEF libraries. The Net Area refers to the estimated
post-route net area and is based on the minimum wire widths defined in the LEF and
capacitance table files and the area of the design blocks.
August 2011
63

RC-P Flow
rc:/> report qor
============================================================
Generated by:
...
Interconnect mode:
placement
Area mode:
physical library
============================================================
Timing
-------Clock Period
-------------vclk01 5000.0
vclk02 6000.0
vclk1 5000.0
vclk2 5000.0
Cost
Critical
Violating
Group
Path Slack
TNS
Paths
--------------------------------------default
No paths
0
vclk01
No paths
0
vclk02
No paths
0
vclk1
-1683.1
-2853
17
vclk2
2340.8
0
0
--------------------------------------Total
-2853
17
Instance Count
5699
546
5153
26
Area & Power

Cell Area
Leakage Power
Dynamic Power
Total Power
1340683.252
1220489.984
41.08%
4305.304 nW
157594103.325 nW
157598408.630 nW
Max Fanout
Min Fanout
Average Fanout
Terms to net ratio
Runtime
Hostname
540 (scan_enI)
0 (DTMF_INST/n_197)
2.6
3.6
4.0
79 seconds
rcae006
Silicon Virtual Prototype

------------------------Total Net Length
Average Net Length
Routing Congestion
446549.55 um
71.84 um
H: 0.83% V: 1.85%
August 2011
64

RC-P Flow
Because you executed the synthesize -to_placed command, the QoR report also
contains a Silicon Virtual Prototype section that lists the total and average net length in
micron, and the routing congestion in %. Routing congestion is a measure of track overflow.

Netlist (.v)
Mode file (.mode)
DEF file (.def)
Timing derate file (.derate.tcl) generated when RTL Compiler changed the default
timing derate values
Congestion map (.cmap.gz)
Note: The full DEF file that is generated is the exact same DEF file that was loaded or
generated by synthesize -to_placed. However, RTL Compiler generates the
information for the Scan DEF file (.scan.def). Although the scan chains will be re-ordered
in the back-end once the placement is determined, any scan reordering done in synthesis is
based on the current placement. This placement may not be carried forward. For example,
the placement will change if more optimization is done in RTL Compiler. There will always be
slight adjustments to the scan order, which are best accomplished in the back-end. The scan
DEF file is generated for continual convergence: getting closer to the final result with each
reordering.
Use the -basename option to specify both an output directory and a custom basename:
rc:/> write_design -encounter -basename output/final
August 2011
65

RC-P Flow
Sample Script for RC-P Flow

set_attribute encounter_executable path_to_soc_executable
elaborate DTMF_CHIP
report ple
read_sdc dtmf.sdc
synthesize -to_placed -incremental
report area
report qor
August 2011
66
A
Terminology
Abbreviations on page 68
Glossary on page 69
August 2011
67

Terminology
Abbreviations
DEF
Design Exchange Format
LEF
Library Exchange Format
PLE
Physical layout Estimation
R/C
Resistance/Capacitance (parasitics)
RC-P
Encounter RTL Compiler with Physical
SDC
Synopsys Design Constraints
SPEF
Standard Parasitic Exchange Format
SVP
Silicon Virtual Prototype
WLM
Wire Load Model
August 2011
68

Terminology
Glossary
Term
Origin
Definition
BLOCKAGES
DEF
Prevent either placement or routing in the

specified area. Types are:
LAYERprevent signal net routing
PLACEMENTprevent placement. See also
SOFT, PARTIAL, and PUSHDOWN.
CLASS
DEF
Defines the macro type. Examples are:

BLOCKhierarchical block
COREstandard cell, including memory cells
COVERcontains fixed floorplan data, such as
power routing
PADI/O cell
congestion
tool
density screen
Measures the routability of the design by

comparing the number of required tracks and
the number of available tracks.
See PARTIAL
FENCE
DEF
Type of REGION that only allows instances

associated with the region to be placed in it.
FILL
DEF
Rectangular shape that defines a metal fill in

the design.
gcell
One unit of the GCELLGRID.
GCELLGRID
DEF
Global routing grid whose cells enclose a

specified number of tracks
GROUPS
DEF
Defines a group of components (logical

elements) that are typically placed close
together.
You can associate a REGION with a group. If
you do not associate a region with the group,
the group can be placed anywhere but the
instances in the group will be placed closely
together.
August 2011
69

Terminology
GUIDE
DEF
Type of REGION in which instances associated

with the region should be placed by preference.
Other instances can also be placed in this
region, and the instances associated with the
region can migrate outside the boundary of the
region.
HALO
DEF
Placement blockage around a component. This

type of blockage is associated with the
component. As a result a halo moves with the
component.
MACRO
LEF
Physical description of a library cell.
morphing
RC
Congestion optimization technique that moves

cells from high utilization regions to low
utilization regions.
OBS
LEF
Routing layer obstruction associated with a

MACRO.
PARTIAL (placement
blockage)
DEF
Type of PLACEMENT blockage that allows a

percentage of the blockage area to be used for
standard cells during initial placement.
pcell
Cell with a physical description that does not

appear in the RTL/netlist. Examples are filler
cells, antenna cells, feedthrough cells.
pdomain
tool
Physical information for a CPF power domain.
PIN
DEF
Defines the direction, layer, location, and size of

a signal or power connection point on a
MACRO.
PITCH
LEF
Defines the distance between routing tracks in

the preferred direction for a given routing layer.
porosity
tool
Measure of unused space during initial

placement which allows for cell resizing and
new cell insertion during optimization.
process shrink
PUSHDOWN
August 2011
Technique to create a new process by optically

shrinking the geometries from an existing
process.
DEF
Type of PLACEMENT blockage created a

higher level in the hierarchy and pushed down
into the block.
70

Terminology
REGION
DEF
Defines a location (physical area) for a GROUP.

By default, all instances in the group are placed
inside the predefined location, but other
instances can also be placed in this location.
You can further constrain a region by assigning
a type: choose between FENCE and GUIDE.
Rho
capacitance
table
resistivity table based on the width and spacing

of the layer
ROW
DEF
Core rows in the core area of the design define

the legal placement locations for the standard
cells.
ShrinkFactor
capacitance
table
Factor used to model the process shrink

technique.
SOFT (placement
blockage)
DEF
Type of PLACEMENT blockage that prevents

instances from being placed in the specified
area during initial placement.
SLOTS
DEF
Defines the rectangular shapes that are cut into

wide metal wires to prevent dishing.
SPACING
LEF
Specifies the minimum spacing allowed

between wires on the same layer, or between
two via cuts on the same net or on different
nets.
SPECIALNETS
DEF
Describes the wiring of prerouted nets, such as

power and ground nets. These nets are not
touched by the automatic router.
steiner tree
An algorithm to find the shortest interconnect

for a given set of objects. Given a set V of points
(vertices), "steiner tree" interconnects them by
a network (graph) of the shortest length, where
the length is the sum of the lengths of all edges.
TRACKS
DEF
Predefined routing resources that define the

routing grid.
utilization
tool
Percentage of available placement area filled

with placed instances. High utilization can lead
to congestion. Low utilization can lead to long
wires and need for buffering.
August 2011
71

Terminology
August 2011
72
Index
A
attributes
def_file 24, 40, 61
C
capacitance table file, info used 18, 35, 55
cells
reporting cell count 25, 42
commands
read_def 22, 38, 59
read_encounter 57
synthesize -to_placed 62
write_encounter design 27, 44, 65
D
design information hierarchy 10
P
physical information
in design hierarchy
August 2011
10
73
August 2011
74

RC Phys

Caricato da

Informazioni sul documento

Titolo originale

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

RC Phys

Caricato da

Copyright:

Formati disponibili

Design with RTL Compiler Physical

Product Version 10.1

2007-2011 Cadence Design Systems, Inc. All rights reserved.

Design with RTL Compiler Physical

Using Physical Information in Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Product Version 10.1

Design with RTL Compiler Physical

Setting the Appropriate Synthesis Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Product Version 10.1

Design with RTL Compiler Physical

Using Physical Information in Synthesis on page 6

Special Files for Physical Flows on page 8

Physical Information in the Design Information Hierarchy on page 10

Product Version 10.1

Design with RTL Compiler Physical

Using Physical Information in Synthesis

Wire-load Models (WLM)

Uses actual design and physical library

Wire-load models are statistical.

Dynamically calculates wire delays for

Wire-load models are calculated based on

Correlates better with place and route.

Correlation is difficult even with custom wireload models.

Product Version 10.1

Design with RTL Compiler Physical

Product Version 10.1

Design with RTL Compiler Physical

Special Files for Physical Flows

Capacitance Table Capacitance tables contain the same type of parasitic

Product Version 10.1

Design with RTL Compiler Physical

Encounter Configuration The Encounter configuration file contains Tcl variables

Product Version 10.1

Design with RTL Compiler Physical

Physical Information in the Design Information Hierarchy

Product Version 10.1

Design with RTL Compiler Physical

The dex directory contains information for design exploration.

The libraries directory can have several subdirectories each representing a

Product Version 10.1

Design with RTL Compiler Physical

regions contain information about regions defined in the DEF file.

Product Version 10.1

Design with RTL Compiler Physical

Attributes Affecting the PLE Flow on page 15

Reading the LEF Libraries on page 16

Loading the Capacitance Information on page 18

Checking the Physical Layout Estimation Information on page 19

Setting the Appropriate Synthesis Mode on page 21

Reading the Floorplan on page 22

Analyzing the Results on page 25

Exporting Files for Place and Route on page 27

Sample Script for Simple PLE Flow on page 28

Product Version 10.1

Design with RTL Compiler Physical

Read timing libraries

Read HDL files and elaborate

Check physical layout

Change SDC constraints

Product Version 10.1

Design with RTL Compiler Physical

Attributes Affecting the PLE Flow

Product Version 10.1