Improvement in Read Performance of 10T SRAM Cell Using Body Biasing in Forward Bias Regime

IPASJ International Journal of Electronics & Communication (IIJEC)
Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm

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ISSN 2321-5984
A Publisher for Research Motivation........
Volume 4, Issue 11, November 2016
Improvement in Read Performance of 10T SRAM

Cell Using Body Biasing in Forward Bias Regime
Rajat Gupta1, Amit S. Rajput2, Nikhil Saxena3
1-3
Department of Electronics and Telecommunication Engineering

ITM Universe Gwalior- 474001, India
ABSTRACT
Stability and access time play an important role in the performance metrics of SRAM Cell. As the technology node decreases
stability of the memory cell decreases whereas access time (during read and write operation) increases in SRAM cell.
Increasing of access time leads to a slow speed of SRAM cell while decreasing of stability leads to its poor noise tolerant
capacity. This article proposes a new way for designing an SRAM cell. In this article, a 10T SRAM cell based on FBB
technique is proposed .The proposed cell achieves 36.79% improvement inTRA compared to COND10Twith same RSNM of
read decoupled SRAM cells.SRAM cells are simulated in HSPICE using the 45nm PTM file to verify our design
Keywords: Forward Body Biasing, read current, read delay, read static noise margin (RSNM)
1. INTRODUCTION:In memory circuit, there is no large increment in its speed in recent years but processor's speed is observed. Thus, a gap
between performing capability of memory and processor is widening with time. Silicon industry is embedding SRAM
on same die with processor in the form of cache memory. In order, to achieve faster cache memory, threshold voltage of
MOSFETS needs to be decreased[1]. Moreover, smaller devices cause a significant degradation in SRAM cell data
stability with the scaling of CMOS technology. The robustness of an SRAM cell is characterized by the hold stability
during a read operation. In a conventional 6T SRAM cell, the data storage nodes are directly accessed through the pass
transistors connected to the bitlines. The storage nodes are disturbed due to the voltage division between the crosscoupled inverters and the access transistors during a read operation. The data is most vulnerable to external noise
during a read operation due to this intrinsic disturbance produced by the direct data-read-access mechanism of a
standard 6T SRAM circuit (destructive read) [2][3] .Fig.1shows the butterfly curve for hold and read SNM of
conventional 6T.
(a)
(b)
Figure1 (a) Conventional 6T SRAM cell (b) Butterfly curve for read and hold SNM at 45nm @ VDD=0.7V
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Thus, an SRAM cell is required to be faster and disturb-free during read operation.
The problem of disturb free read operation for attain appropriate read stability is eliminated by many different
configuration of SRAM cells. These SRAM cells could be categorized into two types, namely single ended sensing cells
such as 8T (as shown in figure 1(a)) [4]. In single ended SRAM cells, read stability improves by providing isolate
circuit for read operation so that the contents of the latch circuit in SRAM cell does not disturb during read operation.In
general, a single-endedsensing cell is not as robust as the differential one, and hence,it often requires some extra
compensation scheme to maintainthe reliability as proposed in [5]Moreover, problem of decreased sense margin occurs
in the single ended cells[6]. Differential SRAM cells have been developed for eliminate the problem of decreased sense
margin. Z. Liu and V. Kursun have proposed a 9T bitcell with differential read disturb free operation (as shown in
fig 1 (b)) [7]. Differential 9T SRAM bitcell suffers from penalty of large body effect offered by the read buffer, this
effect results in reduction in its drive strengthand it takes longer time to discharge bitline [8]. Fig.1(c) is referred to as
P-P-N Based 10T SRAM Cell [9]. This type of cell still suffers with a minor problem of read disturbance and its read
access time is closely to the conventional 6T bitcell. A differential 10T bitcell which provides read-disturb free
operation has also been reported[10][11]. Read access time of this cell is closely to that of conventional 6T because this
cell also uses two NMOS transistors for read current path during read operation. These cells show improvement in read
stability at penalty of poor read performance. In this article, a differential 10T SRAM cell based on FBB (Forward body
biasing) is proposed. Proposed cell provides significantly improvements in read delay and read current for high read
performance as compared to other cells and maintain its read stability same as read decoupled cells (8T,9T,Differential
10T).
The remainder of the paper proceeds as follows. In section 2, brief discussion of body biasing in forward bias regime is
described. Section 3 presents the proposed design. In section 4, the simulation results and discussion are presented.
Finally section V concludes this paper.
(a)
(b)
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ISSN 2321-5984
(c)
Figure 2(a) Single Ended SRAM cell[4]. (b), (c) Differential SRAM cells[7][9].
2. BODY BIASING IN FORWARD BIAS REGIME

In this technique, threshold voltage of MOSFET decreases as body to source forward biases[12]. Lower threshold
MOSFET results in higher drain current as compared to zero substrate MOSFET. Furthermore, in the active mode, a
slightly forward substrate bias can be used to increase the circuit speed while reducing SCEs [13].
Device
NMOS
No Body Biasing
(Zero substrate bias) (Z.B)
Vb=Vss
Forward Body Biasing
Reverse Body Biasing
Vb>Vss
Vb<Vss
The equation provided below explains the reason behind the variations in the threshold voltage and thereby drain
current.
Vt = Vt0 + ( s + VSB s )
(1)
where Vt0 is the threshold voltage at zero substrate bias; VSB is the source to body bias; sis the surface potential;
(tox /ox) 2q si N A is the body effect coefficient where tox is oxide thickness; ox is permittivity of oxide, si is the
permittivity of silicon, NA is the doping concentration; q is the charge of an electron[14].
3.PROPOSEDFBB D10T SRAM CELL

This paper proposes a differential 10T SRAM cell with FBB. This cell is identical to conventional differential 10T
(CON D10T) SRAM cell. The proposed design does not require much architectural changes compared to CON D10T .
The only change that is required the routing of interconnects for body biasing of NMOSFETS during read operation. If
the cell content is 1, threshold voltage of both respective MOSFETS (MN5/7 or MN6/8) is decreased during read
operation, thereby enhancing read current and the proposed cell provides higher read performance.
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FFigure 3 Conventional differential 10T
Figure 4FBB differential 10T
A fair comparison of the proposed design with its conventional is made by maintaining the same sizes of the FETs in
both the designs. The width of the FETs used in the design (for 45-nm technology) are 45 nm for MN1/2/3/4/5/6/7/8,45
nm for MP3/6 and the length of all the MOSFETs is 45 nm, the minimum value allowed in the 45-nm technology
node.
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Figure 5Cell status during read operation
4.SIMULATION AND RESULTS:This section presents simulation results and comparison in 45nm technologyTable 1-Standard Parameter Used for Simulation in HSPICE with respect to Nominal VDD=0.7V
Channel Length (L)
45nm
ThresholdVoltage
(Vt)
Channel doping
Concentration
(NDEP)
Oxide thickness (tox)
Vtn
Vtp
NDEPN
NDEPP
0.427V
-0.375V
2.84E+18
2.13E+18
1.1nm
4.1Read CurrentRead current (I read) is the current flowing through the read access transistor of SRAM cell during read operation.
However, in the proposed design, high cell content forward biases the body of respective MOSFETs (MN5/7 or MN6/8)
during read operationwhich reduces the threshold voltage of the respective MOSFETs and thereby decreasing the
resistance of read path which results in higher read current as compared to CON D10T. A significant improvement of
Iread is observed in FBB D10T as compared to CON D10T as evident from the Table-2 and the Figure-4.From the
table2 it can be observed that FBB based D10T SRAM cell shows 36.44% increment in read current as compared to
CON D10T SRAM cell when VDD is kept at 0.7volt.
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Figure 4 Read Current vs Supply Voltage

Table 2. Iread Comparison with Power Supply Variation at 45nm Technology
Cell
CON
D10T
Cell
VDD
(Volt)
Iread(Amp)
(u= E-6)
0.5
3.6495E-6
0.7
1.32036E5
2.92862E5
FBB D10T
0.5
8.2082E-6
0.7
2.07742E5
3.58782E5
4.2 Read Access TimeThe TRA (read access time or read delay) for differential SRAM cell is estimated from the time when RWL is initiated
to the time when RBL/RBLB is discharged by 50mV from its initial high level. A 50 mV difference between (RBL)
and (RBLB) is acceptable to trigger the sense amplifier correctly, thereby avoiding misread while accessing the cell in
read mode. For a single ended SRAM cell (SE8T),TRAis estimated as time taken byRBL to drop the voltage by 75%
from its initial high value to avoid misread [1]. From the Figure 5 it can be observed that there is an improvement in
read delay with FBB based D10T SRAM cell as compared to CON D10T SRAM cell. This improvement is achieved
because during read operation in FBB based D10T SRAM cell, bitcell read current (Iread) increases which often results
from an decrease in Vth for respective MOSFETS during read operation as compared to CON D10T SRAM cell. Thus
precharged to VDD bitline discharges fast through MN5/7 or MN6/8 in FBB based D10T SRAM cell as compared to
CON D10T SRAM cell to a voltage differential value (50mv) which can trigger the sense amplier correctly. The
analyzed results are reported in Table 3. From the table 3 it can be observed that FBB based D10T SRAM cell shows
36.79% improvement in read delay as compared to CON D10T SRAM cell when VDD is kept at 0.7 volt
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Figure 5. Read Delay vs Supply Voltage

Table 3. Read delay comparison with Power Supply Variation at 45nm Technology
Cell
CON
D10T
Cell
VDD
(Volt)
Read
Delay (TRA)
(sec)
0.5
1.4369E11
0.7
3.6876E12
1.4476E12
FBB D10T
0.5
6.6267E12
0.7
2.3307E12
2.7953E13
4.3 Read Static Noise MarginRead static noise margin determines the read stability. In this paper, Butterfly curve method is used to calculate the
read SNM of the proposed cell. During read operation, voltage transfer curve is plotted for the one inverter then inverse
VTC is Plotted for the other. This plotting of two VTCS gives the butterfly curve. Side length of the largest square that
can be inscribed inside the comparatively smaller lobe of butterfly curve is the measurement of Read SNM [7]. The read
static noise margin of the proposed FBB D10T SRAM cell and CON10T is equal to its hold SNM because both the cells
are read decoupled
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Figure 6 Static VTCs during read operation

Table 4. Speed, read current, read static noise margin comparison at VDD=0.7V.
SRAM
cell
Propose
d
differential
10T SRAM
cell
Read
Access
Time(TRA)(se
c)
2.3307E-12
Read
Current (Iread)
(Amp)
RSNM(m
v)
20.7742E-6
223mv
Differen
tial
10T
SRAM cell
3.6876E-12
13.2036E-6
223mv
CON 9T
1.3699E-11
13.2036E-6
223mv
PPN
based 10T
3.3567E-12
13.2031E-6
222mv
Single
ended 8T
5.3725E-11
13.2036E-6
223mv
3.2266E-12
25.5109E-6
74mv
CON 6T
5. CONCLUSIONThis study proposes a Forward Body Biasing based differential 10T SRAM cell. This analysis has shown that
significant improvement in read delay as compared to conventional cells at low power supply such as 0.7V. The
proposed cell also exhibits higher read current.Read stability of the proposed cell is same as conventional 10T because
both cells are read decoupled. The proposed SRAM cell therefore, is an attractive option or useful where high speed
and high stability are major concern.
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References
[1]. S. Pal and A. Islam, Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Application, IEEE
Trans. Comput. Des. Integr. Circuits Syst., vol. 0070, pp. 110, 2015.
[2]. S. A. Tawfik and V. Kursun, Low Power and Robust 7T Dual-Vt SRAM Circuit,In IEEE, pp. 14521455,2008.
[3]. Z. Liu and V. Kursun,High Read Stability and Low Leakage Cache Memory Cell,Proceedings of the IEEE
International Symposium on Circuits and Systems, pp. 2774-2777, 2007.
[4]. L. Chang, D. Fried, J. Hergenrother, J. Sleight, R. Dennard, R. R. Mon-toye, L. Sekaric, S. McNab, W. Topol, C.
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[5]. N. Verma and A. P. Chandrakasan, 65 nm 8T sub-Vt SRAM employing sense-amplier redundancy,In Proc. Int.
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[6]. I. J. Chang, J. Kim, S. P. Park, and K. Roy, A 32 kb 10T subthreshold SRAM array with bit-interleaving and
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Author
Nikhil Saxenareceived his B.E. degree in Electronics and Communication Engineering from Institute of
information Technology and Management, Gwalior in 2010 and received his M.Tech degree in microelectronics
and Embedded Technology from J.P institute of Information and Technology, Noida (U.P) in 2013. His
Research interest is design of ultralow-power nanoscale circuits for portable/wearable/energy-harvesting
applications.
Amit Singh Rajput received his B.E.degree in Electronics Engineering from jawaharlal institute of
technology, khargone (M.P), India in 2001 and M.Tech in VLSI design From Nirma University Ahmadabad in
2006. His research interests are low power VLSI design, process invariant SRAM circuit, analog and digital
integrated circuit design.
Rajat Gupta received the B.E degree in Electronics and Telecommunication Engineering in the year 2012from M.P.C.T, Gwalior,
India. He is currently doing M.Tech degree in (VLSI Design) from ITM Universe, Gwalior, India. His research interests are digital
logic design for ultra-low voltage and high stability
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IPASJ International Journal of Electronics & Communication (IIJEC)

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm

A Publisher for Research Motivation........

Volume 4, Issue 11, November 2016