TSPCR Logic

Inductive parasitic
Barrel shifter
Ratioed Logic
Semi-custom design flow
Limits of scaling
How does power density and Vi scales for fixed voltage scaling and full
scaling.
Switching threshold voltage of a Symmetrical CMOS inverter.
Design abstraction level in the digital circuits.
Explain the source of power consumption (static and dynamic )of CMOS inverter.
Write the drain current equation for P channel MOS transistor of 3
region of operation.
Write the drain current equation for N channel MOS transistor of 3
region of operation.
If 4 pMOS transistor and cascaded source to gate find the output voltage from 4th
pass transistor is tied to 0V assume Vip=-1V.
Sources of clock skew and Jitter.
Graphically obtain the VTC of CMOS inverter where Vdd=2V consider
Vgs= 0,0.4,0.8,0,1.6,2V.
Standard cell based design
Zipper CMOS circuit
Race around condition with waveform.
Pass transistor and transmission gate and their difference

Compute the threshold voltage for Vsb =-2.5V 2(phi)f= 0.6, for PMOS
transistor having threshold of -0.4V given body effect constant of 0.4.
Discuss in detail NORA CMOS logic design style, discuss its advantages
over domino CMOS logic gate
Explain the system integrity issues in dynamic CMOS design.
Explain the standard compile cell and discuss the difference between
macro and mega cells.
Discuss the impact of positive and negative clock skew on the
performance of sequential circuits.
How negative skew avoids races and hampers of the circuit
performance.
Draw and explain the energy band gap of MOS transistor in accumulation
depletion and inversion region.
Problem of cascading of dynamic gates explain ways to solve it
Explain concept of pulse register, draw the circuit diagram and explain
the concept of glitch generation
Pipe-lining approach to optimize the sequential circuits, expression for
minimum allowable clock period for pipe-lining circuit
Design techniques to reduce the delay for large fan in circuits
Elmore delay model
Various methods of scaling of MOS
Domino Logic circuits, Draw Domino circuit for 4:1 mux, 4 bit CLA adder

Switching translation probability and its calculation for XOR Gate.

Explain PLA, PAL and FPGA
Explain meta stability in sequential circuits
Draw CMOS positive edge triggered master slave flip flop
Dual rail circuit for OR/NOR gate

Various problem in Dynamic circuits and their resolution

Draw IV characteristics of P-MOS including channel length modulation
Relationship between mask channel length and electrical length
L=Lm-2Ld where Ld is lateral diffusion length
Draw N-MOS equivalent circuit, explain variation of channel capacitance
as a function of drain source voltage for different operating modes