Analog IC Design

Chapter 6. Operational Amplifiers

Outline
6.1. Generalities
6.2. Power-Supply Rejection
6.3. Output Stages
6.4. Two-Stage Class-A Transconductor
6.5. Class-AB Amplifiers
6.6. Current-Mode Amplifiers

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Analog IC Design

6.1. Generalities: A. Characteristics Ideal Op Amp

Symbol:

vO = (vP vN)AV vIDAV

Null Ports:

High ZIN

Low VOFFSET

Low ZO

High SR dvO/dt

High AV

High iO(MAX)

High fBW

High ICMR

Low PVDD/VSS

High vO(MAX)

Low Cost

Wide Temperature Range

High SNR

Low Headroom

Headroom Min{vDD vSS}

High-Input Impedance ZIN iP iN 0.

Virtual Short Series-mixed negative feedback virtually shorts input terminals.

Actual Op Amp
Differential- and common-mode response:
"v +v %
v O = ( v P v N ) A V + $ P N ' A C v ID A D + v IC A C
# 2 &

Differential-mode frequency response:

z1, are zeros.

"
s %
A V0 $1+
'...
A V0 2p1 2p 2 ... s + 2z1 ...
# 2z1 &
AV =
=
"
%
"
%
2z1... s + 2p1 s + 2p 2 ...
s
s
$1+
'$1+
'...
2p
2p
#
1 &#
2&
p1, p2, are poles.

(
)(

)
)

Insightful format because AV = AV0 at low frequency when s = 0.

One dominant low-frequency bandwidth-setting pole.
All other poles are at or above f0dB.
f0dB = GBW = AV0pBW OL.

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Analog IC Design

v PSRR+ =

v dd A VDD
v dd
=
AD
PSRR +

v PSRR =

v ss A VSS
v ss
=
AD
PSRR

v CMRR =

v ic A C
v ic
=
AD
CMRR

RO = Output resistance

IOS* = Input-referred offset current (IBP IBN)

RID = Differential input resistance

VOS* = Input-referred offset voltage

CID = Differential input capacitance

vN* = Input-referred noise voltage

RIC = Common-mode input resistance

iN* = Input-referred noise current

CIC = Common-mode input capacitance PSRR = Power-Supply Rejection Ratio

IBP and IBN = Input bias currents

CMRR = Common-Mode Rejection Ratio

B. Composition
Differential Input Stage:
Buffer differential input signals High input impedance.
Convert differential input to ground-referenced signal (although not always).
Gain Stage: Amplify signals.
Output Buffer: Drive heavy loads Low output impedance.
Compensation: Stabilize circuit when looped with negative feedback.
Bias: Establish bias currents and voltages.

Design Strategy:
Translate
Voltages to Currents
Currents to Currents
Currents to Voltages
Voltages to Voltages

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Analog IC Design

Internal Components

Loads
Gain Stages

Bias Circuits

Using N- and P-type MOSFETs and BJTs.

6.2. Power-Supply Rejection

Power-supply rejection ratio PSRR is a measure of
how much a circuit favors input signals over supply ripples.
Ratio of forward gain
to supplyoutput gain.
PSRR +/

AV

v dd/ss =0

A VDD/VSS

v id =0

Negative feedback opposes the effects of supply noise Suppresses Noise.

vo = (0 vo)AV + vdd/ssAVDD/VSS
vo =

v dd/ss A VDD/VSS v dd/ss A VDD/VSS

v dd/ss

=
1+ A V
AV
PSRR +/

As long as AV > 1 Up to f0dB.

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Analog IC Design

A. Power-Supply Gain
Voltage-Divider Model: Model what connects to the output vO.
Output transistors MT and MB
couple (voltage-divide) supply noise.
High supply impedances
limit supply noise.
Output transconductors igmt and igmb
inject supply noise.
Grounded loads ZLOAD shunt output noise.
Shunt feedback shunts output noise with
ZSHUNT =

Z OL
Z OL
1
1

A OL FB A G.OL Z OL FB A G.OL FB G LG

B. Feed-Through Noise: i. In Mirrors

Current mirrors convert supply noise voltage vac to noise current iac.
Supply impedance ZO limits noise current iac.
Current mirrors reproduce noise current iac.

High supply impedance limits noise current iac iIN's ZO should be high.

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Analog IC Design

ii. From Differential Stages

P-type mirrors
into balanced loads:
Reproduce positivesupply noise vdd.
Cancel negativesupply noise vss.
N-type mirrors
into balanced loads:
Cancel positivesupply noise vdd.
Reproduce negativesupply noise vss.

iii. In Power Transistors

Common-Mode Concept:
MOS iD (|vG vS| |vT|)2

and

BJT iC exp(|vB vE|/Vt).

Noise that is common to gate/base and source/emitter terminals cancels.

Possible Output Terminals:
Source/emitter: Voltage followers reproduce gate noise.
Remove gate noise.

Drain/collector: Unmatched gatesource noise in CS/CE transconductors

produces noise current Reproduce supply noise in gate.
Eliminate feed-through noise from output transistors with:
Balanced mirror-gain stages and coupling common-mode capacitors.

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Analog IC Design

6.3. Output Stages: A. Class A, i. Follower

Class-A Transistor: Always conducts current Considerable power.
Conducts across 360 of a sinusoid: Conduction angle is 360.
iC/D, gm, and gain > 0 across vO's swing vO is linear.
Class-A Stage: A current source biases a Class-A transistor.

Class-A NMOS Follower

vO = vIN vGS1 = vIN vTN1 VDS1(SAT).

vIN(MAX) and vGS (i.e., IQ2 and RL) limit vO(MAX).
VDS2(SAT) or RL limits vO(MIN).
iO 0.5KN'S1[(vIN vO) vTN1]2 IQ2.
vIN(MAX), vO, and IQ2 limit iO(MAX)+.
Bias IQ2 limits iO(MAX).
Bulk effect raises vTN1 Reduces vO(MAX) and iO(MAX)+.

Example: vIN(MAX) = vDD = vSS = 2.5 V, KN' = 150 A/V2, N = 0,

VTN0 = 0.7 V, (W/L)1 = 300, (W/L)2 = 150, IQ2 = 1 mA, and RL = 1.5 k.
Solution: vO(MAX) = iO(MAX)+(1.5k) = 1.5 V and VDS2(SAT) 300 mV.

vO(MIN) = Max{2.5 + 300m, (1m)(1.5k)} = 1.5 V

iO(MAX) = 1 mA when vIN shuts M1.

vO(MAX)

iO(MAX) 0.5(150)(300){[2.5 iO(MAX)+(1.5k)] 0.7}2 1m 1 mA

+

Power-Supply Rejection
MT's igmt reproduces gate noise vdd or vss in vO.
MB's igmb mirrors RBIAS's noise vss/RBIAS and vdd/RBIAS.
MT's 1/gmT shunts MB's noise in igmb and
MT's and MB's rds noise contributions.
vo

1
v dd/ssg mT rdsB v dd
v
v dd
v ss
+
+ ss +
+

v dd/ss
1+ g mT rdsB R BIAS R BIAS rdsT +1/g mT rdsB +1/g mT g mT

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Analog IC Design

Power Efficiency
For maximum power efficiency (i.e., long operational life), reduce power losses
Low vDS(AVG) For sinusoids, vO(PEAK)'s swing close to the supplies vDD and |vSS|.
Ideal Maximum-Efficiency MAX Waveforms:
When vDD = |vSS|, vO(MAX) |vO(MIN)| vDD.
vDS1(MIN) 0, vDS1(MAX) vDD vSS = 2vDD.
At vO(MIN) and vDS1(MAX), iD1 can near zero.
For a symmetrical vO, iO(MAX)+ iO(MAX) = IQ.
iD1(MAX) 2IQ at vO(MAX) and vDS1(MIN).
PM1 = vDS1iD1 = [vDD(1 + sint)] [IQ(1 sint)]
= vDDIQ(1 sin2t) PM1(MAX) = vDDIQ at Q point.
Fraction of PSUPPLIES delivered:
Maximum Possible
v R(PK) i R(PK)

v R(RMS)i R(RMS)
v R(PK)i R(PK)
v I
PO
2 2
=
=
=
=
< DD Q = 25%
PSUPPLIES ( v DD v SS ) i DD(AVG)
(v DD v SS ) IQ 2 (v DD v SS ) IQ 4v DDIQ

Maximum efficiency when

iD vs vDS with Parabolas of Constant Power

vDS(AVG) is lowest: vDS(MAX) = 2vDD.

Drive is symmetrical: iD(MAX) = 2IQ.
When designed for maximum
efficiency, PM1(MAX)
is at Q point.
Load-line slope is 1/RL.
Pivots about Q point with RL.
With higher RL: vO bottoms to vSS before iD1 is zero iD1 0 at 2vDD Higher PM1.
With lower RL: M1's 2IQ does not raise vO to vDD vDS1 0 at 2IQ Higher PM1.

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Analog IC Design

Design Example

Objective:
Select RL for maximum efficiency
when vTN 0.5 V, VDS(SAT) = 0.2 V,
vIN(MAX) vDD = vSS = 5 V, and IQ2 = 2 mA.
Solution:

vO(MAX) vDD vGS1 = 4.3 V

(2IQ2 IQ2)RL = IQ2RL
RL 4.3 V/2 mA = 2.15 k

Efficiency =

PO

PSUPPLIES

v R(PK)
4.3m
1 4.3
=
= = 21.5%
20m 2 ( v DD v SS ) 4 5

!v
$! I $ (4.3)(2m)
PO = v R(RMS)i R(RMS) = # R(PK) &# Q2 & =
= 4.3 mW
2
" 2 %" 2 %
PSUPPLIES = ( v DD v SS ) i DD(AVG) = (2v DD )IQ2 = (10)2m = 20 mW

Ideally: PO(MAX) at vO(MAX) vDD is 5 mW Efficiency 5m/20m = 25%.

ii. Transconductor

VDS1(SAT), VSD2(SAT), and RL limit vO(MAX).

vGS does not limit vO(MAX).

Class-A

iO IQ2 0.5KN'S1(vIN vSS vTN1)2.

NMOS

Bias IQ2 limits iO(MAX)+.

CS Stage

vIN(MAX) and IQ2 limit iO(MAX).

Example: vIN(MAX) vDD = vSS = 2.5 V, KN' = 150 A/V2, KP' = 50 A/V2, N = 0.5,
VTN0 = 0.7 V, (W/L)1 = 300, (W/L)2 = 150, IQ2 = 1 mA, and RL = 1.5 k.
Solution:

iO(MAX)+ = 1 mA when vIN shuts M1.

iO(MAX) = |vO(MIN)|/1.5k = 1.45 mA
VSD2(SAT) = 0.27 V vO(MAX) = Min{2.5 0.27, (1m)(1.5k)} = 1.5 V
v O(MIN) = 2.5 +

" v O(MIN)
%
2
$$
+1m '' 2.17 V
(150)(300) # 1.5k
&

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Analog IC Design

Design Example

Objective:
Select RL for maximum efficiency
when vTN = 0.5 V, VDS(SAT) = 0.2 V,
vIN(MAX) vDD = vSS = 5 V, and IQ2 = 2 mA.
Solution:

vO(MIN) vSS + VDS(SAT) = 4.8 V

(IQ2 2IQ2)RL = IQ2RL
RL 4.8 V/2 mA = 2.4 k

Efficiency =

v R(PK)
PO
4.8m
1 4.8
=
=
=
= 24%
PSUPPLIES 20m 2 ( v DD v SS ) 4 5

!v
$! I $ (4.8)(2m)
PO = v R(RMS)i R(RMS) = # R(PK) &# Q2 & =
= 4.8 mW
2
" 2 %" 2 %
PSUPPLIES = ( v DD v SS ) i DD(AVG) = (2v DD )IQ2 = (10)2m = 20 mW

Class-A CS/CE efficiency is closer to 25% than that of a Class-A Follower.

Power-Supply Rejection
When driven by a P-type mirror, MT's vg vdd and igmt 0.
MB's igmb mirrors RBIAS's noise vss/RBIAS and vdd/RBIAS.
MT's rdsT and MB's rdsB voltage-divide supply noise.
v
v
v r
v r
v o dd + ss ( rdsB || rdsT ) + dd dsB + ss dsT
rdsT + rdsB rdsT + rdsB
R BIAS R BIAS

Distortion
Characterized by influence on a pure sinusoid vin = VPsin(t).
Output with distortion: vo = a1VPsin(t) + a2VPsin(2t) + + aNVPsin(Nt)
Harmonic Distortion: Harmonic-to-fundamental signal-strength ratio: HDi |ai|/|a1|
Total Harmonic Distortion: Combined squareroot contributions:
THD

Small signals are linear.

Large signals and square law for FETs and exponential for BJTs.

a 2 + a 3 +... + a N
a1
2

iD/C in gm and gain vary with vO Gain variation produces nonlinearity.

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Analog IC Design

In BJT
vIN = VBE + vin

(
(
"V %
" v %+
"v % +
v O = R L ( I Q i C ) = R L *I Q I S exp $ BE ' exp $ in '- = R L I Q *exp $ in ' 1# Vt &
# Vt &,
# Vt & ,
)
)

Taylor-Series Expansion: Exp (x) = 1 + x + x2/2! + x3/3! +

2
3
(" %
+
1"v % 1"v %
v
v O = R L I Q *$ in ' + $ in ' + $ in ' +...- a 1v in + a 2 v in 2 + a 3 v in 3 +...
*)# Vt & 2 # Vt & 6 # Vt &
-,

Where

a1 =

R L IQ
Vt

a2 =

R L IQ
2Vt

a3 =

R L IQ
6Vt

vin = VPsin(t) vO = a1VPsin(t) + a2VP2sin2(t) + a3VP3sin3(t) +

Or

v O = a 1VP sin (t ) +

a 3 VP 3 #
a 2 VP 2 #
$1 cos ( 2t )%& +
$3sin (t ) sin (3t )%& +...
2
4

" a V 2 %" 1 % V
HD 2 $ 2 P '$
'= P
# 2 &# a1VP & 4Vt

" a V 3 % " 1 % 1 " V %2

HD 3 $ 3 P '$
'= $ P '
# 4 &# a1VP & 24 # Vt &

Example: If VP = 0.5Vt HD2 = 12.5% and HD3 1%.

Example
Class-A CE NPN with vO(PEAK) = 0.6 V, RL = 1 k, and IQ = 1.86 mA:
AV gm1RL = 70.6 vIN(PEAK) vO(PEAK)/AV = 0.6/70.6 = 8.5 mV
HD2 = VP/4Vt = 8.5m/4(26m) = 8.2% Significant.
HD3 = VP2/24Vt2 = (8.5m)2/24(26m)2 = 0.45% Less significant.
Origin of distortion: Gain variation across vO's swing.

0.6

1.86m
iC(MIN)
IQ i R(PK)
1k (1k) = 49
AV v
=
R L =
R L =
O(MAX)
Vt
26m
Vt

0.6

1.86m +
iC(MAX)
IQ + i R(PK)
1k (1k) = 95
AV v
=
R L =
R L =
O(MIN)
V
V
26m

t
t

The gain of the follower varies less (i.e., is more linear) because
inherent negative feedback suppresses gain sensitivity.

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Analog IC Design

B. Class B/AB
Class-B Transistor: Conducts half the sinusoid cycle Conduction angle is 180.
Less conduction than Class A More power efficient than A.
iC/D, gm, and gain = 0 when vO crosses zero Less linear than A.
Class-AB Transistor: Conducts more than half, but less than a full cycle.
Conduction angle is between 180 and 360.
Less conduction than Class A More efficient, but less linear than A.
More conduction than Class B Less efficient than B.
iC/D, gm, and gain > 0 when vO crosses zero More linear than B.
Class-B/AB Stage: Two Class-B/AB pushpull transistors.
One transistor conducts when the other does not.

i. Followers
vIN, vGS1 and vSG2 (and RL) limit vO(MAX).
vIN and vO limit gate drive Limit iO(MAX).
IQ does not limit iO(MAX).
Bulk effect reduces vO(MAX) and iO(MAX).
M1 and M2 conduct less than the full cycle More efficient than Class A.
Maximum possible power efficiency with lowest vDS When vR(PK) vDD.

v R(RMS)i R(RMS)
PO
=
PSUPPLIES v DDi DD(AVG) + v SS i SS(AVG)

%
"v
%" v
Maximum Possible
$$ R(PK) ''$ R(PK) '
$
'
v R(PK) v DD
# 2 &# R L 2 &
=
=
<
= 78.5%
"v
%
"v
% 2 2v
4v DD
DD
v DD $$ R(PK) '' + v SS $$ R(PK) ''
# R L &
# R L &

Each transistor conducts half the cycle from each supply.

With symmetrical supplies vDD = |vSS|.

Page 12

E.g.: If vDD = 5 V
and vR(PK) = 4 V,
62.8%.

Analog IC Design

Distortion
iD1 and iD2 rise with a higher gategate bias voltage.
Higher vG1 vG2 Higher gate drive vGS1 + vGS2.
iL, iC/D, and gm fall to minimum when vO crosses zero.
Produces cross-over distortion.

Class AB

Class B

M1 and M2 are off.

M1 and M2 are on.

Cross-over distortion when iD12 = 0.

Followers are linear because iD 0.
Each transistor conducts 180.

iD12 0 Less cross-over distortion.

Followers are linear because iD 0.
Each transistor conducts > 180.

Shorted-Gates Class-B Example

M1 and M2:
PushPull Output
Shorted Gates:
Class-B Battery

Gategate bias voltage is zero iD1 = iD2 = 0 when vO is zero.

M1 and M2 shut when vIN is within vTN and |vTP| of 0 V.
Class-B operation Considerable cross-over distortion.
vO(MAX) = vIN(MAX) vGS1 = vIN(MAX) vTN VDS1(SAT)
vO(MIN) = vIN(MIN) + vSG2 = vIN(MIN) + |vTP| + VSD2(SAT)

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Analog IC Design

Diode-Stack Class-B/AB Example: "Diamond" Driver

M1 and M2: PushPull Output
IQM7M6: Bias Current
+
VBAT

M4M5 Diode Stack: Class-B/AB Battery

M3: CS Amplifying Driver
vGS loop sets iD1 and iD2 from:
vGS5 + vSG4 = Constant VBAT = f(IQ)
VSD4(SAT) + VDS5(SAT) = VSD2(SAT) + VDS1(SAT)

Operation:

When M2 sinks iL, vSG2 is higher VBAT reduces vGS1 to set iD1.
When M1 supplies iL, vGS1 is higher VBAT reduces vSG2 to set iD2.
When vO is zero, iD1 = iD2 and VBAT sets iD12.
If VBAT is low, iD12 = 0 when vO = 0 Class B.
If VBAT is high, iD12 > 0 when vO = 0 Class AB.

ii. Transconductors
VDS1(SAT) and VSD2(SAT) (and RL) limit vO(MAX).
vGS does not limit vO(MAX).
vIN limits gate drive Limits iO(MAX).
vO and IQ do not limit iO(MAX).
vDS(MIN) of CS < vDS(MIN) of Follower More efficient than ABB followers.
Example: If vDD = vSS = 5 V and vR(PK) = 4.8 V.

4.8
PO
v
= R(PK) = 75.4% Closer to 78.5%.
PSUPPLIES 2 v DD v SS 4 5

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Analog IC Design

Distortion
iD1 and iD2 rise with a lower gategate bias voltage.
Lower vG2 vG1 Higher gate drives |vGS's|.
iL, iC/D, and gm fall to minimum when vO crosses zero.
Produces cross-over distortion.

Class B

Class AB

M1 and M2are off.

M1 and M2 are on.

Cross-over distortion when iD12 = 0.

Transconductors produce gain distortion.
Each transistor conducts 180.

iD12 0 Less cross-over distortion.

Transconductors produce gain distortion.
Each transistor conducts > 180.

Shorted-Gates Class-AB Example

M1 and M2:
PushPull Output
Shorted Gates:
Class-AB Battery
Gategate bias voltage is zero:
Gate drives peak when vO transitions Shoot-through current can be excessive.
Too lossy for many analog applications.
M1 and M2 shut when vIN is within |vTP| and vTN of vDD and vSS.
vO(MAX) = vDD and vO(MIN) = vSS with capacitive loads Wide swing.
Useful as digital inverter.

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Analog IC Design

Diode-Stack Example
MPOMNO: PushPull Output
MPPMNP: Push Bias

Operation:
MNN and MPP voltage-buffer vIN.

MNNMPN: Pull Bias

MPN and MNP current-buffer iNN and iPP.

MNMMNO and MPMMPO mirror iNN and iPP.
Bias:
+
VBAT

iNO and iPO rise with iNN and iPP.

iNN and iPP rise with gategate voltage VGN VGP.
iNO pulls current when vIN > vTN + |vTP| + VGP.
iPO supplies current when vIN < VGN vTN |vTP|.
Class AB: iNO = iPO > 0 when vO crosses zero.
If VBAT VGN VGP > 2vTN + 2|vTP|.

Min{vDD vSS} > 4|vGS| + 2VDS(SAT)

Class B: iNO = iPO = 0 when vO = 0 otherwise.

Adaptive-Stack Example
Operation: MNIN amplifies and drives vIN.

MPOMNO: PushPull Output

MNBMPG: B/AB Bias

When vIN is low iNIN is low.

IPI raises vGNO MNO pulls iRL.

pG+

MNB shuts and MPB current-buffers IPI.

VGP, VSGPB, and IPI bias MPO to IPO(MIN).
When vIN is high iNIN is high.
MNB carries IPI and MPB shuts.

pG

iNIN lowers vGPO MPO supplies iRL.

VGN, VGSNB, and IPI bias MNO to INO(MIN).

Min{vDD vSS} > 2|vGS| + VDS(SAT)

Bias: VGN and MNB bias MNO and VGP and MPB bias MPO.
Class AB: iNO = iPO > 0 when vO = 0 if VGN > vSS + 2vTN and VGP < vDD 2|vTP|.
Class B: iNO = iPO = 0 when vO = 0 otherwise.

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Analog IC Design

C. Summary
Conduction Angle: Class A's > AB's > B's.
vGS/BE limits followers' vO(MAX) and VDS(SAT)/CE(MIN) limits transconductors' vO(MAX).
vO limits gate drive in followers, but not in transconductors.
More efficient when transistors conduct less B > AB > A.
More efficient when vDS/CE is low CS/CE > Followers.
1
= 25%
4
More linear when current and gain vary less

Maximum Efficiency:

A <

HDA < HDAB < HDB

and

B <

= 78.5%
4

HDFollowers < HDCS/CE.

More cross-over distortion when vO crosses zero if current is zero

Substantial in B.

Less in AB.

Little in A.

More current when gate/base drive is high iCS/CE(MAX) > iFollowers(MAX).

6.4. Two-Stage Class-A Transconductor

Process differential input:

Combine and amplify signals:

Differential Pair M1M2

Pair into mirror load M3M4.

Amplify and drive load:
Class-A CS transconductor MA.
Bias:
Reference circuit generates IBIAS.
MB, MT, and MB2 mirror IBIAS.
Input and feedback
set VN, VP, and VO.
Compensation:
Miller CC splits pGA and pO.

Design Feature:

vSD3 = vSG3 vSD4 = vSGA and vDS1 vDS2 when vSG3 vSGA.
Systemic input-referred offset VOS(S) is practically nil.

Page 17

Analog IC Design

A. Static Parameters
Bias Currents (where Si Wi/Li):
IT = IBIAS(ST/SB)
IA = IBIAS(SB2/SB)
With negative Feedback, vN vP.
I13 I24 0.5IT.
To match VSD3(SAT) and VSDA(SAT),
I13/S3 should match IA/SA.
Limits:

vO(MAX) = vDD VSDA (SAT)

vIC(MAX) = vDD vSG3 VDS1(SAT) + vGS1

vO(MIN) = vSS + VDSB2(SAT)

= vDD |vTP| VSD3(SAT) + vTN

iO(MAX)+ = 0.5KP'SA(vSGA(MAX) |vTP|)2 IB2

Drive: vSGA(MAX) = vDD (vIC(MAX) vTN2)

vIC(MIN) = vSS + VDST(SAT) + vGS1

= vSS + VDST(SAT) + vTN + VDS1(SAT)

iO(MAX) = IB2 = IBIAS(SB2/SB)

B. Slew Rate
Slew-Rate Limit Maximum possible dvO/dt.
Largest C's limit circuit to dvC/dt iC/C Consider largest C's CC and CL.
IT
iA+
IT

IT

SR

IT

iL

IT

iL
IB2

SR+
IB2

Slew-Rate Scenarios: CC by i2 or i4

SRC = IT/CC

CL by iA i2 IB2 SRL+ = (iA IT IB2)/CL

CL by IB2 i4

SRL

= (IB2 IT)/CL

Design usually
ensures:
iA+ >> IB2 >> IT.

vo/vgA is high Large vO's result from small vGA's: vGA 0 SRC SRO.
Worst-Case SRO: SRO+ = Min{SRC+, SRL+} IT/CC, SRO = Min{SRC, SRL} IT/CC.

Page 18

Analog IC Design

C. Offset and Electronic Noise

Systemic Offset VOS(S): Design ensures vDS1 vDS2 and vSD3 vSD4 VOS(S) 0.
Random Offset VOS* results from mismatched transistors.
Differential pair M1M2's v12 appears across input vID.
Load mirror M3M4's i34 offsets i12.
Diode connections M3MA's v3A alters vGA, except gain GDRD2 divides it.
Bias mirror MTMB2's iTB2 offsets i3A, except gain gmAGDRD2 divides it.
2

2
2
2
2

i i
i i
i3A
i TBA
*
VOS = 12 + 34 +
+
12 + 34
g m1 g m1 g mAg m1 ( rds2 ||rds4 ) g mAg m1 ( rds2 ||rds4 )
g m1 g m1

Electronic Noise vN*: Gain gmAGDRD2 suppresses iAB2* i1234* and gm12 set noise vN*.
vN

2
2
2
2
*
*

i *
i*
i *
i*
iA
i BA
3
1
= 2 12 + 2 34 +

2
+
+
2

g m1
g m1
g m1 g mAg m1 ( rds2 ||rds4 ) g mAg m1 ( rds2 ||rds4 )
g m1

D. Small-Signal Response
Small-Signal Parameters:

AV0 = gm1(rds2 || rds4)gmARO

RO = rdsA || rdsB2

RID

pGA = pMiller 1/2(rds2 || rds4)(gmAROCC)

f0dB GBW = AV0pGA = gm1/2CC
CC shorts after pGA ZO 1/gmA and
pO gmA/2(CL + CPAR)
pG3 = pMirror gm3/2(2CGS3 + CGD4 + CGD1)
zD4 = zMirror = 2pG3
zRHP = zC gmA/2CC
Example: gm13 = 100 S, CG3 = 200 fF, gmA = 1 mS, rds24 = 2 M, rdsAB2 = 0.5 M,
CC = 5 pF, and CL + CPAR = 10 pF RID , RO = 250 k,
AV0 = 25 kV/V, pGA = 127 Hz, f0dB = 3.18 MHz, pO = 16 MHz, zRHP = 32 MHz,
pG3 = 80 MHz, and zD4 = 160 MHz pGA << f0dB < pO < zRHP < pG3, zD4.

Page 19

Analog IC Design

E. Power-Supply Rejection: i. Model and ii. Miller Effect

PSRR Model

Model what connects to vO MA, MB2, CC, and CL.

IBIAS's ZO should be high MB2's igmB2 can be negligible.
P-type mirror reproduces vdd and cancels vss
at MA's gate vsgA 0 igmA 0.
CC diode-connects MA to vDD.
MA's rdsA || ZgmA falls after ZgmA = rdsA.

Z gmA =

vo
igmA

1
R O1 +
vo
sCC
=
=
v o R O1g mA g mA R O1

R O1 + Z C

1
>>R O1
sCC

1
g mA R O1sCC

Slightly below
Miller pole pMiller.
fM

1
<p Miller
2R O1g mA rdsACC

rdsA

Where vGA's RO1 rds2 || rds4.

rdsA || ZgmA stops falling past fM after ZgmA flattens at 1/gmA.

When 1/sCC RO1, past fgmA 1/2RO1CC fMgmArdsA >> fM.

iii. Positive Supply Gain

At low frequencies, rdsA || ZgmA rdsA rdsA and rdsB2 voltage-divide vdd.
Past fM, rdsA || ZgmA falls MA couples more vdd to vo and AVDD rises Zero.
As rdsA || ZgmA drops below rdsB2, AVDD flattens to rdsB2/rdsB2 or 1 Pole.

r +r
From fM, AVDD climbs rdsA + rdsB2 Frequency rises dsA dsB2 .
rdsB2
rdsB2

rdsA + rdsB2
r +r
1
f = fM dsA dsB2

p Miller
2R
r
g
C
dsB2
O1 mA C rdsA rdsB2

CL then shunts what 1/gmA couples of vdd to vo past pO.

rdsB2
s

1+

rdsB2 || Z CO
r + r 2fM
A VDD =
dsA dsB2
(rdsA || Z gmA ) + (rdsB2 || Z CO ) 1+ s 1+ s
2p Miller 2p O

AVDD 1 after pMiller and before pO.

Page 20

Analog IC Design

Positive PSRR
+
PSRR 0 =

r +r
A V0
= g m1 ( rds2 || rds4 ) g mA ( rdsA || rdsB2 ) dsA dsB2 = g m1 ( rds2 || rds4 ) g mA rdsA
A VDD0
rdsB2

If rdsA rdsB2 PSRR0+ 2AV0.

pMiller and pO appear in both AV and AVDD They cancel in PSRR+:
PSRR + =

PSRR +

g ( r || r ) g r
AV
PSRR 0

= m1 ds2 ds4 mA dsA

A VDD
s
s
1+

1+

2fM
2fM
+

g ( r || r ) g r
PSRR 0
= m1 ds2 ds4 mA dsA 1
2f0dB g m1

R O1g mA rdsA CC
2fM CC
+

g
f0dB m1 >>fM
2CC

PSRR0+ 1 at f0dB No rejection.

iv. Negative Supply Gain

At low frequencies, rdsA || ZgmA rdsA rdsA and rdsB2 voltage-divide vdd.
As ZgmA drops below rdsA || rdsB2, AVSS falls MA shunts more vss to vDD pMiller pole.
Past fgmA = fMgmArdsA, rdsA || ZgmA stops falling at 1/gmA AVSS flattens Zero.
CL then shunts rdsB2's injection of vss across 1/gmA in vo past pO.
rdsA
s

1+

rdsA || Z gmA || Z CO
rdsB2 + rdsA 2fgmA
A VSS =

rdsB2 + ( rdsA || Z gmA || Z CO )

s
s
1+

1+
2p Miller 2p O

A VSS

1/g mA
after fgmA and before pO.
rdsB2

Page 21

Analog IC Design

Negative PSRR
PSRR 0 =

r +r
A V0
= g m1 ( rds2 || rds4 ) g mA ( rdsA || rdsB2 ) dsA dsB2 = g m1 ( rds2 || rds4 ) g mA rdsB2
A VSS0
rdsA

If rdsA rdsB2 PSRR0 2AV0.

pMiller and pO appear in both AV and AVSS They disappear in PSRR:
PSRR =

PSRR

g ( r || r ) g r
AV
PSRR 0

= m1 ds2 ds4 mA ds5

A VSS
s
s

1+
1+
2fgmA
2fgmA

g ( r || r ) g r
PSRR 0
= m1 ds2 ds4 mA dsB2 g mA rdsB2
2f
g m1
0dB

R O1CC
CC
2fgmA

f0dB

g m1
>>fgmA
2CC

PSRR0 gmArdsB2 at f0dB Considerable rejection.

v. Summary
P-type mirror reproduces vdd and cancels vss in MA's vGA.
MA cancels vdd in vGA with vdd in vSA.
IBIAS's ZO suppresses vdd and vss in igmB2.
CL shunts both input and supply
signals No effects in PSRR.
CC diode-connects MA.
rdsA || ZgmA falls to 1/gmA.
CC couples vdd and shunts vss PSRR+ << PSRR.

Page 22

Analog IC Design

F. Nulling Zero
Challenge:

zRHP gmA/2CC may not be sufficiently high.

Fix:

Limit CC's iFF, transform zRHP into an in-phase zero zM, and
use zLHP to recover pO's phase with current-limiting resistor RM.

Design:

zM 1/2(RM 1/gmA)CC pO gmA/2CL:

RM =

1 C L + CC

g mA CC

But:

CC and CL short past pO.

RM shunts rds2 || rds4.

CGA shorts RM at pNULL.
pNULL = pGA' 1/2RMCGA.
p NULL 2 (1/g m1 ) CC
=
>> 1
f0dB
2R M CGA

Since gmA >> gm1 and CGA << CC, RM's KC/gmA is low and pNULL >> f0dB.

CMOS Implementation
When moderate-resistance, low voltage-coefficient, and low temperature-drift
(analog) resistors are not available, channel resistance RCHANNEL is useful:
MR's IDR = 0 VSDR = 0 and MR is biased in triode as RCHANNEL.

Derive required vSGR from desired RCHANNEL = vSD/iD TRIODE 1/KP'SR(vSGR |vTP|).
Design desired vSGR with MB3 and MB4's vSGB3 + vSGB4 = vSGR + vSGA.

Page 23

Analog IC Design

G. Design Variables
Low-Frequency Gain AV0:
gm1,A and rds2,4,A,B2.
Unity-Gain Frequency f0dB:
gm1 and CC.
Phase Margin PM:
f0dB, pO, and zM.
gm1,A, CC, CL, and RM.
Input Common-Mode Range ICMR:
VDST,1,3(SAT).

Power Dissipation PQ:

Slew Rate SR:

vDD vSS and IQuiescent = IBIAS + IT + IB2.

IT and CC.

Offset VOS: Low if vSG3 vSGA and transistors match.

Output Swing vO(MAX):

VDSA,B2(SAT).

M1 to M2 and M3 to M4: Critical for i1 i2.

M3 to MA and MT to MB2: Good for vD13 vD24.

H. Design Example
Specifications:

vDD = vSS = 2.5 V

1 vIC 1.8 V 2 vO 2 V

PQ 1 mW

80 iO 80 A

CL 10 pF

SR 10 V/s

AV0 > 3 kV/V

f0dB 5 MHz

PM 60

IBIAS = 6 A

Process: L 0.6 m, LOL = 100 nm, COX'' = 2.4 fF/m2, KN' = 115 A/V2,
KP' = 40 A/V2, |VTP0| = 0.9 V, VTN0 = 0.65 V, and 1/L = 30 V for L = 3 m.
Sample Design:
1. Differential pair from ICMR and supplies.
Headroom to vDD = vDD vIC(MAX) = 2.5 1.8 = 0.7 V.
Headroom to vSS = vIC(MIN) vSS = (1) (2.5) = 1.5 V.
Negative Margin > Positive Margin.
Accommodate tail current with an N-type pair
and if possible, connect bulk to source No bulk effect on vTN.

Page 24

Analog IC Design

Designed:

2. gm12 and CC from f0dB gm12/2CC 5 MHz.

CC 5 pF gm12 157 S.

CC 5 pF

3. IT from CC and SR = IT/CC 10 V/s.

IT 60 A
S12 10

IT 50 A 60 A.

ST 10

4. S12 from IT and gm12 = [2(0.5IT)KN'S12] 157 S.

S34 15

S12 3.6 10.

5. ST from IT and vIC(MIN) = vSS + VDST(SAT) + VTN0 + VDS12(SAT) 1 V.
Where VDS12(SAT) = [2(0.5IT)/KN'S12] 228 mV.
VDST(SAT) 0.62 V ST 2IT/[KN'VDST(SAT)2] = 2.7 10.
6. S34 from IT and vIC(MAX) = vDD |VTP0| VSD34(SAT) + VTN0 1.8 V.

VSD34(SAT) 0.45 V S34 2(0.5IT)/[KP'VSD3(SAT)2] = 7.4 15.

7. IB2 from iO(MAX) = IB2 80 A 90 A.

MB2 mirrors MT IB2/IT = SB2/ST SB2 = 15.
8. Check vO(MIN) = vSS + VDSB2(SAT) 2.18 V 2 V.
VDSB2(SAT) = [2IB2/KN'SB2] 320 mV.
9. SA from S3 and IB2 VSDA(SAT) VSD3(SAT).
VSD3(SAT) = [2(0.5IT)/KP'S3] VSDA(SAT) = [2IB2/KP'SA].
(0.5IT)/S3 IB2/SA SA 3S3 = 45.

Designed:
CC 5 pF
IT 60 A
S12 10
ST 10
S34 15
IB2 90 A

10. Check pO gmA/2CL 10 MHz f0dB = 5 MHz.

SB2 15

11. For reasonable gain (i.e., low effects) and matching,

SA 45

all L's can be 5LMIN = 3 m.

Page 25

L's 3 m

Analog IC Design

12. RM from PM = 180 Tan1(f0dB/pMiller) Tan1(f0dB/pO) + Tan1(f0dB/zM) 60.

f0dB gm1/2(CC + WALOLCOX") 8 MHz.
pMiller 1/2(rds2 || rds4)[gmA(rdsA || rdsB2)(CC + WALOLCOX") 670 Hz.
pO gmA/2CL 9 MHz.
Tan1(f0dB/zM) 12 In-phase zero at zM 38 MHz.
And since zM = 1/2(RM 1/gmA)CC,
RM 2.6 k 3 k.
13. SB from IBIAS, IT, and ST.
MT mirrors MB.
IT/IBIAS = ST/SB
SB = ST(IBIAS/IT) = 1.

Designed:

IB2 90 A

CC 5 pF

SA 45

IT 60 A

SB2 15

S12 10

L's 3 m

ST 10

RM 3 k

S34 15

SB 1

14. Check f0dB gm12/2(CC + WALOLCOX") 8 MHz > 5 MHz.

Designed:

15. Check AV0 = gm12(rds2 || rds4)gmA(rdsA || rdsB2)

IT 60 A

(263)(0.5M)(569)(167k)

S12 10

12.5 kV/V = 82 dB > 3 kV/V.

ST 10
S34 15

16. Check vO(MAX) = vDD VSDA(SAT)

= 2.5 0.32 = 2.18 V > 2 V.
17. Check pMirror gm3/2CG3.

IB2 90 A
SA 45
SB2 15

CG3 COX"{2W34[(2/3)L3 + LOL] + (W4 + W1)LOL} = 465 fF.

pMirror 65 MHz >> f0dB = 8 MHz.
18. Check PQ = (IBIAS + IT + IB2)(VDD VSS) = 780 W < 1 mW.

Page 26

L's 3 m
RM 3 k
SB 1

Analog IC Design

19. Check pNULL 1/2RMCGA.

Designed:

CGA COX"{WA[(2/3)LA + LOL] + (W4 + W2)LOL} = 698 fF.

IT 60 A

pNULL 76 MHz 10f0dB = 80 MHz.

S12 10

20. Check iO(MAX)+ = iA(MAX) IB2.

ST 10

iA(MAX) 0.5KP'SA(vDD vGA(MIN) |VTP0|)2.

S34 15

Worst case of vGA(MIN) is at vIC(MAX).

IB2 90 A

vGA(MIN) = vIC(MAX) vGS2 + VDS2(SAT)

SA 45

= vIC(MAX) VTN0 = 1.8 0.65 = 1.15 V.

iA(MAX) 182 A and iO(MAX)+ 92 A > 80 A.

SB2 15
L's 3 m
RM 3 k

21. Check other specifications, and if necessary,

SB 1

revisit design steps and choices.

6.5. Class-AB Amplifiers: A. One-Stage Transconductor

Differential Input:

Differential Currents:

M1M2 processes vP vN.

M3M5 and M6MAB1 mirror i1.

M4MAB2 mirrors i2.
Class-AB Output:
MAB1 and MAB2 combine i1 and i2.
Bias:
Reference circuit generates IBIAS.
MBMT mirrors IBIAS.
Input and feedback
set VP, VN, and VO.

Feature: pO is dominant and all other poles

are at gm/CPAR No CC and fast.
Tradeoff: Lower AV0 and higher VOS and vN*.

Page 27

IT splits between M1 and M2.

M3M5, M6MAB1, and M4MAB2
mirror M12's bias currents.

Analog IC Design

i. Static Parameters
Bias Currents (where Si Wi/Li):
IT = IBIAS(ST/SB)
With negative Feedback, VN VP
I13 I24 0.5IT.
IAB1 IAB2 Design must ensure:
(S5/S3)(SAB1/S6) (SAB2/S4).
IAB12 = I12(SAB2/S4) = (0.5IT)(SAB2/S4)
Limits:
vIC(MAX) = vDD vSG3 VDS1(SAT) + vGS1

iO(MAX) = iAB1(MAX) = IT(S5/S3)(SAB1/S6)

= vDD |vTP| VSD3(SAT) + vTN

iO(MAX)+ = iAB2(MAX) = IT(SAB2/S4) iO(MAX)

vIC(MIN) = vSS + VDST(SAT) + vGS1

= vSS + VDST(SAT) + vTN + VDS1(SAT)
vO(MAX) = vDD VSDAB2(SAT)

ii. Small-Signal Response

vO(MIN) = vSS + VDSAB1(SAT)

iAB1 = 0 at iAB2(MAX), iAB2 = 0 at iAB1(MAX),

iAB1 = iAB2 > 0 when vO = 0 Class AB.

AV0 = gm1(SAB2/S4)RO
RO = rdsAB1 || rdsAB2

RID

pO 1/2RO(CL + CPAR)
f0dB GBW = AV0pO
= gm1(SAB2/S4)/2(CL + CPAR)
pG3 and pG4 each affect half of AV.
They produce the effect of one pole.
pG3 = gm3/2CG3, pG4 = gm4/2CG4
pG6 = gm6/2CG6, zAB1 = zMirror 2pG6
Example: If gm12AB12 = 200 S, gm3456 = 100 S, CGS12AB12 = 200 fF,
CGS3456 = 100 fF, rdsAB12 = 2 M, and CL = 10 pF.
Results: RID , RO = 1 M, AV0 = 400 V/V, pO 16 KHz, f0dB 6.4 MHz,
pG4 = pG6 53 MHz, pG3 80 MHz pO << f0dB << pG4, pG6 < pG3.

Page 28

Analog IC Design

iii. Other Parameters

1
Slew Rate: iAB1(MAX) and iAB2(MAX) slew CL + CPAR SR = I T AB2
.
S4 C L + C PAR

Systemic Offset: vDS mismatch across all mirrors contribute High.

VOS(S) must counter the effects of all mismatches:
VOS(S) =

v DS6AB1 v SD4AB2 ( v SD35 /rds5 )

v DS6AB1 v SD4AB2
v SD35

+
=
+
AV
AV
S
/S
g
g
S
/S
r
||
r
r
( 5 3 ) m1 m1 ( AB2 4 ) ( dsAB1 dsAB2 ) ds5 (S5 /S3 ) gm1

Random Offset: Mismatches in the differential pair and all mirrors contribute High.
VOS

2
2
i

i i i35
i 6AB1
4AB2
= 12 + 34 +
+
+

g
g
S
/S
g
S
/S
S
/S
g
S
/S
g

m1 m1 ( 5 3 ) m1 ( AB1 5 )( 5 3 ) m1 ( AB2 4 ) m1

Electronic Noise: Differential pair and all mirrors inject noise Noisy.
2

i * i * S i * S i * S i * S
i *
*
v N = 2 12 + 2 34 + 5 3 + 6 3 + AB1 4 + AB2 4
g m1
g m1 g m1 S5 g m1 S5 g m1 SAB2 g m1 SAB2

iv. Supply Rejection and v. Cascodes

Supply impedances to mirror M6MAB1 balance when vO is unloaded.
N-type mirror:

Cancels vdd AVDD 0 and PSRR+ approaches .

Reproduces vss AVSS 1 and PSRR AV.
Design Notes:
Cascoding mirrors can
Reduce VOS(S) and
Raise AV0, but also
Reduce vO(MAX).
RLOAD and CLOAD to ground
Shunt signal and noise in vO.
AV and AVSS fall.

Page 29

Analog IC Design

B. Two-Stage Hybrid
AB CS input amplifies and AB follower/transconductor drives the load.
MOB shuts when MOT drives iOT(MAX) iO(MAX)+ = iOT(MAX) f(IT).
MOB mirrors IT when MOT is off iO(MAX) = iOB(MAX) = IT(SOB/S6)(S5/S3).
iOT = iOB = 0.5IT(SOB/S6)(S5/S3) > 0 when vO = 0.
Class AB Little cross-over distortion.

Distortion:
MOT's AV MOB's AV.
AV(PK)+ AV(PK).
Gain distortion.
Power-Supply Rejection:
Gain stage cancels vdd
and reproduces vss.
MOT reproduces vss
and shunts rdsOT's
and MOB's injection.

C. Two-Stage Folded-Cascode Follower

Stacked gategate battery vSGO1 + vGSO2 biases MAB1 and MAB2:
Sets MAB1's and MAB2's no-load current.
Shuts MAB1 and MAB2 when supplying iO(MAX)+ or pulling iO(MAX).

PSR: Gain stage cancels vdd and reproduces vss and followers reproduce vss.

Page 30

Analog IC Design

D. Two-Stage Transconductor
MBOT and MBOB bias MOT and MOB:
When MOB pulls iO(MAX), MBOB shuts and MBOT cascodes MAB2 and biases MOT.
When MOT supplies iO(MAX)+, MBOT shuts and MBOB cascodes MAB1 and biases MOB.
CCT and CCB split poles and RM impedes out-of-phase feed-forward currents.

i. When Sinking Power

M5C balances mirror M6MAB1 when MOB sinks the load.
N-type mirror M6MAB1 cancels vdd and reproduces vss in vGOB.
igmOB excludes vdd and MOB cancels vss Low supply gain.

Without M5C, RDBOT magnifies igAB1's vdd and vss noise Higher supply gain.

Page 31

Analog IC Design

Example when MNO dominates:

vss appears in vGOB Feed-through to vGOB 0 dB.
MOB rejects vGOB's vss and rdsOBrdsOT voltage-divides vss AVSS0 7 dB.
vdd is nearly absent in vGOB Feed-through to vGOB 55 dB.
MOB excludes vdd and rdsOBrdsOT voltage-divides vdd AVDD0 10 dB.

PSRR0 AV0's 78 dB AVDD0/VSS0's 7 to 10 dB = 8588 dB.

Balanced mirror favors MOB PSRR is high when iO < 0.

ii. When Supplying Power

When MOT supplies the load: M5C current-buffers i5 and MBOB current-buffers iAB1.
M5 and MAB2 tend to balance mirror M6MAB1.
N-type mirror M6MAB1 tends to cancel vdd and reproduce vss in vGOT.
MOT amplifies vSOT's vdd and vGOT's vss High supply gain.
M5CMBOB cascode M5MAB1 to diminish igmAB1's vdd and vss and rdsAB1's vss.

Page 32

Analog IC Design

Example when MOT dominates:

Some vdd appears in vGOT Feed-through to vGOT 7 dB.
Some vss is absent in vGOT Feed-through to vGOT 25 dB.
MOT amplifies imperfections AVDD/VSS0 1130 dB.

PSRR0 AV0's 91 dB AVDD0/VSS0's 1130 dB = 6180 dB.

iii. Combined Response

When iO is 0 mA, MOB and MOT both conduct in Class-AB fashion.
MOBMOT dominance determines feed-through and supply gain.
vss mostly in vGOB and vdd in vGOT Feed-through 0 to 4 dB.
vdd is mostly absent in vGOB and some vss in vGOT Feed-through < 14 dB.

PSRR0 AV0's 87 dB AVDD0/VSS0's 625 dB = 6281 dB.

Page 33

Analog IC Design

6.6. Current-Mode Amplifiers

Motivation for processing currents:
Low-resistance nodes High-frequency poles.
Low-voltage swings Lower large-signal slew-rate delays.
Lower charge/discharge energy for capacitors.
More headroom to supplies Higher dynamic range.
Ideal Characteristics:

Current Amplifier

AI .

RINP

RINP, RINN Should shunt iIN 0 .

RO Should impede iO .
RO

RINN

Ideal Source and Load:

RS Should impede iIN .

iO = (iP iN)AI

RL Should shunt iO 0 .

A. Current-Mode Concept
Conceptual Development:
High accuracy with negative feedback.
Highest bandwidth fI 0dB when FB does not attenuate AI LG.
Use current amplifier in unity-gain feedback.
Translate vIN to iIN with RIN.
A load RL steals current away from iFB.
iFB iO with RL.
Should not load the circuit Buffer the output.
AG

1 A I
iO i IN iO 1
=
A I(CL) =

=
v IN v IN i IN R IN
R IN 1+ A I

Page 34

Analog IC Design

For a voltage gain:

Translate iO to vOI with ROI.
Buffer vOI with high-ZIN AV so iFB = AI's iO.
Since ROI does not affect iFB, AI remains in unity gain across ROI values.
A V.IO

" A A %" R %
v O " i IN %" i O %" v OI %" v O % " 1 %
= $$
''$$ ''$$
''$$
'' = $$
'' A I(CL) R OI A V = $$ I V ''$$ OI ''
v IN # v IN &# i IN &# i O &# v OI & # R IN &
# 1+ A I &# R IN &

Frequency Response:
AI(CL) sets vO/vIN's bandwidth fV BW to fI 0dB.
ROI/RIN sets vO/vIN's gain, but not fV BW.
fV BW = fI 0dB f(Gain).
No fall in fV BW for higher gain.

B. Example: i. Operation
RIN translates vin to iin.
M1M2 amplifies iin ifb.
ROI translates io to vg8.
M8 buffers and reproduces vg8.
M34567 bias M1M2 and M8.

v
g m8 ( rds7 || R L )
1
S /S
i
v in
i
v

= in o g8 o
2 1 (R OI )

v o v in i in io v g8 R IN 1+ S2 /S1
1
1+ g m8 +
( rds7 || R L )
r

ds8
Design Notes:

M2's rds2 and M4's rds4 steal current from ROI Reduce ROI, lengthen M2's L2
and M4's L4, degenerate M2 and M4, and/or cascode M2 and M4.
1/gm1 adds load to vIN Raise RIN and/or gm1 (i.e., I34 and/or W12).

Page 35

Analog IC Design

ii. Small-Signal Response

AI OL io/ie = S2/S1
FB ifb/io 1 if ROI << rds2 || rds4
AI CL io/iin = AI OL/(1 + AI OL)
AV IO = vo/vin (1/RIN)AI CL(ROI)
if iin vin/RIN RIN >> 1/gm1.
fV BW = fI 0dB GBWI = AI OLpG8
(S2/S1)/2ROICG8
fV 0dB GBW = AV IOfV BW

For iR1 vin/R1, RIN >> 1/gm1.

pG1 gm1/2(CGS1 + CGS2)

For ifb io, ROI << rds2 || rds4.

pO gm8/2(CGS8 + CL)

Limited gain ROI/RIN.

Raising RD2 and RD4 relaxes ROI's limit.

zGS8 gm8/2CGS8 In phase.

If RIN = 10 k, ROI = 200 k, S1 = S2, CG8 = 250 fF AV IO = 10 and fV 0dB = 32 MHz.

C. Design Notes on High-Speed Amplifiers

gm/CPAR limits bandwidth:

I C "(W/L)
I K '(W/L)
I t
gm
D
D OX
D OX3
C PAR
COX"WL
COX"WL
WL

Higher currents raise gm/CPAR (i.e., gain and bandwidth), but also power.
Shorter channel lengths raise gm/CPAR more than shorter tOX lowers gm/CPAR.
Finer-pitch technologies reach higher bandwidths.
Each stage introduces at least one bandwidth-limiting pole.
Because BJTs are exponential and FETs are square law,
BJT gm's are normally higher than MOS gm's.
1Compensating

a negative-feedback loop reduces bandwidth.

Avoid negative feedback if possible and unnecessary.

Since:

2Low

resistances raise bandwidth and lower gain.

And:

3Poles

near f0dB in an open-loop system (with no feedback) are harmless.

Implement 1open-loop system with 3several 2low-gain, high-bandwidth stages.

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Analog IC Design

Chapter 7. Comparators

Outline
7.1. Generalities
7.2. Open-Loop Comparators
7.3. Summing Comparators
7.4. Hysteretic Comparators
7.5. Regenerative Comparators
7.6. High-Speed Comparators

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Analog IC Design

7.1. Generalities: A. Operation

A comparator is a one-bit analogdigital (A/D) converter.
Compares analog inputs and outputs a "high" only if vP > vN.

Desirable Static Parameters:

High output swing vO = VOH VOL.
High input common-mode range ICMR.
Good resolution Low vID(MIN) = vO/AV0 VIH VIL.
High gain AV0.

Desirable Dynamic Parameters:

Low input-referred offset VOS.

Short propagation delay tP.

Low input-referred noise.

High slew rate SR.

High input resistance RIN

B. Dynamic Response

Step Response

Propagation Delay:
From vID's VID(MID) = 0.5(VIL + VIH).
To vO's VO(MID) = 0.5(VOL + VOH).

t P Avg t P(RISE) , t P(FALL) =

t P(RISE) + t P(FALL)
2

Bandwidth-Limited Response:
Linear single-pole system produces an exponential response.
AV =

A V0
s
1+
2p1

)
# t &,
v O = v ID A V0 +1 exp % (.
$ 1 '*

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Analog IC Design

Step Response: When vID undergoes an instant step transition.

*
$ t 'v O = v ID A V0 ,1 exp && ))/ tP t when vO 0.5vO(FINAL) 0.5(VOH VOL).
,+
% 1 (/.

Minimum drive vID(MIN) (VOH VOL)/AV0.

Input-overdrive factor KO vID/vID(MIN).

vID KOvID(MIN)
# 2K &
O
t P = 1 ln %%
((
$ 2K O 1 '

With a linear circuit, response tP is a negative exponential Fast at first, then slow.

Slew-Rate Limited Response:

SR =

C
dv O i O(MAX)
0.5 ( VOH VOL )
v
=
t P(SR) = t C = L v O = O =
dt
CL
SR
SR
iO(MAX)

Example
Parameters: pBW = 1.6 kHz, AV0 = 1 kV/V, SR = 1 V/s,
VOH = 1.5 V, VOL = 0.5 V, and vID = 10 mV.
Solution:

vID(MIN) = (VOH VOL)/AV0 = 1 mV

KO = vID/vID(MIN) = 10
tP(BW) = (1/2pBW) ln [2KO/(2KO 1)] = 5.1 s
tP(SR) = 0.5(VOH VOL)/SR = 0.5 s
tP tP(BW) + tP(SR) = 5.6 s

Consider both bandwidth and slew rate.

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Analog IC Design

C. Noise
Noise in vID produces uncertainty in transition and jitter at the output.
Comparator
threshold

vin

vout

VOH

Noise
Jitter

VOL

Incorporating sufficient hysteresis in the comparator removes noise jitter.

vin

VTRP+

vHYS > vN*

VTRPVOH

VTRIP+ VTH(RISE) > VTRIP VTH(FALL)

VOL

vout

No Jitter

7.2. Open-Loop Comparators: A. Class-A Transconductor

VOH = vDD because iA is 0.

VOL = vSS + vDSA(TRIODE)
vDSA(TRIODE) = IBRDSA(ON)
RDSA(ON) is channel resistance:

Performance Parameters:
VTRIP = VGSA(IQ ) + v SS = VTN0 +

2I B
+ v SS
K N'(W/L)A

R DSA(ON) =

v DS
1

K N'(W/L)A v GSTA
iD

Where vGSTA vGSA vTN

SR+ = IB = IBIAS(SB/S1)/CL

AV0 gm1(rdsA || rdsB)

SR = (iA IB)/CL

pO 1/2(rdsB || rdsB)CL

= [0.5KN'(W/L)AvGSTA2 IB]/CL

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Analog IC Design

B. Class-AB Transconductor

Performance Parameters:
VOH = vDD because iAB1 = 0.
VOL = vSS because iAB2 = 0.
ICMR is same as in op amp.
AV0 gm1(SAB2/S4)(rdsAB1 || rdsAB2)
pO 1/2(rdsAB1 || rdsAB2)CL
SR+ IT(SAB2/S4)/CL
SR IT(S5/S3)(SAB1/S6)/CL

Low gain (one gain stage), limited SR (by IT), symmetrical SR (MAB12 pushpull),
high-swing (rail-to-rail to vDD and vSS), one low-frequency pole (at vO), and
poor offset and poor noise (from several transistors in first stage).

C. Two-Stage Class-A Transconductor

Op amp without compensation because circuit is not used in negative feedback.
Performance Parameters:
VOH = vDD vSDA(TRIODE)
vSDA(TRIODE) = IB2RSDA(ON)
R SDA(ON) =

v SD
1

K P'(W/L)A v SGTA(MAX)
iD

vIC limits vSGTA(MAX).

VOL = vSS because iA is 0.
ICMR is same as in two-stage op amp.

AV0 gm1(rds2 || rds4)gmA(rdsA || rdsB2)

SR = IB2/CL = IBIAS(SB2/SB)/CL

pO 1/2(rdsA || rdsB2)CL

SR+ = (iA(MAX) IB2)/CL

CL shunts CGDA's Miller gain.

= [0.5KP'(W/L)AvSGTA(MAX)2 I5]/CL

Page 41

pGA 1/2(rds2 || rds4)CGSA.

Analog IC Design

Step Response
Differential stage trips when vP crosses vN.
Class-A transconductor trips when vGA crosses VTRIPA: Analyze when circuit balances.

2I B2
VTRIPA = v DD v SGA(IBIAS ) = v DD VTP 0 +
K P'(W/L)A

tGA: IT slews CGA.

MA reacts when
vGA reaches VTRIPA.
tP = tGA + tO.
IO(MAX) << IO(MAX) +
SRO << SRO+.
tP(F) >> tP(R).

IT limits SRGA delays tGA+ and tGA Faster with higher IT.
Wide gate swing at vGA delays falling response (tGA+) Faster with lower swing.

Linear Two-Pole Step Response

Assuming no slew-rate conditions exist:
Raising the second pole pO
Removes pO.
accelerates response.

Two
equivalent
poles.
Reducing the
second pole pO Removes
pGA.

slows response.

All poles slow response Shift as many poles as possible to high frequency.

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Analog IC Design

D. Clamped and Buffered Two-Stage Class-A Transconductor

MG12 limits vGA's swing and Class-AB inverters(1,2,3) drive low-Z loads.
(1) Center

trip points: Balance FET strengths Offset N/P and vT mismatches.

(2) Raise

bandwidth: Lighten MAB2's load Minimum-size clamp and inverter.

(3) Raise

CL's slew rate: Build drive current Increasingly larger inverters.

Lowest delay with e 2.67 larger stages, but inverters dissipate power
use 5 to 10 larger stages.
Example if VTN0 = |VTP0|:
(1) W
PI1

2.5WNI1

(2) L
G1,G2,I1,I2

LMIN

(2) W
G1,G2,NI1

WMIN

(3) W
PI2

5WPI1

(3) W
NI2

5WNI1

7.3. Summing Comparators

Use: Sum analog inputs Trip when vA + vB crosses 0.
How: Project voltages to currents that sum.
Operation: MA12 and MB12's iD projections sum and balance when inputs balance.
Matching Requirements: M1:M2, MA1:MA2, MAT:MBT, MA12:MB12, M9:M10, M3:M4.

iO = (vAP vAN)gmA12 + (vBP vBN)gmB12 = 0 when inputs balance.

If gmA12 gmB12, vO trips when vA + vB crosses 0.

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Analog IC Design

7.4. Hysteretic Comparators: A. Externally Defined

i. Inverting Configuration
State of vO sets vP and comparator trips when vIN crosses vP.
Positive feedback
establishes hysteresis.

VTRIP+ = v P

VTRIP = v P

v O =VOH

v O =VOL

VHYS = VTRIP =

(V

VOH R IN
R FB + R IN

VOL R IN
R FB + R IN

OH

VOL R IN

R FB + R IN

Inserting a voltage between RIN and ground shifts VTRIP+ and VTRIP
by the same amount without affecting VHYS.
Trip points are sensitive to supplies via VOH and VOL Variable and noisy.

ii. Noninverting Configuration

vIN and state of vO set vP and comparator trips when vP crosses 0.
Positive feedback
establishes hysteresis.

VTRIP+ = v IN

VTRIP = v IN

v P =0 and v O =VOL

v P =0 and v O =VOH

" V %
= i RFB R IN = $$ OL '' R IN
# R FB &
" V %
= i RFB R IN = $$ OH '' R IN
# R FB &

#R &
VHYS = VTRIP = VOH VOL %% IN ((
$ R FB '

Connecting a voltage to vN shifts VTRIP+ and VTRIP

by the same amount without affecting VHYS.
Trip points are sensitive to supplies via VOH and VOL Variable and noisy.

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Analog IC Design

B. Current Defined: i. Class-AB Transconductor

Transition when i1 i3.

Schmidt Trigger

M2 is off and about to trip: vS2 = VTRIP+ vTN2.

i1 = 0.5K N'S1 ( VTRIP+ VTN0 )

2
2

i3 = 0.5K N'S3 ( v DD v S3 ) v TN2

0.5K N'S3 ( v DD VTRIP+ )

Positive
Feedback

Transition when i4 i6.

M5 is off and about to trip: vS5 = VTRIP + |vTP5|. Trip points are insensitive to K',
2

i 4 = 0.5K P'S4 ( v DD VTRIP ) VTP0

i 6 = 0.5K P'S6 ( v S5 v TP5 )

but sensitive to vTN, vTP, vDD, and vSS.

Inaccurate, variable, and noisy.
Useful for digital applications.

0.5K P'S6 VTRIP 2

ii. Two-Stage Class-A Transconductor

State of vO and iH produce an offset that vID must overcome to trip the comparator.
When vP rises towards vN,
Positive
Feedback

vO is initially low,
MFB is off and iH is 0, so
vO rises when i2 overcomes i1.
When vP falls towards vN,
vO is initially high,
MFB is on and iH > 0, so
vO falls when i1 overcomes i2 + iH.

Notes: Positive feedback establishes hysteresis.

Hysteresis is asymmetrical: VTH+ VTH.

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Analog IC Design

If iH is not low, use large-signal model.

If iH is low, use linear model.

VHYS = VTRIP+ VTRIP = 0 VOS(S)

iH
g m1

VOS(S) = v GS2 v GS1 =

2 (i2 + iH )
2i 2

S2 K N '
S1K N'

Where VT's cancel and

i1 + i2 = (i2 + iH) + i2 = IT.
Hysteresis is asymmetrical.
Trip points are
independent of the supplies.

C. Voltage Defined
vH produces an offset that vID must overcome to transition vO.
MH1MH2:

Adds offset vH when vO is low.

Subtracts offset vH when vO is high.

VTRIP+ = VTRIP = v H mH12

g m12

vH should be low to keep translation linear.

MH1MH2 should match M1M2 and MT should match MHT.
Hysteresis is symmetrical.

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Analog IC Design

D. Load Defined: Cross-Coupled Mirrors

When vI1 rises towards vI2,
vO1 is initially high,
M3M6 is off and vO1 falls
when i1 overcomes i2(S5/S4).

VTRIP+ = v GS1 v GS2 =

2i 2 (S5 /S4 )
2i 2

S1K N'
S2 K N '

Where VT's cancel and

i1 + i2 = i2(S5/S4) + i2 = IT.

i1 = i2(S5/S4) > i2 i1 must surpass 0.5IT by some margin to induce a transition.

When vI1 falls towards vI2,

vO2 is initially high,
Positive
Feedback

M4M5 is off and vO2 falls

when i2 overcomes i1(S6/S3).

VTRIP = v GS1 v GS2 =

2i1 (S6 /S3 )

2i1

S1K N'
S2 K N '

Where VT's cancel and

i1 + i2 = i1 + i1(S6/S3) = IT.

Notes: S6/S3 and S5/S4 should be greater than 1 to establish hysteresis.

S6/S3 and S5/S4 set the symmetry of the hysteresis.
Positive feedback establishes hysteresis.

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Analog IC Design

Example
Parameters:
vI1 = vIN, vI2 = VREF = 1 V,
S1 = S2 = S5 = S6 = 10,
S3 = S4 = 2, IT = 20 A,
vDD = 2.5 V, vSS = 2.5 V,
and KN' = 100 A/V2.

vIN+: i2(S5/S4) + i2 = IT at i1 = 16.7 A.

VOH vDD
vO(MAX)

Solution:

VTRIP+ = vGS1 vGS2 + VREF 1.136 V

vIN: i1(S6/S3) + i1 = IT at i1 = 3.33 A.
VTRIP = vGS1 vGS2 + VREF 0.864 V

VOL = vDD vSG3

Note that vO(MAX) is vSG34 at IT Low.

Folded Class-AB Transconductor

MAB1 mirrors M3's current i3 and M7 mirrors M4's current i4.
M8 and MAB2 fold M7's projection of i4 to output vO.

iO(MAX)+ = IT(SAB1/S3)

iO(MAX) = IT(S7/S4)(SAB2/S8)

Symmetrical slew rate, high voltage swing, and pushpull architecture.

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Analog IC Design

7.5. Regenerative Comparators: A. Concept and Latch

Concept: Positive feedback regenerates and latches vO to the supplies.
As vO regenerates, feedback grows and response accelerates.
Location: Positive feedback at the input shifts threshold to establish hysteresis.
Positive feedback at the output accelerates response with
gain-divided and therefore minimal effects on trip points.
Latch:

Operation:
Small vI1 vI2 difference vid
produces imbalance.
Positive feedback

Positive
Feedback

regenerates
initial imbalance.

Basic Advantage: Regeneration accelerates transition Faster response.

B. Response Time
Small Differential Input:

+t
C t v 1
v O(FIN) = v O(INI) exp GS = id g m1

exp

g
g
2
m3
m3
LATCH

Positive Exponential

i1 = 0.5vidgm1 i2 = 0.5vidgm2
vO1(INI) = vO2(INI)
R EQ

v O1
v O1
1

=
g m3
i3
v O2g m3

C EQ CGS

Propagation Delay:
vO(FIN) reaches 0.5(VOH VOL) in tP.
V V
OL

t P = LATCH ln OH
2v

O(INI)

Lower drive vID produces an exponentially slower response.

With positive feedback, response tP is a positive exponential Slow at first, then fast.

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Analog IC Design

7.6. High-Speed Comparators: A. Response Time

Regenerative Response

Linear Response

Fast at first,

Slow at first,

even with low input drive, and

Slow in the end.

with little regeneration, and

Fast in the end,
as output regenerates.

Use: Linear input stages to amplify drive.

Regenerative output stages to accelerate transitions.

B. Design Notes
Low resistances raise bandwidth and lower gain.
Poles near f0dB are harmless.
Use multiple low-gain, high-bandwidth stages.
Linear stages are faster with low overdrive vIN.
Regenerative stages are faster with high overdrive vIN.
Low-voltage swings vO shorten propagation delay.
Use linear low-swing preamplifier and regenerative high-swing output.
To drive large CL with least delay, use increasingly 2.67 larger AB inverters.
But to reduce power, build drive with 5 to 10 larger AB inverters.

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Analog IC Design

Example
Two low-gain, low-swing pre-amplifiers with regenerative Class-AB output.
Three balanced

Gate-Drive Booster

5 larger
Class-AB inverters.

High-swing Class-AB latch.

Page 51