Chapter 4 - Flip-Flops and Related Devices

BETC 2404
DIGITAL ELECTRONICS
CHAPTER 4:
FLIP-FLOPs AND RELATED DEVICES
UNIVERSITI TEKNIKAL MALAYSIA MELAKA

Kompetensi Teras Kegemilangan
PART 1:
LATCH AND FLIP FLOP

Sequential Circuits
Combinational output depends only on the input.
Do not have memory
Cannot store state
Sequential output depends on input and past behavior.

Require use of storage elements.
Contents of storage elements is called state.
Circuit goes through sequence of states as a result of changes in inputs.

Sequential Circuits Types

Synchronous
State changes synchronized by one or more clocks
Easier to analyze because can factor out gate delays
Set clock so changes allowed to occur before next clock pulse
Asynchronous
Changes occur independently
Potentially faster
Harder to analyze

Simple Memory Elements

A simple memory element: feedback will hold value
A
Basic storage made from gates

Reset
Set
A memory element with NOR gates:

Use Set/Reset to change stored value
Latch
Latch is a type of temporary storage device that has two
stable (bistable) state: SET and RESET:
SET means that the output (Q) is HIGH
RESET means that the output (Q) is LOW
Type of latches:
SR / SR Latch (SR = Set-Reset)
Gated SR Latch
Gated D Latch
SR Latch
R
Function Table
Function
Qo
Hold
Reset
Set
Not allowed
Graphical symbol
If S & R both 1 at same time, Q = Q = 1

SR Latch
SR
0X
Detailed Function
Table
Q+
Excitation Table
Q+
01
10
1
X0
Excitation Table: What are the necessary inputs

to cause a particular kind of change in state?
State Transition
Diagram:
The excitation table in
graphical form

SR Latch
Function Table
S
Function
Qo
Hold
Reset
Set
Not allowed

Gated SR Latch
Add Control Input
Typically, control signal is referred to as a clock
EN
c) Block Diagram
a) Logic Diagram
b) Block Diagram

Gated SR Latch
1
EN
0
1
R
0
S
EN
0
R
1
?
Q
0
Graphical symbol
1
?
Q
0
Time

Gated D Latch
D
(Data)
S
Q
EN
Q
(a) Logic Diagram
c) Block Diagram

Gated D Latch
D
EN
(c) Graphical symbol
EN
D
Q
EN = 1
EN = 1
EN = 1
(d) Timing diagram

EN = 1
D Latch
0
Detailed Function
Table
Excitation Table
Q+
Q+
1
1
State Transition
Diagram
Standard Symbols Latches
Circle at input indicates negation

Flip-Flops
Flip flops are bistable devices and performs a function
same as latches.
However, the output changes only during the rising edge
(positive edge-triggered) or falling edge (negative edgetriggered) of the clock pulse.
There are 4 types of flip-flop:
a) S-R flip flop
b) D flip flop
c) J-K flip flop
d) T flip flop
16

Flip-Flops
Ensure only one transition.
Two major types:
1. Master-Slave
Two stage
Output not changed until clock disabled
2. Edge triggered
Change happens when clock level changes

Edge-Triggered Flip-Flops
Synchronous input
Change state either at positive edge or negative edge
of a clock pulse.
Edge triggered S-R flip flop

S-R Flip-Flop
Positive-edge S-R Flip Flop:

S-R Flip-Flop
Edge-triggeringpulse transition
detector, produces
a very shortduration spike
during the
transition of the
clock pulse.

D Flip-Flop
1
P3
P1
Clock
P2
Clock
P4
(b) Graphical symbol
(a) Logic Diagram
A positive-edge-triggered D flip-flop
D Flip-Flop
Positive-edge D Flip Flop:

D Latch vs D Flip-Flop
D
Clock
Qa
Clk
EN Q
Qa
Clock
D
Qb
Qa
Qb
Qc
Qc
Qb
Qc
(b) Timing diagram
(a) Logic Diagram
Comparison of level-sensitive and edge-triggered devices

T Flip-Flop
Positive-edge T Flip Flop:
24

T Flip-Flop
Exercise:
Determine the Q output waveforms flip flop
in Figure (a) for T and CLK inputs in Figure (b)
below. Assume that flip flop initially RESET.
Figure (a)
CLK
T
Q
CLK
T
Q
Figure (b)
25

JK Flip-Flop
(a) Logic Diagram

J K Q ( t + 1)
0
0
1
1
0
1
0
1
Q (t )
0
1
Q (t )
(c) Graphical symbol
(b) Truth table

JK Flip-Flop
Positive-edge J-K Flip Flop:

JK Flip-Flop
Negative-edge J-K Flip Flop:

JK Flip-Flop
Detailed
Function Table
J K Q
Q+
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
SR
0X
0
Excitation Table
Q
Q+ J K
0 X
1 X
X 1
X 0
X1
1
X0
State Transition
Diagram

1X
Symbols Edge-Triggered
Arrow indicates edge trigger

Asynchronous Inputs
State of the flip flop change independent of the
clock.
Input
Output
Comment
Invalid
SET
RESET
Q0
Toggle

Asynchronous Inputs
Example:
Input

Comment
Invalid
SET
RESET
Q0
Toggle

Output
Q
Flip-flops Operating Characteristics




Propagation delay time:
tPLH from triggering edge of clock pulse to LOW-to-HIGH output
transition.
tPHL from triggering edge of clock pulse to HIGH-to-LOW output
transition.
tPLH from leading edge of preset input to LOW-to-HIGH output
transition.
tPHL from leading edge of clear input to HIGH-to-LOW ouput
transition.


Set-up time,ts
Minimum interval required for the logic level to be maintained
constantly on the inputs prior to the triggering edge of clock
pulse.
Hold-time, th
Minimum interval required for the logic levels to remain on the
inputs after the triggering edge of the clock pulse.
Maximum clock frequency response
Highest rate at which a flip-flop can be reliably triggered
Pulse width, tw
Minimum pulse widths for reliable operation.
Power dissipation
Total power consumption of the device. P=VCC X ICC
Flip-flops Applications
Parallel data storage

Frequency division

Counting

PART 2:
COUNTER

Sequential circuits that go through prescribed sequence of states. Depending

on the way they are clocked, counters can be broadly categorized as:
1. Synchronous
2. Asynchronous
Counters can also be further classified in terms of:
1. Type of sequence
2. Modulus number of states
(MOD number is equal to the number of states that the counter goes
through before recycling. Adding FFs will increase the MOD number)
3. Number of flip-flops

Asynchronous Counter
Operation

Asynchronous Counter
Operation
Asynchronous binary counter
a) 2-bit asynchronous binary counter
b) 3-bit asynchronous binary counter
c) 4-bit asynchronous binary counter
Asynchronous decade counter

Asynchronous Counter Operation

a) 2-bit asynchronous binary counter






c) 4-bit asynchronous binary counter


Asynchronous decade counter

Counters with MOD Number < 2N
Changing the MOD number.

o
Find the smallest MOD required so that 2N is

less than or equal to the requirement.
Connect a NAND gate to the asynchronous

CLEAR inputs of all FFs.
Determine which FFs are HIGH at the desired

count and connect the outputs of these FFs to
the NAND gate inputs.
Example:
A counter is needed will count the number of
items passing on the conveyor belt. A photocell
and light source combination is used to
generate a single pulse each time crosses its
path. The counter must be able to count as
many as one thousand items. How many FF
required?



Ripple counters are simple, but the

cumulative propagation delay can cause
problems at high frequencies.
For proper operation the following apply:
o
Tclock N x tpd
Fmax = 1/N x tpd

Synchronous Counter Operation


Synchronous binary counters
a) 2-bit counter
b) 3-bit counter
c) 4-bit counter
Synchronous BCD decade counter


a) 2-bit synchronous binary counter


b) 3-bit synchronous binary counter


b) 3-bit synchronous binary counter
Q1 ONLY toggle (HIGH)
if Q0 HIGH at next clock
cycle (Rising Edge)
Q2 ONLY toggle (HIGH)
if both Q1 and Q0 at next
clock cycle (Rising Edge)
Its keep previous value if
the Q0 (or Q1) still not
active.


c) 4-bit synchronous binary counter


c) 4-bit synchronous binary counter

PART 3:
SHIFT REGISTER

Shift Register
A type of sequential logic circuit, mainly for storage of digital
data.
They are a group of flip-flops connected in a chain so that
the output from one flip-flop becomes the input of the next
flip-flop.
Most of the registers possess no characteristic internal
sequence of states.
All the flip-flops are driven by a common clock, and all are
set or reset simultaneously.
Basic Shift Register

a)
b)
c)
d)
Serial in/serial out (SISO)

Serial in/parallel out (SIPO)
Parallel in/serial out (PISO)
Parallel in/parallel out (PIPO)

SISO Shift Register

A basic four-bit shift register can be constructed using four D flip-flops, as
shown below.
Operation: The register is first cleared, forcing all four outputs to zero. The
input data is then applied sequentially to the D input of the first flip-flop on the
left (FF0). During each clock pulse, one bit is transmitted from left to
right. Assume a data word to be 1001. The least significant bit of the data has
to be shifted through the register from FF0 to FF3.
SISO Shift Register

4-bit SISO

SIPO Shift Register

For this kind of register, data bits are entered serially in the same
manner as discussed in the last section. The difference is the way in
which the data bits are taken out of the register. Once the data are
stored, each bit appears on its respective output line, and all bits are
available simultaneously. A construction of a four-bit serial in - parallel
out register is shown below.

SIPO Shift Register

4-bit SIPO
Waveforms

SIPO Shift Register

4-bit SIPO

PISO Shift Register
A four-bit parallel in - serial out shift register is shown below. The circuit uses D
flip-flops and NAND gates for entering data (i.e. writing) to the register.
D0, D1, D2 and D3 are the parallel inputs, where D0 is the most significant bit
and D3 is the least significant bit. To write data in, the mode control line is taken
to LOW and the data is clocked in. The data can be shifted when the mode
control line is HIGH as SHIFT is active high. The register performs right shift
operation on the application of a clock pulse.

PISO Shift Register

4-bit parallel in/serial out
Waveforms

PISO Shift Register

4-bit PISO

PIPO Shift Register
For parallel in - parallel out shift registers, all data bits appear on the parallel
outputs immediately following the simultaneous entry of the data bits. The
following circuit is a four-bit parallel in - parallel out shift register constructed by
D flip-flops.
The D's are the parallel inputs and the Q's are the parallel outputs. Once the
register is clocked, all the data at the D inputs appear at the corresponding Q
outputs simultaneously.

PIPO Shift Register

4-bit PIPO
Waveforms

PIPO Shift Register


Chapter 4 - Flip-Flops and Related Devices

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BETC 2404

UNIVERSITI TEKNIKAL MALAYSIA MELAKA

UNIVERSITI TEKNIKAL MALAYSIA MELAKA

Sequential output depends on input and past behavior.

UNIVERSITI TEKNIKAL MALAYSIA MELAKA

Sequential Circuits Types

UNIVERSITI TEKNIKAL MALAYSIA MELAKA

Simple Memory Elements

Basic storage made from gates

A memory element with NOR gates:

If S & R both 1 at same time, Q = Q = 1

UNIVERSITI TEKNIKAL MALAYSIA MELAKA

Excitation Table: What are the necessary inputs

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(a) Logic Diagram

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(c) Graphical symbol

(d) Timing diagram

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Standard Symbols Latches

Circle at input indicates negation

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Edge triggered S-R flip flop

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(b) Graphical symbol

(a) Logic Diagram

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(b) Timing diagram

(a) Logic Diagram

Comparison of level-sensitive and edge-triggered devices

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(a) Logic Diagram

(c) Graphical symbol

(b) Truth table

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Arrow indicates edge trigger

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Flip-flops Operating Characteristics

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Flip-flops Operating Characteristics

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Flip-flops Operating Characteristics

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Flip-flops Operating Characteristics

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Flip-flops Operating Characteristics

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Sequential circuits that go through prescribed sequence of states. Depending

Counters can also be further classified in terms of: