Part - 4

Control unit, Interrupts and Pipeline of

Fixed point DSPs (TMS320C54X series)

Status and control registers

The 54x has three status and control registers:

1. Status register 0 (ST0)
2. Status register 1 (ST1)
3. Processor mode status register (PMST)
ST0 and ST1 contain the status of various conditions and modes
PMST contains memory-setup status and control information.
These registers are memory-mapped, they can be stored into and loaded from
data memory
The status of the processor can be saved and restored for subroutines and
interrupt service routines (ISRs).
Status register 0 (ST0) diagram

Status register 1 (ST1) diagram

Processor mode status register (PMST) diagram

Status register 0 (ST0)

DP- Data-memory page pointer or Data page pointer 9 bits
This 9-bit field is concatenated with the seven LSBs of an instruction word to form a
direct-memory address of 16 bits for single data memory operand addressing.
The DP field can be loaded by the LD instruction with a short-immediate operand or
from data memory
OVB - Overflow flag for accumulator B 1 bit
OVB is set to 1 when an overflow occurs in either the ALU or the multipliers adder and
the destination for the result is accumulator B.
OVA - Overflow flag for accumulator A 1 bit
OVA is set to 1 when an overflow occurs in either the ALU or the multipliers adder and
the destination for the result is accumulator A.
C Carry flag 1 bit
Carry is set to 1 if the result of an addition generates a carry; it is cleared to 0 if the
result of a subtraction generates a borrow. Otherwise, it is reset after an addition and
it is set after a subtraction.
TC Test /control flag 1 bit
TC stores the results of the arithmetic logic unit (ALU) test bit operations.
The status (set or cleared) of TC determines if the conditional branch, call, execute,
and return instructions execute
ARP - Auxiliary register pointer 3 bits
This 3-bit field selects the auxiliary register to use in the indirect single-operand
addressing

Status register 1 (ST1)

ASM Accumulator shift mode bit 5 bits
The 5-bit ASM field specifies a shift value within a 16 through 15 range and is
coded as a 2s-complement value.
CMPT Compatibility mode bit 1 bit
Determines the compatibility mode for the ARP
CMPT = 0 ARP is not updated in indirect addressing mode with a single data
memory operand.
CMPT = 1 ARP is updated in indirect addressing mode with a single data memory
operand, except when the instruction is selecting auxiliary register 0 (AR0).
FRCT Fractional mode bit 1 bit
When FRCT is 1, the multiplier output is left-shifted by one bit to compensate for
an extra sign bit.
C16 Dual 16-Bit/double-precision arithmetic mode bit 1 bit.
Determines the arithmetic mode of the ALUs operations
C16 = 0 The ALU operates in double-precision arithmetic mode.
C16 = 1 The ALU operates in dual 16-bit arithmetic mode.
SXM Sign-extension mode bit - 1bit
Determines whether sign extension is performed
SXM = 0 Sign extension is suppressed. SXM = 1 Data is sign extended before
being used by the ALU.

Status register 1 (ST1) cont

OVM Overflow mode bit - 1 bit
Determines what is loaded into the destination accumulator for overflow.
OVM = 0 An overflowed result from either the ALU or the multipliers adder
overflows normally in the destination accumulator.
OVM = 1 The destination accumulator is set to either the most positive value
(00 7FFFFFFFh) or the most negative value (FF 8000 0000h) upon encountering an
overflow.
0 Always read as 0.
INTM Interrupt mode bit 1 bit
INTM globally masks (disables) or enables all interrupts.
INTM = 0 All unmasked interrupts are enabled.
INTM = 1 All maskable interrupts are disabled.
HM 0 Hold mode bit - 1 bit
HM indicates whether the processor continues internal execution when
acknowledging an active HOLD signal.
HM = 0 The processor continues execution from internal program memory but
places its external interface in the high-impedance state.
HM = 1 The processor halts internal execution.
XF XF status bit 1 bit
XF indicates the status of the external flag (XF) pin, which is a general purpose
output pin.

Status register 1 (ST1) cont

CPL Compiler mode bit 1 bit
CPL indicates which pointer is used in relative direct addressing
CPL = 0 The relative direct-addressing mode using the data page pointer
(DP) is selected.
CPL = 1 The relative direct-addressing mode using the stack pointer (SP)
is selected.
BRAF Block-repeat active flag bit 1 bit
BRAF indicates whether a block repeat is currently active.
BRAF = 0 The block repeat is deactivated. BRAF is cleared when the
block-repeat counter (BRC) decrements below 0.
BRAF = 1 The block repeat is active. BRAF is automatically set when an
RPTB instruction is executed.

Processor Mode Status register (PMST)

Only on the LP devices; reserved bits on all other devices

SST - Saturation on store bit 1 bit

When SST 1, saturation of the data from the accumulator is enabled
before storing in memory.
The saturation is performed after the shift operation.
SMUL - Saturation on multiplication bit 1 bit
When SMUL = 1, saturation of a multiplication result occurs before
performing the accumulation in a MAC or MAS instruction.
CLKOFF - Clock out off 1 bit
When the CLKOFF bit is 1, the output of CLKOUT is disabled and remains
at a high level.
DROM On-chip Data ROM selection bit 1 bit
DROM enables on-chip ROM to be mapped into data space.
The values for the DROM bit are:
DROM = 0 The on-chip ROM is not mapped into data space.
DROM = 1 A portion of the on-chip ROM is mapped into data space.

Processor Mode Status register (PMST) cont

Only on the LP devices; reserved bits on all other devices

AVIS - Address visibility mode bit 1 bit

AVIS enables/disables the internal program address to be visible at the
address pins.
AVIS = 0 The external address lines do not change with the internal
program address. Control and data lines are not affected and the address
bus is driven with the last address on the bus.
AVIS = 1 This mode allows the internal program address to appear at the
pins of the 54x so that the internal program address can be traced.
OVLY - On-chip RAM overlay bit 1 bit
OVLY enables on-chip dual-access data RAM blocks to be mapped into
program space.
The values for the OVLY bit are:
OVLY = 0 The on-chip RAM is addressable in data space but not in
program space.
OVLY = 1 The on-chip RAM is mapped into program space and data space.

Processor Mode Status register (PMST) cont

Only on the LP devices; reserved bits on all other devices

MP/MC Microprocessor/Microcomputer mode pin 1 bit

MP/MC enables/disables the on-chip ROM to be addressable in program
memory space.
MP/MC = 0 The on-chip ROM is enabled and addressable.
MP/MC = 1 The on-chip ROM is not available
IPTR - Interrupt vector pointer 9 bits
The 9-bit IPTR field points to the 128-word program page where the
interrupt vectors reside.
You can remap the interrupt vectors to RAM for boot-loaded operations.

Conditional Instructions
Instructions in a processor can be divided in to two categories
Unconditional instructions
Conditional instructions
Unconditional instructions
Arithmetic and logic instructions ADD, SUB, MPY, OR, AND etc.
Unconditional control instructions branch, call and return.
Syntax B loop , CALL sine, RET
Conditional instructions
These instructions are executed based on certain logical conditions
How the logical conditions are defined in processors?
Based on the content of accumulator
EQ (equal to 0)
NEQ (not equal to 0)
GT (greater than 0)
LT (less than 0)
GEQ (greater than or equal to 0) LEQ (less than or equal to 0)
Based on the flags
OV (over flow)
NOV (no over flow)
C (carry)
NC (no carry)
TC (test control true)
NTC (test control false)
Based on hardware pin
BIO (BIO signal low)
NBIO (BIO signal high)

10

Conditional Instructions cont

Types of Conditional instructions
1. General conditional instructions
2. Multiple conditional instructions
3. Delayed conditional instructions
4. Execute conditional instructions
1. General conditional instructions
These instructions are execute only when the specified conditions are met.
Syntax BC EQ, loop - branch to the label loop, if the content of
accumulator is equal to zero
CC GEQ, sine - call the function sine, if the content of
accumulator is greater than or equal to zero
RC NC - return to the main program, if there is no carry

2. Multiple conditional instructions

More than one condition is specified in the instruction. If all the specified
conditions are met, then the instruction is executed.
Syntax BC EQ, C loop - branch to the label loop, if the content of
accumulator is equal to zero and carry bit is set.

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Conditional Instructions cont

2.

Multiple conditional instructions

How many conditions can be specified?
It depends on the grouping of the logical conditions in the processor.
Example In `C54X the conditions are grouped in two groups
The conditions that are used
should not be from the same
group
With in the group, they should
not be from the same category

3. Delayed conditional instructions

Delayed conditional instructions are used to avoid pipeline conflicts
Two one word instructions or one two word instruction below the delayed
conditional instruction is executed before branching (for 4 level pipeline)
Syntax BCD EQ, loop - branch to the label loop, if the content of
ST A,10h
accumulator is equal to zero after executing two
ADD *ar2,A
instructions below the branch

12

Conditional Instructions cont

4. Execute conditional instructions
When conditional branches to skip over 1- or 2-word code segment,
the branch can be replaced with a 1-cycle conditional execute instruction
(XC).
There are two forms for the XC instruction.
One form is a conditional execute of a 1- word instruction (XC 1, cond).
The second form is a conditional execute of one 2-word instruction or
two 1-word instructions (XC 2, cond).
Far conditional instructions
In `C54X the PM can be extended to 23 bits.
The program counter can be extended by 7 bits with XPC register
For the extended Program memory far conditional instructions are used
Syntax FB [D]
- far branch
FCALL [D] - far call
FRET [D]
- far return
Conditional store instructions
Some CPU registers can be conditionally stored in data memory using the
conditional store instructions
Syntax SACCD store accumulator A or B
STRCD store temporary register T
SRCCD store BRC register

13

Repeat Instructions and Repeat Hardware

Repeat instructions are used to execute instructions N times with out
instruction over head
DSPs have two types of repeat instructions
RPT
single instruction repeat
RPTB
block instruction repeat
To execute repeat instructions a repeat hardware is used
Hardware details
Registers
PASR/RSA program start address
register
PAER/REA program end address
register
RPTC repeat counter register
BRCR block repeat count register
Flags
S flag - single repeat flag
BRAF - block repeat active flag in (ST1)

14

Repeat Instructions and Repeat Hardware cont

Block repeat operation Syntax
RPTB loop
instruction 1
:
loop
instruction N

15

Block repeat operation with example

The number of time the block is to be repeated
is loaded in BRCR register
The block is repeated N+1 times the valued
loaded in BRCR
Example
LD # 9h, BRCR
RPTB loop
ADD *ar2, A
ADD *ar3,B
MPY #10h, A
loop MPY #15h,B
When RPTB instruction is decoded the BRAF flag
bit in ST1 is set 1.
The repeat hardware is operational.
The program word fetched is End address of the
block i.e. load in PAER
The current content of PC is the start address of
block i.e. loaded in PASR
The content of PC is compared with PAER, if it is
false, increment PC. If it is true one time block
repeat is over, reload PASR in PC.
On execution of instructions in the block, BRCR
decrements.For BRCR = 0 hardware stops. BRAF =0

Repeat Instructions and Repeat Hardware cont

Single repeat operation Syntax
RPT #N
Instruction

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Single repeat operation with example

The single instruction below the RPT instruction
is executed N+1 times.
Example
RPT #9h
MPY *AR2+, A
When RPT instruction is decoded the S flag set 1.
The repeat hardware is operational.
The program word fetched is count value (N) loaded
in RPTC register
The PAER and PASR are same i.e. the content of PC
The same instruction address is sent to PM.
On execution of the instruction every time RPTC

decrements. For RPTC = 0 the hardware stops, S=0

The maximum number of times the single

instruction repeat and block repeat executed is
65536.

Interrupts

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What is an interrupt?
Interrupt is a signal (to be of any form) which is used to establish data transfer
between CPU and other devices.
What are the different types of interrupts?
Interrupts

External
Interrupts

Hardware
Interrupts

Internal
Interrupts

Software
Interrupts

NonMaskable
Nonmaskable
maskable

Maskable

Hardware
Interrupts

Nonmaskable

Maskable

Software
Interrupts

Nonmaskable

Maskable

1. All external
Interrupts are
hardware initiated
2. Internal interrupts
are initiated by both
hardware and
software
3. Only external
interrupts are Nonmaskable
4. All Internal
interrupts are
maskable

Interrupts cont
Interrupts in DSPs
External- Hardware initiated Non-maskable interrupts RS and NMI
RS Reset (hardware reset) - Program execution stops, all registers initialized to original value
NMI Non-maskable interrupt Program execution stops, register contents are not affected
External- Hardware initiated maskable interrupts INT0, INT1,INT2, INT3
INT0 External user interrupt 0
INT 1 External user interrupt 1
INT 2 External user interrupt 2
INT 3 External user interrupt 3
Internal- Hardware initiated maskable interrupts
All on-chip peripherals have interrupts
TINT Timer interrupt
XINT Serial port transmit interrupt
RINT Serial port receive interrupt
HINT Host port interface interrupt
Internal- software initiated maskable interrupts
INTR, TRAP

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Interrupts cont

Maskable and Non-Maskable Interrupts

Maskable interrupts are the interrupts that can be enabled and disabled by the
user with the help of interrupt maskable register (IMR) by programming.
Non-maskable interrupt have no registers to enable or disable.
For all the maskable interrupts in a processor, a bit is assigned in the IMR
register.
The list of maskable interrupts in a processor can be known from the IMR
register.
The format of IMR in `C54X (`C541)

The format of Interrupt Flag Register (IFR)

The occurrence of the interrupt to the processor will set 1 the corresponding
bit in IFR until the CPU recognize the interrupt
The format of IFR is same as IMR

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Priority of interrupts
Interrupt location and priority table (`C541)

The non-maskable interrupts

have highest priority
Next priority is for external
hardware initiated maskable
interrupts
Next is priority is for internal
hardware initiated maskable
interrupts
The positions for the maskable
interrupts in IMR & IFR is
based on their priorities
Interrupt number is important
for interrupt vector address
generation

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Interrupt Programming
What is interrupt Programming?
Writing the interrupt service routing (ISR) for each and every interrupt and
storing them in the interrupt service routine address (ISRA) generated by the
processor.
How the interrupt service routine address is generated?
The interrupt-vector address is generated by concatenating the interrupt
vector pointer (IPTR) field of the PMST with the interrupt-vector number
(031) shifted by 2.

Example: Let IPTR = 01, the interrupt number for INT0 is 16 (10h)
The ISRA generated for INT0 is concatenating IPTR (01h) with (10h)
left shifted by two.
we get ISRA as 00C0h
The number of address locations allotted for each interrupt is four
By changing the IPTR, ISRA generated can be made access any block of
Program memory

21

Interrupt Programming cont

ISRA generated by the processor has only four PM locations for each interrupt.
ISR needs more than four memory locations.

In the locations of PM pointed by ISRA has instructions (branch) to point to the

starting address of the PM where the actual ISR is present for the interrupt.

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Maskable Interrupt enable/disable

23

After interrupt programming , it is important to enable the maskable interrupts

using IMR.
The CPU recognizes the interrupts and generates ISRA, if and only if the
corresponding bit in IMR is set 1 enabled
To enable the interrupts a proper control word is to be loaded in IMR
While loading a control word in IMR, the processor should not process any
interrupts or there should not be any pending interrupts.
This can be ascertained by INTM bit in status register.
Example Assume that for a serial port communication INT1 , XINT and RINT
interrupts are used
The corresponding bits in IMR are set 1
Now the control word to be loaded in IMR to enable these three
interrupts is 0032h

Program to enable interrupts

SET INTM - mask/disable globally the maskable interrupts
LD #32h, IMR load control word to enable serial port interrupts
CLR INTM unmask/enable globally the maskable interrupts

Interrupt Processing/Operation

24

Once an interrupt has been passed to the CPU, the CPU operates in the
following manner
Maskable Interrupts:
1. The corresponding bit in the IFR is set 1, this gives the information to CPU
that interrupt has occurred.
2. Check for the conditions INTM = 0 and the corresponding bit in IMR =1, the
acknowledgment conditions are tested.
3. If the conditions are true, the CPU acknowledges the interrupt, generating
an IACK signal; otherwise, it ignores the interrupt and continues with the
main program.
4. When the interrupt has been acknowledged, its flag bit in the IFR is cleared
to 0 The INTM bit is set 1 (to block other maskable interrupts).
5. ISRA is generated by the CPU with IPTR value and interrupt number
6. The PC is saved on the stack by PUSH operation and ISRA is loaded in PC
7. The CPU branches to and executes the interrupt service routine (ISR).
8. The ISR is concluded by a return instruction, which pops the return address
off the stack.
10. The CPU continues with the main program till next time IFR is set.

Interrupt Processing/Operation cont

25

Non-maskable Interrupts:
1. The CPU immediately acknowledges the interrupt, generating an IACK
signal.

2. If the interrupt was requested by RS, NMI, or the INTR instruction, the the
INTM bit is set to 1 to block maskable hardware interrupts.
3. If the INTR instruction has requested one of the maskable interrupts, the
corresponding flag bit is cleared to 0.
4. The PC is saved on the stack.

5. The CPU branches to and executes the ISR.

6. The ISR is concluded by a return instruction, which pops the return address
of the stack.

7.

The CPU continues with the main program

Interrupt context save and retrieve

When an interrupt service routine is executed, certain CPU registers must be

saved automatically.
Accumulators, Auxiliary register compare register (ARCR), Index register (INDX)
Product register (PREG), Status registers, Temporary registers

There are two ways to do interrupt context save and retrieve

Hardware stack - 1 level deep stack (Shadow registers)
When the interrupt trap is taken, the contents of all these registers are
pushed onto a 1-level stack.
The values in the registers at the time of the interrupt trap are still
available to the ISR but are also protected in the shadow registers.
The shadow registers are copied back to the CPU registers when the
return instruction is executed.
This function allows the CPU to be used for the ISR without requiring
context save and restore overhead in the ISR.
With only a 1-level stack for the registers, nested interrupts cannot be
supported.
Software Stack
When the interrupt trap is taken, the contents of all these registers are
stored in data memory using stack pointer.
When the return instruction is executed software code restores the
contents of these registers.

26

Interrupt latency
Interrupt latency is defined as the number of clock cycle delay from the clock
cycle the interrupt occurred to the interrupts service routine get executed.
What is minimum latency?
For a 4 level pipelined system the minimum latency is 8 clock cycles
3 cycles to execute instructions in the pipeline before executing a
software vector.
1 cycle for the interrupt to be recognized by the CPU
4 cycles to execute the interrupt instruction and flush the pipeline
The minimum latency depends on the number of pipeline stages and the
number of clock cycle required for the CPU to recognize.
What is maximum latency?
The maximum interrupt latency depends on the type of instructions in the
pipeline.
Instructions such as repeat, branch, call which are in the pipeline are to be
completely executed before recognizing the interrupt.

27

Power down modes

28

In power down mode the processor enters a dormant state and dissipates less
power than in the normal mode while maintaining the CPU contents
How to invoke power down mode?
The power-down mode can be invoked by executing the IDLE 1, IDLE 2 or
IDLE 3 instructions.
By driving the HOLD signal low with the HM status bit set to 1.
IDLE1
The IDLE1 mode halts all CPU activities except the system clock.
The system clock is applied to the peripherals, the peripheral circuits
continue to operate.
The peripherals such as serial ports , timers etc can take the CPU out of its
power-down state.
IDLE2
The IDLE2 mode halts the on-chip peripherals as well as the CPU.
Power is significantly reduced because the device is completely stopped.
Since, the on-chip peripherals are stopped, they cannot be used to wake
up from IDLE2.
To terminate IDLE2, activate any of the external interrupt pins (RS, NMI, and
INTx) with a 10-ns minimum pulse.

Power down modes cont

IDLE3
IDLE3 is used for a complete shutdown of the processor.
The IDLE3 mode functions like IDLE2 but it also halts the PLL.
The IDLE3 state allows you to reconfigure the PLL externally if the system
requires to operate at a lower speed to save power.
In some architectures separate power down mode LOPOWER is available
which will operate the processor at a lower speed.
HOLD MODE
It enables to put the address, data, and control lines into the
high-impedance state.
Depending on the value of the HM bit, this mode is used to halt the CPU.

29

Pipeline operation

30

Basic pipeline operation 4 phases Fetch, Decode, Read and Execute

Name of the pipeline phase and operations performed in each phase
Name of
the phase

Operations performed

Hardware used

Fetch

The program counter address is send to PM

through PAB.
The Instruction word is read from that address and
reaches CPU through PDB and PC is incremented.

Control unit and

PB

Decode

The instruction fetched is decoded, know the

operation to be performed
Know the type of addressing mode
If address of the operand is to be generated, the
DM address is generated
ARU updates are performed

Control unit and

ARU

Read

The data memory address generated in decode

phase is send to DM through DAB.
The data is read from that address and reaches
CPU through DDB.

Control unit and

DB

Execute

Perform the operation

Data memory write is performed

All processing
blocks & DB(W)

Pipeline operation cont

31

Understanding Basic pipeline for various addressing modes

PM address Opcode
080 LD #10h,DP
081 LD #1000h,AR2
083 SUB 20h, B
084 NOP
085 ADD *AR2+,A
086 NOP
087 ST A, *AR2+
088 LDM AR0,A

No. of clock
cycle

Fetch

Decode

Read

Execute

LD #10h,DP

LD

LD #10h,DP

1000h

LD

LD #10h,DP

SUB 20h, B

Dummy

LD

LD #10h,DP

NOP

SUB 20h, B

Dummy

LD

ADD *AR2+,A

NOP

SUB 20h, B

Dummy

NOP

ADD *AR2+,A

NOP

SUB 20h, B

ST A, *AR2+

NOP

ADD *AR2+,A

NOP

LDM AR0,A

ST A, *AR2+

NOP

ADD *AR2+,A

LDM AR0,A

ST A, *AR2+

NOP

LDM AR0,A

ST A, *AR2+

10
11
12

LDM AR0,A

Immediate one word activities in fetch, decode and execute

Immediate two word first word - activities in fetch, decode and execute
second word only fetch
Direct one word activities in fetch, decode , read and execute ARU not used
Indirect one word activities in fetch, decode, read and execute All blocks used
NOP only fetch

Pipeline operation cont

How the Basic pipeline phases are increased in `C54X to 6 level pipeline
Name of the
phase

Change in
phase

Operations performed

Program
prefetch

The program counter address is send to PM

through PAB.

Program
fetch

The Instruction word is read from that address and

reaches CPU through PDB and PC is incremented.

Decode

Decode

The instruction fetched is decoded, know the

operation to be performed
Know the type of addressing mode
If address of the operand is to be generated, the
DM address is generated
ARU updates are performed

Read

Access

The data memory address generated in decode

phase is send to DM through CAB.
CAB and DAB used for dual access,
EAB used for write

Read

The data is read from that address and reaches

CPU through DDB.
Both CDB and DDB used for dual access

Execute

Perform the operation

Data memory write is performed, EDB is used for write

Fetch

Execute

32

Pipeline conflicts

33

Branch instruction in the pipeline

Clk
Cycle

Operation performed

The PAB is loaded with the address of a

branch instruction.

Two words of the branch instruction are

fetched. Third word address loaded in PAB

3
Clk
cycle

Pre
fetch

PAB=a1

PAB=a2

PB=B

PAB=a3

PB=b1

IR = B

PAB=a4

PB=i3

IR = b1

Dummy

PAB=b1

PB=i4

Dummy

Dummy

Dummy

PB=j1

Dummy

Dummy

Dummy

IR = j1

Dummy

Dummy

b1

dummy

dummy

dummy

dummy

dummy

6
7
8

9
10

Fetch

Decode

Access

Read

Execute

j1

7
8

9
10

Two more instructions, i3 and i4, are

fetched.
These two instructions after the branch
instruction, i3 and i4, are not allowed to
move past the decode stage and are
eventually discarded.
After the second word of the branch
instruction (represented by b1) is
decoded, PAB is loaded with this new
value.

The two-word branch instruction enters

the execution stage of the pipeline
Also, j1 is fetched from address b1
These cycles are also consumed by the
same branch instruction since the next
two instructions, i3 and i4, were not
allowed to complete their execution; this is
why a branch instruction takes four cycles
to execute
j1 completes execution

Pipeline conflicts cont

Delayed Branch instruction in the pipeline

Clk
cycle

Pre
fetch

PAB=a1

PAB=a2

PB=B

PAB=a3

PB=b1

IR = B

PAB=a4

PB=i3

IR = b1

Dummy

PAB=b1

PB=i4

IR = i3

Dummy

Dummy

PB=j1

IR = i4

i3

Dummy

IR = j1

i4

i3

b1

dummy

i4

i3

dummy

i4

6
7
8

9
10

Fetch

Decode

Access

Read

Execute

j1

In delayed branch, the

pipeline behaves in the same
manner as it is for the
regular branch instruction.
The two instructions
following the branch, i3 and
i4, are allowed to complete
their execution.
Therefore, only cycles 6 and
7 are consumed by the
delayed-branch instruction
This makes the delayed
branch into a 2-cycle
instruction

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Pipeline conflicts cont

Other Pipeline conflicts
Due to the number of on-chip buses
MMREG access followed by Indirect addressing - simple Harvard
Write instruction followed by dual operand read - modified Harvard
Due to memory

On-chip memory
Write followed by dual operand access due to DARAM
If a dual-access memory block is mapped in both program and data
spaces, an instruction fetch will conflict with a data operand read
access if they are performed on the same memory block.
Off-chip memory
One set of external address and data buses, a bus conflict occurs
between instruction fetch (F), operand read (R), and execute (E) write
phases if program, data or both memory are external.

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Assignment 2 Question Weightage 5 Marks

36

1. Draw the detailed flow chart for single interrupt processing in

`C54X processor.
2. Draw the detailed flow chart for multiple interrupt processing in
`C54X processor.
3. List the various interrupts present in the processor that you
have selected in Assignment - 1

37

End of Part-4