Part - 6

On-chip peripherals and Interfacing

List of on-chip peripherals

Clock generator
Timer
Serial port
Buffered serial port (BSP)
Time-division multiplexed (TDM) serial port
Multi-channel buffered serial port (McBSP)
Parallel port
Software-programmable wait-state generator
DMA Controller
External memory interface (EMIF)
Host port interface (HPI)
On-chip peripherals are Programmable Peripheral Interface (PPI)
Hardware Programmable Clock generator
Software Programmable all other devices

Clock generator
The clock generator provides stable clock signal for the processor as well as
I/O devices
Clock generator consists of an internal oscillator and a phase lock loop (PLL)
circuit
Clock generator is hardware programmable device
It provides the flexibility for the system designer to select the clock source.
The clock generator is driven by a crystal resonator circuit or by an external
clock source.
The clock signal generated by internal oscillator circuit or obtained from
external source, is divide by two inside the chip

Clock generator pins

X1
X2/CLKIN

DSP chip

CLKMD1
CLKMD2
CLKMD3
CLK OUT

X1 Crystal oscillator pin1

X2 Crystal oscillator pin2 / External clock input pin
CLKMD1 CLKMD3 Mode select pins
CLK OUT Clock out put pin

Clock generator cont

Modes of operation
1. Internal mode
2. External mode
3. Hardware configurable PLL
Internal mode
An external crystal oscillator is connected
between pin X1 and X2.
The mode select pins are provided with +VDD [1].
The internal oscillator generates the clock signal
supply voltage is applied.
The internally generated clock signal is divided by
2 as system clock.
The frequency of oscillation of the external crystal
should be two time more than the system clockb
required.

X1
DSP Chip
X2
CLKMD1
CLKMD2
CLKMD3
CLK OUT

Crystal
Oscillator

+VDD [1]

Clock generator cont

External mode
X1

No Connection

X2

External Clock input

DSP Chip

CLKMD1
CLKMD2
CLKMD3

+GND [0]
+GND [0]
+VDD [1]

CLK OUT

The external clock signal is fed to pin X2.

Pin X1 is open (not connected)
The mode select pins are provided with logic voltages [001].
The external clock signal is divided by 2 on-chip and used as system clock.
The frequency of the external clock signal should be two time more than the
system clock required.

Clock generator cont

Hardware configurable PLL

PLL functions with a lower external frequency source than the machine cycle
rate of the CPU.
This feature reduces high-frequency noise from a high speed switching clock.
The internal oscillator or the external clock source is fed into the PLL and it is
multiplied by a factor N .
If you are using the internal oscillator circuit, the clock source is divided by 2
to generate the internal CPU clock.
If you are using the external clock, the internal CPU clock is a factor of N
(No need to divide by 2.

Timer

What is the use of timer?

Timer is used to generate low frequency clock signal for the low
speed peripheral devices from the CPU high frequency clock and
is used for synchronization.
What is the hardware used in timer?
Timer can be a programmable modulo N counter
The counter used in timer can be up or down counter
For the up counter logic, comparator and reset logic is used
For the down counter, check for zero and reload logic is used
On-chip timer
The on-chip timer is a software-programmable timer that consists
of Registers for programming
The number of on-chip timers may vary from processor to
processor
Each timer will have its own set of memory mapped registers for
programming.

`C54X on-chip Timer

`C54X timer is of 20 bit dynamic range
On-chip timer registers
The on-chip timer consists of three memory-mapped registers
1. Timer control register (TCR)
16-bit memory-mapped register (TCR) contains the control and status
bits of the timer.

TDDR - Timer divide-down ratio.

Specifies the timer divide-down ratio (period) for the on-chip timer.
TSS Timer start stop bit.
Stops or starts the on-chip timer
TRB - Timer reload bit
PSC - Timer pre-scaler counter.
Specifies the count for the on-chip timer
Free - Used in conjunction with the Soft bit to determine the state of the timer.
Free = 0 The Soft bit selects the timer mode.
Free = 1 The timer runs free regardless of the Soft bit.
Soft - Used in conjunction with the Free bit to determine the state of the timer
Soft = 0 The timer stops immediately
Soft = 1 The timer stops when the counter decrements to 0.

`C54X on-chip Timer cont

On-chip timer registers

2. Timer period register (PRD)
16-bit memory-mapped (PRD) is used to program the divide down count value of
the timer.
3. Timer register (TIM)/Timer counter register
16-bit memory-mapped (TIM) is loaded with the (PRD) value and decremented.
Timer block diagram and operation
Timer control register (TCR)

Timer consists of two set of counter and

register 4bit (TDDR &PSC), 16 bit (PRD & TIM)
Timer is clocked by CLKOUT of the processor

Timer programming
For the divide down count value less than 16, first set of counter is used and for divide
down count more than 16, either second set of counter or both counters can be used.

Serial port
Serial port interfaces provide full duplex, bidirectional, communication with
serial devices such as codecs, serial analog to digital (A/D) converters, and
other serial systems.
The serial port interface signals are directly compatible with many industrystandard codecs and other serial devices.
The serial port may also be used for inter-processor communication in
multiprocessing applications
Both receive and transmit operations are double-buffered, thus allowing a
continuous communications stream with either 8- or 16-bit data packets.
The maximum operating frequency for the standard serial port of one-fourth
of CLKOUT (10 Mbit/s at 25 ns, 12.5 Mbit/s at 20 ns) is achieved when using
internal serial port clocks.

Serial port pins

CLKR
CLKX

DSP chip

FSR
FSX
DR
DX

CLKR - Receive clock signal

CLKX - Transmit clock signal
FSR - Receive frame synchronization signal
FSX - Transmit frame synchronization signal
DR - Receive serial data
DX - Transmit serial data

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Serial port cont

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Serial port registers

Serial port operates through three MMREGs (SPC, DXR, and DRR) and
Two other registers (RSR and XSR),are not directly accessible to the program
All the registers are 16-bit size
SPC Serial Port Control register
DXR Data Transmit register
DRR Data receive register
XSR Data transmit shift register
RSR Data receive shift register
Serial port modes of operation
Burst mode
There are periods of serial port inactivity between packet transmits.
The data packet is marked by the frame sync pulse occurring on FSX

Continuous mode
In continuous mode, a frame sync on FSX/FSR is not necessary for consecutive packet
transfers at maximum packet frequency after the initial pulse.

Serial port cont

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Serial Port Control register (SPC)

DLB - Digital Loopback Mode. 0- disable 1- enable

FO - Format. Specifies the word length of the serial port transmitter and receiver, 0 16 bit, 1 8 bit
FSM - Frame Sync Mode. 0 Continuous mode, 1 Burst mode
MCM - Clock Mode. Specifies the clock source for CLKX. 0 CLKX is taken from CLKX pin,
1 - CLKX is driven by an on-chip clock source.
TXM - Transmit Mode. Configures the FSX pin as an input (TXM = 0) or as an output (TXM = 1).
XRST - Transmit reset
RRST - Receive reset
IN0 - CLKR used as input pin
IN1 - CLKX used as input pin
RRDY Receive ready
XRDY Transmit ready
XSREMPTY XSR empty
RSRFULL RSR full
Soft Used with Free bit. 0- stops immediately, 1 stops after completing transmission
Free Used with soft bit. 0- emulation mode, 1- serial port clock runs free regardless of the Soft bit

Serial port cont

Serial port block diagram and operation

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A transmit is initiated by writing data to the

DXR, which copies the data to the XSR.
The XSR manages shifting the data to the
DX pin, thus allowing another write to DXR
as soon as the DXR-to-XSR copy is
completed.
During transmits, upon completion of the
DXR-to-XSR copy, a 0-to-1 transition occurs
on the transmit ready (XRDY) bit in the SPC.
This 0-to-1 transition generates a serial port
transmit interrupt (XINT) that signals that
the DXR is ready to be reloaded.
The process is similar in the receiver.
Data from the DR pin is shifted into the
RSR, which is then copied into the DRR
from which it may be read.
Upon completion of the RSR-to-DRR copy,
a 0-to-1 transition occurs on the receive
ready (RRDY) bit in the SPC.
This 0-to-1 transition generates a serial port
receive interrupt (RINT).

Serial port Interface - TLC320C40 audio codec

TLC320C40 and TLC320C41 are single
monolithic CMOS chips consisting of
14-bit resolution A/D and D/A converters
and four microprocessor compatible
serial port modes.
It has two analog inputs , which can be
selected by a multiplexer
It has switched capacitor band pass antialiasing filter at the input side and
switched capacitor low pass filter for
reconstruction at the output side.
The sampling rate and the conversion rate
of the A/D and D/A can be programmed
Sampling and conversion rates vary from
4KHz to 19.2 KHZ
The two differential amplifiers at the
output are used to amplify the
reconstructed output.
The codec has on-chip programmable
serial port. It can be programmed to
transmit and receive the synchronously
as well as asynchronously

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Serial port Interface cont

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The master clock (MSTR CLK) for the

codec is generated from DSP timer
On providing the master clock, the shift
clock (SHIFT CLK) signal is generated
by dividing MSTR CLK by 4
The shift clock is used as clock transmit
and receive for the on-chip serial device
in DSP

Serial port initialization program steps

1. On-chip timer programming for the generation of clock
It depends on the serial data transfer rate (bits/sec). The serial data transfer rate decide the shift
clock frequency. The master clock frequency is 4 times that of shift clock. The divide down
ratio for the timer is ratio of CPU clock rate divided by the master clock frequency.
2. Reset the on-chip serial port
By loading the control word in SPC with XRST and RRST bits active will reset the serial port
3. Programming the on-chip serial port
A control word to be loaded in SPC to decide the mode of operation of the serial port. Bit size,
Burst or continuous mode, clocking, synchronization etc.
4. Reset the external codec circuit
The external codec reset pin is connected to XF pin of DSP. The reset timing for codec is 0.5
msec. The XF pin can be made active low for 0.5 msec. and made active high after reset.
5. Programming the external device serial port
The control words for the external serial device can be transmitted using secondary
communication from DSP to codec.

Parallel port
Parallel port pins
CLKOUT
PS/ DS/ IS
A15-A0
D15-D0
R/W
RD
WE
STROBE

- CPU Clock output

- Program/ Data / I/O space select
- Address lines
- Data lines
- Read/Write enable
- Read data
- Write data
- Strobe signal

CS
EN
A15-A0
D15-D0
RD
WE

- Chip select
- Data bus direction enable
- Address lines
- Data lines
- Read enable
- Write enable

Memory pins

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Parallel port timing diagram

Parallel port write timing diagram
Write timing 2 clock cycles

Write timing is 2 clock cycles

On the leading edge of PS/DS/IS and R/W the address is on the address bus
Half clock cycle to select the address
After half clock cycle, the write enable is active for one clock cycle
On the leading edge of write enable the data is on the data bus for one clock cycle
Strobe is used extend the write timing to more than two clock cycles

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Parallel port timing diagram cont

Parallel port read timing diagram
Read timing 1 clock cycle

Read timing is 1 clock cycle

On the leading edge of PS/DS/IS and R/W the address is on the address bus
Half clock cycle to select the address
After half clock cycle, the read enable is active for half clock cycle
On the leading edge of read enable the data is on the data bus for half clock cycle
Strobe is used extend the write timing to more than two clock cycles

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Parallel interface External memory interface

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External data memory interface

Case 1 64Kx 16 bit memory data space
Case 2 64Kx 16 bit memory program space
Case 3 64Kx 16 bit memory I/O space
Case 4 64K x 16 bit memory all space
Case 5 64Kx 8 bit memory interface
Case 6 32K x 16 bit memory interface
Case 7 Two 16K x 16 bit memory interface
For 64K x 16 bit memory DSP and memory buses are directly connected.
If the speed of memory is slower, then software programmable wait state generator is
used to introduce wait states to a maximum of 7 clock cycles for PM, DM and I/OM
spaces.
For 64K x 8 bit memory two 64K x 8 bit memory chips are connected in parallel, with 8
LSB bits of data line connected to chip 1 & MSB 8 bits of data line connected to chip 2.
For memory space less than 64Kx 16 bits, memory chip select is signal is activated with
the help of decoding gates, designed with inputs from MSB bits of address lines and
PS/DS/IS signals

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End of Part-6