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INTRODUCTION
87
TABLE II
COMPARISON OF TRANSISTOR COUNT OF GDI AND
STATIC CMOS
TABLE I
BASIC FUNCTIONS USING GDI CELL
FUNCTION
INVERTER
F1
F2
OR
GDI
2
2
2
2
CMOS
2
6
6
6
AND
MUX
XOR
XNOR
NAND
NOR
2
2
4
4
4
4
6
12
16
16
4
4
OUTPUT
FUNCTION
INVERTER
AB
F1
A.
A+B
F2
A+B
OR
AB
AND
AB+AC
MUX
AB+BA
XOR
TABLE III
AB+AB
XNOR
Digital Circuits
B. 8-bit Comparator
88
TABLE IV
Logic Style
CMOS
GDI
N-PG
Power(in mW)
1.82
1.4
13.87
Number of
transistor
96
96
96
C. 4-bit Multiplier
The multiplier is implemented using 0.5m CMOS
technology with 3.3V supply voltage. Comparison
results are shown in table V. 26 transistors are used in
GDI technique while 44 Transistors are used in standard
CMOS.
VI. CONCLUSION
A novel GDI technique for low-power design was
presented. Comparisons with existing TG and N-PG
techniques were carried out, showing an up to 45%
reduction of power-delay [7] product in the test chip in
GDI over CMOS and significant improvements in
performance. GDI will allow high density of Fabrication
as now a days chip area is very important parameter [3,
6]. The GDI technique allows use of a simple and
efficient design algorithm, based on the Shannon
expansion. It makes GDI suitable for synthesis and
realization of combinatorial logic in real LSI chips,
while using a single-cell library. This proves to be an
additional advantage of GDI over CMOS and PTL.
Implementations of GDI circuits in SOI or twin-well
CMOS processes are expected to supply more powerdelay efficient design, due to the use of a complete cell
library with reduced transistor count.
TABLE V
COMPARISON OF GDI, CMOS 4-BIT MULTIPLIER
Logic Style
CMOS
GDI
Power(in mW)
1.265
0.3079
Number of Transistors
44
26
D. XOR Gate
XOR Gate is implemented using 180nm technology
and the comparison is done among Complementary Pass
Transistor Logic (CPL), Dual Pass Transistors (DPL),
standard CMOS and GDI Techniques and results are
mentioned in table. Among all the implemented
techniques GDI consumes least power and the least
number of transistors. 23.93 micro Watts is consumed
by standard CMOS, power consumed by different
techniques is mentioned with respect to standard CMOS
technique.
TABLE VI
COMPARISON OF GDI, CMOS, CPL AND DPL XOR
GATE
Logic Style
CMOS
CPL
DPL
GDI
Percentage
Power
Consumed
with respect
to CMOS
Number of
Transistor
100
107.35
43.96
27.12
16
10
(A)
OUTPUT OF F1
89
(C)
OUTPUT OF F2
(F)
REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
.
(E)
90
GDI
CMOS
FIG. 3(A)
FIG. 3(B)
FIG. 3(C)
FIG. 3(D)
FIG. 3(E)
FIG. 3(F)
INVERTER
OR
AND
91
NOR
FIG.3(G)
FIG.3(H)
FIG.3(I)
FIG.3(J)
FIG.3(K)
FIG.3(L)
XOR
XNOR
92
NOR
FIG.3(M)
FIG.3(N)
FIG.3(O)
FIG.3(P)
NAND
93