1.

5 On Resistance,
15 V/12 V/5 V, 4:1, iCMOS Multiplexer
ADG1404
FEATURES

FUNCTIONAL BLOCK DIAGRAM

1.5 on resistance
0.3 on-resistance flatness
0.1 on-resistance match between channels
Up to 400 mA continuous current
Fully specified at +12 V, 15 V, and 5 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
14-lead TSSOP and 4 mm 4 mm, 16-lead LFCSP

ADG1404
S1
S2

S3
S4

A0

A1

EN

06816-001

1 OF 4
DECODER

Figure 1.

APPLICATIONS
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Communication systems
Relay replacement

GENERAL DESCRIPTION
The ADG1404 is a complementary metal-oxide semiconductor
(CMOS) analog multiplexer, comprising four single channels
designed on an iCMOS process. iCMOS (industrial CMOS) is
a modular manufacturing process that combines high voltage
CMOS and bipolar technologies. It enables the development of
a wide range of high performance analog ICs capable of 33 V
operation in a footprint that no previous generation of high
voltage parts has been able to achieve. Unlike analog ICs using
conventional CMOS processes, iCMOS components can
tolerate high supply voltages while providing increased
performance, dramatically lower power consumption, and
reduced package size.
The on-resistance profile is very flat over the full analog input
range, ensuring excellent linearity and low distortion when
switching audio signals.

The ADG1404 switches one of four inputs to a common output,

D, as determined by the 3-bit binary address lines, A0, A1, and
EN. Logic 0 on the EN pin disables the device. Each switch
conducts equally well in both directions when on and has an
input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. All switches
exhibit break-before-make switching action. Inherent in the
design is low charge injection for minimum transients when
switching the digital inputs.

PRODUCT HIGHLIGHTS
1.
2.
3.
4.

2.6 maximum on resistance over temperature.

Minimum distortion.
Ultralow power dissipation: <0.03 W.
14-lead TSSOP and 16-lead, 4 mm 4 mm LFCSP package.

iCMOS construction ensures ultralow power dissipation,

making the parts ideally suited for portable and batterypowered instruments.

Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 20082009 Analog Devices, Inc. All rights reserved.

ADG1404
TABLE OF CONTENTS
Features .............................................................................................. 1

Continuous Current, S or D.........................................................6

Applications ....................................................................................... 1

Absolute Maximum Ratings ............................................................7

Functional Block Diagram .............................................................. 1

ESD Caution...................................................................................7

General Description ......................................................................... 1

Pin Configurations and Function Descriptions ............................8

Product Highlights ........................................................................... 1

Truth Table .....................................................................................8

Revision History ............................................................................... 2

Typical Performance Characteristics ..............................................9

Specifications..................................................................................... 3

Terminology .................................................................................... 12

15 V Dual Supply .......................................................................... 3

Test Circuits ..................................................................................... 13

12 V Single Supply ........................................................................ 4

Outline Dimensions ....................................................................... 16

5 V Dual Supply ............................................................................ 5

Ordering Guide .......................................................................... 16

REVISION HISTORY
3/09Rev. 0 to Rev. A
Changes to Power Requirements, IDD, Digital Inputs = 5 V
Parameter, Table 1............................................................................. 3
Changes to Power Requirements, IDD, Digital Inputs = 5 V
Parameter, Table 2............................................................................. 4
Updated Outline Dimensions ....................................................... 16
7/08Revision 0: Initial Version

Rev. A | Page 2 of 16

ADG1404
SPECIFICATIONS
15 V DUAL SUPPLY
VDD = 15 V 10%, VSS = 15 V 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On-Resistance Match
Between Channels (RON)
On-Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)

25C

40C to +85C

40C to +125C

Unit

VDD to VSS

V
typ

1.5
1.8
0.1

2.3

2.6

max
typ

0.18
0.3
0.36

0.19

0.21

0.4

0.45

max
typ
max
nA typ

12.5

Drain Off Leakage, ID (Off)

nA max
nA typ

30

Channel On Leakage, ID, IS (On)

0.55
0.1

nA max
nA typ

30

nA max

2.0
0.8

V min
V max
A typ
A max
pF typ

0.005
0.1

Digital Input Capacitance, CIN

DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tBBM

VS = 10 V, IS = 10 mA; see Figure 22

VDD = +13.5 V, VSS = 13.5 V
VS = 10 V, IS = 10 mA

VS = 10 V, IS = 10 mA
VDD = +16.5 V, VSS = 16.5 V

0.03
0.55
0.04

DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINLor INH

Test Conditions/Comments

3.5

VS = 10 V, Vs = 10 V; see Figure 23
VS = 10 V, Vs = 10 V; see Figure 23
VS = VD = 10 V; see Figure 24

VIN = VGND or VDD

150
180

220

250

ns typ
ns max

100
120

145

165

ns typ
ns max

110
135

165

185

ns typ
ns max

10

ns typ
ns min

RL = 300 , CL = 35 pF
VS = +10 V; see Figure 29
RL = 300 , CL = 35 pF
VS = +10 V; see Figure 31
RL = 300 , CL = 35 pF
VS = +10 V; see Figure 31
RL = 300 , CL = 35 pF
VS1 = VS2 = 10 V; see Figure 30
VS = 0 V, RS = 0 , CL = 1 nF; see Figure 32

35

Charge Injection

20

pC typ

Off Isolation

70

dB typ

RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 25

Channel-to-Channel Crosstalk

82

dB typ

Total Harmonic Distortion + Noise

0.011

% typ

RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 27

RL = 110 , 10 V p-p, f = 20 Hz to 20 kHz; see

3 dB Bandwidth

55

MHz typ

RL = 50 , CL = 5 pF; see Figure 26

Insertion Loss

0.17

dB typ

23
90
170

pF typ
pF typ
pF typ

RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 26

f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
VDD = +16.5 V, VSS = 16.5 V
Digital inputs = 0 V or VDD

Figure 28

CS (Off)
CD (Off)
CD, CS (On)
POWER REQUIREMENTS
IDD

0.001
1

IDD

170
285

ISS

0.001

VDD/VSS
1

1
4.5/16.5

Guaranteed by design, not subject to production test.

Rev. A | Page 3 of 16

A typ
A max
A typ
A max
A typ
A max
V min/max

Digital inputs = 5 V
Digital inputs = 0 V or VDD
GND = 0 V

ADG1404
12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On-Resistance Match
Between Channels (RON)
On-Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH

25C

2.8
3.5
0.13
0.21
0.6
1.1
0.02
0.55
0.03
0.55
0.1
1.5

40C to +85C

40C to +125C

Unit

Test Conditions/Comments

0 V to VDD

V
typ
max
typ

VS = 0 V to 10 V, IS = 10 mA; see Figure 22

VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = 10 mA

4.3

4.8

0.23

0.25

1.2

1.3

12.5

30

30

2.0
0.8
0.001
0.1

Digital Input Capacitance, CIN

DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tBBM

3.5
230
300
180
240
115
160
100

375

430

295

335

190

220
10

Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD, CS (On)
POWER REQUIREMENTS
IDD

30
80
82
35
0.3
39
150
217
0.001
1

IDD

170

VDD
1

285
5/16.5

Guaranteed by design, not subject to production test.

Rev. A | Page 4 of 16

max
typ
max
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
A typ
A max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
dB typ
pF typ
pF typ
pF typ
A typ
A max
A typ
A max
V min/max

VS = 0V to 10 V, IS = 10 mA
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 23
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 23
VS = VD = 1 V or 10 V; see Figure 24

VIN = VGND or VDD

RL = 300 , CL = 35 pF
VS = 8 V; see Figure 29
RL = 300 , CL = 35 pF
VS = 8 V; see Figure 31
RL = 300 , CL = 35 pF
VS = 8 V; see Figure 31
RL = 300 , CL = 35 pF
VS1 = VS2 = 8 V; see Figure 30
VS = 6 V, RS = 0 , CL = 1 nF; see Figure 32
RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 25
RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 27
RL = 50 , CL = 5 pF; see Figure 26
RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 26
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
VDD = 13.2 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
GND = 0 V, VSS = 0 V

ADG1404
5 V DUAL SUPPLY
VDD = 5 V 10%, VSS = 5 V 10%, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On-Resistance Match
Between Channels (RON)
On-Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH

25C

3.3
4
0.13
0.22
0.9
1.1

40C to +85C

40C to +125C

Unit

Test Conditions/Comments

VDD to VSS

V
typ
max
typ

VS = 4.5 V, IS = 10 mA; see Figure 22

VDD = +4.5 V, VSS = 4.5 V
VS = 4.5 V, IS = 10 mA

4.9

5.4

0.23

0.25

1.24

1.31

VS = 4.5 V, VD = 4.5 V; see Figure 23

VS = 4.5 V, VD = 4.5 V; see Figure 23

0.2
0.02

12.5

nA max
nA typ

0.25
0.05
0.25

1.2

15

VS = VD = 4.5 V; see Figure 24

1.5

20

nA max
nA typ
nA max
V min
V max
A typ
A max
pF typ

VIN = VGND or VDD

2.0
0.8
0.001
35

Break-Before-Make Time Delay, tBBM

Charge Injection
Off Isolation

30
80

ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ

Channel-to-Channel Crosstalk

82

dB typ

3 dB Bandwidth
Insertion Loss
Total Harmonic Distortion + Noise

40
0.27
0.03

MHz typ
dB typ
% typ

33
128
210

pF typ
pF typ
pF typ

tOFF (EN)

560

615

430

480

365

400
50

CS (Off)
CD (Off)
CD, CS (On)
POWER REQUIREMENTS
IDD
ISS

0.001

RL = 300 , CL = 35 pF
VS = 3 V; Figure 29
RL = 300 , CL = 35 pF
VS = 3 V; Figure 31
RL = 300 , CL = 35 pF
VS = 3 V; Figure 31
RL = 300 , CL = 35 pF
VS1 = VS2 = 3 V; see Figure 30
VS = 0 V, RS = 0 , CL = 1 nF; see Figure 32
RL = 50 , CL = 5 pF, f = 100 kHz;
see Figure 25
RL = 50 , CL = 5 pF, f = 100 kHz;
see Figure 27
RL = 50 , CL = 5 pF; see Figure 26
RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 26
RL = 110 , 2.5 V p-p, f = 20 Hz to 20 kHz;
see Figure 28
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = 5.5 V, VSS = 5.5 V
Digital inputs = 0 V, 5 V, or VDD

A typ
A max
A typ
A max

Digital inputs = 0 V or VDD

4.5/16.5

V min/max

GND = 0 V

0.001

VDD/VSS
1

nA typ

340
470
260
355
220
315
100

tON (EN)

VS = 4.5 V, IS = 10 mA
VDD = +5.5 V, VSS = 5.5 V

0.02

0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION

max
typ
max

Guaranteed by design, not subject to production test.

Rev. A | Page 5 of 16

ADG1404
CONTINUOUS CURRENT, S OR D
Table 4.
Parameter
CONTINUOUS CURRENT, S or D1
15 V Dual Supply
ADG1404 TSSOP
ADG1404 LFCSP
12 V Single Supply
ADG1404 TSSOP
ADG1404 LFCSP
5 V Dual Supply
ADG1404 TSSOP
ADG1404 LFCSP
1

25C

85C

125C

Unit

350
450

220
300

100
140

mA max
mA max

300
400

220
300

100
140

mA max
mA max

300
400

220
300

100
140

mA max
mA max

Test Conditions/Comments
VDD = +13.5 V, VSS = 13.5 V

VDD = 10.8 V, VSS = 0 V

VDD = +4.5 V, VSS = 4.5 V

Guaranteed by design, not subject to production test.

Rev. A | Page 6 of 16

ADG1404
ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted.
Table 5.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs
Peak Current, S or D
Continuous Current, S or D2
Operating Temperature Range
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
14-Lead TSSOP, JA Thermal
Impedance (4-layer board)
16-Lead LFCSP, JA Thermal
Impedance
Reflow Soldering Peak
Temperature, Pb free
1

Rating
35 V
0.3 V to +25 V
+0.3 V to 25 V
VSS 0.3 V to VDD + 0.3 V or 30
mA, whichever occurs first
GND 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
600 mA (pulsed at 1 ms,
10% duty cycle maximum)
Data + 15%

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating may be applied at any
one time.

ESD CAUTION

40C to +125C
65C to +150C
150C
112C/W
30.4C/W
260(+0/5)C

Overvoltages at IN, S, and D are clamped by internal diodes. Current should

be limited to the maximum ratings given.
See data given in Table 4.

Rev. A | Page 7 of 16

ADG1404

12

VDD

VSS 3

ADG1404

NC 2
S1 3

TOP VIEW
11 S3
(Not to Scale)
10 S4

D 6

NC

NC 7

NC

NC = NO CONNECT

14 A1

13 NC

12 GND

ADG1404

11 VDD

TOP VIEW
(Not to Scale)

9 S4

NC 5

S2 5

S2 4

10 S3

NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, VSS.
2. NC = NO CONNECT.

06816-002

S1 4

PIN 1
INDICATOR

VSS 1

06816-003

GND

NC 8

A1

NC 7

14
13

D 6

A0 1
EN 2

15 A0

16 EN

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 3. LFCSP Pin Configuration

Figure 2. TSSOP Pin Configuration

Table 6. Pin Function Descriptions

TSSOP
1
2
3
4
5
6
7 to 9
10
11
12
13
14

Pin No.
LFCSP
15
16
1
3
4
6
2, 5, 7, 8, 13
9
10
11
12
14

Mnemonic
A0
EN
VSS
S1
S2
D
NC
S4
S3
VDD
GND
A1

Description
Logic Control Input.
Active High Digital Input. When this pin is low, the device is disabled and all switches are off.
When this pin is high, the Ax logic inputs determine the on switches.
Most Negative Power Supply Potential.
Source Terminal. Can be an input or an output.
Source Terminal. Can be an input or an output.
Drain Terminal. Can be an input or an output.
No Connection.
Source Terminal. Can be an input or an output.
Source Terminal. Can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input.

TRUTH TABLE
Table 7.
EN
0
1
1
1
1

A1
X
0
0
1
1

A0
X
0
1
0
1

S1
Off
On
Off
Off
Off

Rev. A | Page 8 of 16

S2
Off
Off
On
Off
Off

S3
Off
Off
Off
On
Off

S4
Off
Off
Off
Off
On

ADG1404
TYPICAL PERFORMANCE CHARACTERISTICS
2.5

3.0
VDD = +10V,
VSS = 10V

2.5

1.5

VDD = +13.5V,
VSS = 13.5V

1.0

VDD = +16.5V,
VSS = 16.5V

VDD = +15V,
VSS = 15V

0.5

TA = +85C
1.5

TA = +25C
TA = 40C

1.0

0.5
TA = 25C
IS = 10mA
12.5

8.5

4.5

0.5

3.5

11.5

7.5

15.5

VS OR VD (V)

Figure 4. On Resistance as a Function of VD (VS), Dual Supply

4.0

10

15

4.5

ON RESISTANCE ()

4.0

VDD = +7V,
VSS = 7V

VDD = +5.5V,
VSS = 5.5V

1.5

5.0

2.5
2.0

Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,

15 V Dual Supply

VDD = +5V,
VSS = 5V

3.0

10

VS OR VD (V)

VDD = +4.5V,
VSS = 4.5V

3.5

VDD = +15V
VSS = 15V
IS = 10mA

0
15

06816-004

0
16.5

ON RESISTANCE ()

TA = +125C

2.0

06816-007

VDD = +12V,
VSS = 12V
ON RESISTANCE ()

ON RESISTANCE ()

2.0

TA = +125C

3.5

TA = +85C

3.0
TA = +25C

2.5
2.0

TA = 40C

1.5

1.0
1.0

VS OR VD (V)

0
5

Figure 5. On Resistance as a Function of VD (VS), Dual Supply

VS OR VD (V)

Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,

5 V Dual Supply

4.5
VDD = 5V,
VSS = 0V

4.0

VDD = 10.8V,
VSS = 0V

VDD = 8V,
VSS = 0V

ON RESISTANCE ()

5
VDD = 12V,
VSS = 0V

3
2
VDD = 13.2V,
VSS = 0V

TA = 25C
IS = 10mA

0
0

10

12

14

VS OR VD (V)

Figure 6. On Resistance as a Function of VD (VS), Single Supply

TA = +125C

3.0

TA = +85C

2.5

TA = +25C

2.0
TA = 40C
1.5
1.0

VDD = 15V,
VSS = 0V

VDD = 12V
VSS = 0V
IS = 10mA

0.5
0

06816-006

3.5

6
VS OR VD (V)

10

12

06815-109

ON RESISTANCE ()

VDD = +5V
VSS = 5V
IS = 10mA
06815-108

0
7

0.5

TA = 25C
IS = 10mA
06816-005

0.5

Figure 9. On Resistance as a Function of VD (VS) for Different Temperatures,

Single Supply

Rev. A | Page 9 of 16

ADG1404
6

80

TA = 25C
IDD PER LOGIC INPUT

70

2
60
IS (OFF) +
ID (OFF) +
IS (OFF) +
ID (OFF) +
ID, IS (ON) + +
ID, IS (ON)

2
4
6

50
IDD (A)

LEAKAGE (nA)

40

VDD = +15V
VSS = 15V

VDD = +12V
VSS = 0V

30

8
20
10
VDD = +15V
VSS = 15V
VBIAS = +10V/10V
40

60

80

100

120

TEMPERATURE (C)

0
0

LEAKAGE (nA)

2
1
0
1
2

20

40

60

80

100

120

TA = 25C

VDD = +15V, VSS = 15V

200
VDD = +5V, VSS = 5V

0
VDD = +12V, VSS = 0V

200

TEMPERATURE (C)

600
15

06816-112

350

300
VDD = +12V, VSS = 0V

250
200
150

VDD = +15V, VSS = 15V

100

VDD = 12V
VSS = 0V
VBIAS = 1V/10V
20

50

40

60

80

TEMPERATURE (C)

100

120

06816-113

15

VDD = +5V, VSS = 5V

400

10

450

500

TIME (ns)

LEAKAGE (nA)

10

Figure 14. Charge Injection vs. Source Voltage

IS (OFF) +
ID (OFF) +
IS (OFF) +
ID (OFF) +
ID, IS (ON) + +
ID, IS (ON)

12

10

VS (V)

Figure 11. Leakage Currents as a Function of Temperature, 5 V Dual Supply

14

14

400

VDD = +5V
VSS = 5V
VBIAS = +4.5V/4.5V

12

400
CHARGE INJECTION (pC)

10

Figure 13. IDD vs. Logic Level

600

IS (OFF) +
ID (OFF) +
IS (OFF) +
ID (OFF) +
ID, IS (ON) + +
ID, IS (ON)

LOGIC, Ax (V)

Figure 10. Leakage Currents as a Function of Temperature,15 V Dual Supply

06815-008

20

06816-012

VDD = +5V
VSS = 5V

Figure 12. Leakage Currents as a Function of Temperature, 12 V Single Supply

Rev. A | Page 10 of 16

0
40

20

20

40

60

80

100

TEMPERATURE (C)

Figure 15. Transition Times vs. Temperature

120

06816-013

14

10

06816-111

12

0.024
0.022
0.020

0.016
0.014

0.010

VS = 10V p-p

0.006

100k

1M

10M

100M

0.002
10

100

1k

10k

100k

FREQUENCY (Hz)

06816-017

0.004

Figure 16. Off Isolation vs. Frequency

VS = 15V p-p

0.012

0.008

FREQUENCY (Hz)

10

VS = 20V p-p

VDD = +15V
VSS = 15V
TA = 25C

0.018
THD + N (%)

0
5 TA = 25C
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
1k
10k

06816-014

OFF ISOLATION (dB)

ADG1404

Figure 19. THD + N vs. Frequency at 15 V

TA = 25C

20

VDD = +5V
VSS = 5V
TA = 25C
VS = 10V p-p

0.1

40

THD + N (%)

CROSSTALK (dB)

30

50
60
70

VS = 5V p-p

0.01

VS = 2.5V p-p

80
90

10k

100k

1M

10M

100M

FREQUENCY (Hz)

0.001
10

06816-015

110
1k

10k

100k

Figure 20. THD + N vs. Frequency at 5 V

0
10

VDD = +15V
VSS = 15V
TA = 25C

20

VDD = +15V
VSS = 15V
V p-p = 0.63V
TA = 25C

ACPSRR (dB)

30

3
4

40

NO DECOUPLING
CAPACITORS

50
60

DECOUPLING
CAPACITORS
ON SUPPLIES

70

80
6

90
10k

100k

1M

10M

FREQUENCY (Hz)

100M

Figure 18. On Response vs. Frequency

100
1k

10k

100k

1M

FREQUENCY (Hz)

Figure 21. ACPSRR vs. Frequency

Rev. A | Page 11 of 16

10M

06815-017

7
1k

06816-016

INSERTION LOSS (dB)

1k
FREQUENCY (Hz)

Figure 17. Crosstalk vs. Frequency

100

06816-018

100

ADG1404
TERMINOLOGY
IDD
The positive supply current.

CIN
The digital input capacitance.

ISS
The negative supply current.

tTRANSITION
The delay time between the 50% and 90% points of the digital
input and switch on condition when switching from one
address state to another.

VD (VS)
The analog voltage on Terminal D and Terminal S.
RON
The ohmic resistance between Terminal D and Terminal S.
RFLAT(ON)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the
specified analog signal range.

tON (EN)
The delay between applying the digital control input and the
output switching on. See Figure 29, Test Circuit 4.
tOFF (EN)
The delay between applying the digital control input and the
output switching off.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.

IS (Off)
The source leakage current with the switch off.
ID (Off)
The drain leakage current with the switch off.

Off Isolation
A measure of unwanted signal coupling through an off switch.

ID, IS (On)
The channel leakage current with the switch on.

Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.

VINL
The maximum input voltage for Logic 0.

Bandwidth
The frequency at which the output is attenuated by 3 dB.

VINH
The minimum input voltage for Logic 1.

On Response
The frequency response of the on switch.

IINL (IINH)
The input current of the digital input.

Insertion Loss
The loss due to the on resistance of the switch.

CS (Off)
The off switch source capacitance, which is measured with
reference to ground.

THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.

CD (Off)
The off switch drain capacitance, which is measured with
reference to ground.
CD, CS (On)
The on switch capacitance, which is measured with reference to
ground.

ACPSRR (AC Power Supply Rejection Ratio)

The ratio of the amplitude of signal on the output to the
amplitude of the modulation. This is a measure of the parts
ability to avoid coupling noise and spurious signals that appear
on the supply voltage pin to the output of the switch. The dc voltage
on the device is modulated by a sine wave of 0.62 V p-p.

Rev. A | Page 12 of 16

ADG1404
TEST CIRCUITS
VDD

VSS
0.1F

0.1F

VDD

NETWORK
ANALYZER

VSS

50
Sx

50
VS

Sx

RL
50

GND

VOUT

06816-020

06816-027

IDS

VS

VOUT
VS

OFF ISOLATION = 20 log

Figure 25. Off Isolation

Figure 22. On Resistance

VDD

VSS
0.1F

0.1F

VDD

NETWORK
ANALYZER

VSS

50
Sx
VS

D
Sx

GND

A
VD

06816-021

VS

VOUT WITH SWITCH

VOUT WITHOUT SWITCH

INSERTION LOSS = 20 log

Figure 23. Off Leakage

VOUT

Figure 26. Bandwidth

VDD

VSS
0.1F

0.1F

NETWORK
ANALYZER
VOUT

VDD
S1

VSS

RL
50

D
S2

VS

NC = NO CONNECT

A
VD

06816-022

NC

RL
50

GND

ID (ON)
Sx

06816-028

RL
50

ID (OFF)

CHANNEL-TO-CHANNEL CROSSTALK = 20 log

VOUT
VS

Figure 27. Channel-to-Channel Crosstalk

Figure 24. On Leakage

Rev. A | Page 13 of 16

06816-029

IS (OFF)

ADG1404
VDD

VSS
0.1F

0.1F

AUDIO PRECISION
VDD

VSS

RS

Sx
IN

VS
V p-p

D
VIN

VOUT

RL
110

06816-030

GND

Figure 28. THD + Noise

VDD VSS

0.1F

VDD VSS
S1
A1
S2
A0
S3
S4

VIN

2.4V

EN

GND

ADDRESS
DRIVE (VIN)

VS1

VS4

3V
50%

VOUT

tTRANSITION

CL
35pF

RL
300

90%

90%

VOUT

50%

0V

tTRANSITION

06816-023

0.1F

Figure 29. Address to Output Switching Times

VIN

300

2.4V

VDD VSS

0.1F

VDD VSS
S1
A1
S2
A0
S3
S4
EN

GND

ADDRESS
DRIVE (VIN)

VS1

VOUT

D
RL
300

CL
35pF

0V

VOUT

Figure 30. Break-Before-Make Time Delay

Rev. A | Page 14 of 16

3V

80%

80%

tBBM

06816-024

0.1F

ADG1404
VDD VSS

0.1F

VDD VSS
S1
A1
S2
A0
S3
S4
EN

GND

VS

3V
50%

VOUT

0.9VOUT

OUTPUT

D
RL
300

300

CL
35pF

VOUT

50%

0V

0.9VOUT

0V

tON (EN)

tOFF (EN)

Figure 31. Enable-to-Output Switching Delay

VDD

VSS

VDD

VSS

Sx

VOUT

RS
VS

DECODER

VOUT
QINJ = CL VOUT

VOUT

VIN

CL
1nF

SW OFF

SW OFF
SW ON

GND

VIN

A1 A2

SW OFF

SW OFF
06816-026

VIN

ENABLE
DRIVE (VIN)

06816-025

0.1F

EN

Figure 32. Charge Injection

Rev. A | Page 15 of 16

ADG1404
OUTLINE DIMENSIONS
5.10
5.00
4.90

14

4.50
4.40
4.30

6.40
BSC
1

PIN 1
0.65 BSC
1.20
MAX

0.15
0.05
COPLANARITY
0.10

0.30
0.19

0.20
0.09

0.75
0.60
0.45

8
0

SEATING
PLANE

061908-A

1.05
1.00
0.80

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

Figure 33. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)
Dimension shown in millimeters

4.00
BSC SQ

0.60 MAX
12 13

3.75
BSC SQ

TOP VIEW
12 MAX
1.00
0.85
0.80
SEATING
0.30
PLANE
0.23
0.18

16

EXPOSED
PAD
0.65
BSC

4
8

PIN 1
INDICATOR

2.65
2.50 SQ
2.35

0.25 MIN

1.95 BCS
0.80 MAX
0.65 TYP

BOTTOM VIEW

0.05 MAX
0.02 NOM
COPLANARITY
0.20 REF
0.08

COMPLIANT TO JEDEC STANDARDS MO-220-VGGC.

031006-A

PIN 1
INDICATOR

0.50
0.40
0.30

Figure 34. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm 4 mm Body, Very Thin Quad
(CP-16-13)
Dimensions shown in millimeters

ORDERING GUIDE
Model
ADG1404YRUZ1
ADG1404YRUZ-REEL71
ADG1404YCPZ-REEL1
ADG1404YCPZ-REEL71
1

Temperature Range
40C to +125C
40C to +125C
40C to +125C
40C to +125C

Package Description
14-Lead Thin Shrink Small Outline Package (TSSOP)
14-Lead Thin Shrink Small Outline Package (TSSOP)
16-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
16-Lead Lead Frame Chip Scale Package (LFCSP_VQ)

Z = RoHS Compliant Part.

20082009 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D06841-0-3/09(A)

Rev. A | Page 16 of 16

Package Option
RU-14
RU-14
CP-16-13
CP-16-13