0.

4 CMOS, Dual DPDT Switch

in WLCSP/LFCSP/TSSOP
ADG888

Data Sheet
FEATURES

FUNCTIONAL BLOCK DIAGRAM

1.8 V to 5.5 V operation

Ultralow on resistance
0.4 typical
0.6 maximum at 5 V supply
Excellent audio performance, ultralow distortion
0.07 typical
0.14 maximum RON flatness
High current carrying capability
400 mA continuous
600 mA peak current at 5 V
Automotive temperature range: 40C to +125C
Rail-to-rail switching operation
Typical power consumption (<0.1 W)

ADG888
S1A
D1
S1B
S2A
D2
S2B
IN1
S3A
D3
S3B
S4A
D4
S4B

APPLICATIONS

SWITCHES SHOWN
FOR A LOGIC 1 INPUT

05432-001

IN2

Cellular phones
PDAs
MP3 players
Power routing
Battery-powered systems
PCMCIA cards
Modems
Audio and video signal routing
Communication systems
Data switching

Figure 1.

GENERAL DESCRIPTION
The ADG888 is a low voltage, dual DPDT (double-pole,
double-throw) CMOS device optimized for high performance
audio switching. With its low power and small physical size, it is
ideal for portable devices.

The ADG888 is available in a 16-ball WLCSP, 16-lead LFCSP,

and a 16-lead TSSOP. These packages make the ADG888 the
ideal solution for space-constrained applications.

This device offers ultralow on resistance of less than 0.8 over

the full temperature range, making it an ideal solution for
applications requiring minimal distortion through the switch.
The ADG888 also has the capability of carrying large amounts
of current, typically 400 mA at 5 V operation.

1.
2.

PRODUCT HIGHLIGHTS

3.
4.

<0.6 over full temperature range of 40C to +125C.

High current handling capability (400 mA continuous
current at 5 V).
Low THD + N (0.008% typical).
Tiny 16-ball WLCSP, 16-lead LFCSP, and 16-lead TSSOP.

When on, each switch conducts equally well in both directions

and has an input signal range that extends to the supplies. The
ADG888 exhibits break-before-make switching action.

Rev. B

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 20052016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

ADG888* Product Page Quick Links

Last Content Update: 11/01/2016

Comparable Parts

Design Resources

View a parametric search of comparable parts

ADG888 Evaluation Board

Documentation

Discussions

Data Sheet
ADG888: 0.4 CMOS, Dual DPDT Switch in WLCSP/
LFCSP/TSSOP Data Sheet
User Guides
UG-429: Evaluation Board for the ADG888 CMOS, Dual
DPDT Switch in the WLCSP Package

View all ADG888 EngineerZone Discussions

Reference Materials

Submit a technical question or find your regional support

number

Evaluation Kits

ADG888 Material Declaration

PCN-PDN Information
Quality And Reliability
Symbols and Footprints

Sample and Buy

Visit the product page to see pricing options

Technical Support

Product Selection Guide

Switches and Multiplexers Product Selection Guide

* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.

ADG888

Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1

ESD Caution...................................................................................5

Applications ....................................................................................... 1

Pin Configurations and Function Descriptions ............................6

Functional Block Diagram .............................................................. 1

Typical Performance Characteristics ..............................................8

General Description ......................................................................... 1

Test Circuits ..................................................................................... 10

Product Highlights ........................................................................... 1

Terminology .................................................................................... 12

Revision History ............................................................................... 2

Outline Dimensions ....................................................................... 13

Specifications..................................................................................... 3

Ordering Guide .......................................................................... 14

Absolute Maximum Ratings............................................................ 5

REVISION HISTORY
4/16Rev. A to Rev. B
Changed CB-16 to CB-16-1 and CP-16-4 to
CP-16-23 ......................................................................... Throughout
Changes to Figure 2 and Table 4 ..................................................... 6
Moved Figure 4 ................................................................................. 7
Added Table 5; Renumbered Sequentially .................................... 8
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 14
12/06Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changes to Table 2 ............................................................................ 4
Changes to Table 3 ............................................................................ 5
Changes to Ordering Guide .......................................................... 13
7/05Revision 0: Initial Version

Rev. B | Page 2 of 17

Data Sheet

ADG888

SPECIFICATIONS
VDD = 4.2 V to 5.5 V, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between
Channels (RON)
On Resistance Flatness (RFLAT (ON))
LEAKAGE CURRENTS
Source Off Leakage IS (Off )
Channel On Leakage ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS 2
tON

+25C

0.4
0.48
0.04
0.06
0.07
0.11

B Version 1

Y Version1

Unit

Test Conditions/Comments

0 to VDD

V
typ
max
typ

VDD = 4.2 V, VS = 0 V to VDD, IDS = 100 mA

See Figure 16
VDD = 4.2 V, VS = 2.2 V, IDS = 100 mA

0.55

0.6

0.07

0.075

0.13

0.14

0.2
0.2

nA typ
nA typ
V min
V max
A typ
A max
pF typ

VIN = VINL or VINH

0.1

RL = 50 , CL = 35 pF
VS = 3 V/0 V; see Figure 19
RL = 50 , CL = 35 pF
VS = 3 V/0 V; see Figure 19
RL = 50 , CL = 35 pF
VS1 = VS2 = 3 V; see Figure 20
VS = 0 V, RS = 0 , CL = 1 nF; see Figure 21
RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 22
Adjacent channel; RL = 50 , CL = 5 pF,
f = 100 kHz; see Figure 25
Adjacent switch; RL = 50 , CL = 5 pF, f = 100 kHz;
see Figure 23
RL = 32 , f = 20 Hz to 20 kHz, VS = 3 V p-p
RL = 50 , CL = 5 pF; see Figure 24
RL = 50 , CL = 5 pF; see Figure 24

0.005
2

Break-Before-Make Time Delay (tBBM)

Charge Injection
Off Isolation
Channel-to-Channel Crosstalk

70
67
99

ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ

67

dB typ

0.008
0.03
29
58
110

%
dB typ
MHz typ
pF typ
pF typ

0.003

A typ
A max

33

35

18

19
5

Total Harmonic Distortion (THD + N)

Insertion Loss
3 dB Bandwidth
CS (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD

1
2

VDD = 4.2 V, VS = 0 V to VDD

IDS = 100 mA
VDD = 5.5 V
VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 17
VS = VD = 1 V or 4.5 V; see Figure 18

2.0
0.8

22
30
13
17
9

tOFF

max
typ
max

VDD = 5.5 V
Digital inputs = 0 V or 5.5 V

Temperature range for the Y version is 40C to +125C for the TSSOP and LFCSP; temperature range for the B version is 40C to +85C for the WLCSP.
Guaranteed by design, not production tested.

Rev. B | Page 3 of 17

ADG888

Data Sheet

VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted.

Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between
Channels (RON)
On Resistance Flatness (RFLAT (ON))

+25C

0.5
0.7
0.045
0.072
0.16

B Version 1

Y Version1

Unit

Test Conditions/Comments

0 to VDD

V
typ
max
typ

VDD = 2.7 V, VS = 0 V to VDD

IS = 100 mA; see Figure 16
VDD = 2.7 V, VS = 1 V

0.75

0.8

0.077

0.083
0.262

LEAKAGE CURRENTS
Source Off Leakage IS (Off )
Channel On Leakage ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS 2
tON

0.2
0.2
1.3
0.8

V min
V max

0.1

A typ
A max
pF typ

Break-Before-Make Time Delay (tBBM)

Charge Injection
Off Isolation
Channel-to-Channel Crosstalk

50
67
99

tOFF

nA typ
nA typ

0.005

28
43
13
20
14

47

50

21

22
5

67
Total Harmonic Distortion (THD + N)
Insertion Loss
3 dB Bandwidth
CS (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD

0.01
0.04
29
60
115
0.003
1

1
2

max
typ
max

IS = 100 mA
VDD = 2.7 V, VS = 0 V to VDD
IS = 100 mA
VDD = 3.6 V
VS = 1 V/2.6 V, VD = 2.6 V/1 V; see Figure 17
VS = VD = 1 V or 2.6 V; see Figure 18

VIN = VINL or VINH

ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ

RL = 50 , CL = 35 pF; see Figure 19

VS = 1.5 V/0 V
RL = 50 , CL = 35 pF; see Figure 19
VS = 1.5 V/0 V
RL = 50 , CL = 35 pF
VS1 = VS2 = 1.5 V; see Figure 20
VS = 0 V, RS = 0 , CL = 1 nF; see Figure 21
RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 22
Adjacent channel; RL = 50 V, CL = 5 pF, f = 100 kHz;
see Figure 25
dB typ
Adjacent switch; RL = 50 , CL = 5 pF, f = 100 kHz;
see Figure 23
%
RL = 32 , f = 20 Hz to 20 kHz, VS = 1 V p-p
dB typ
RL = 50 , CL = 5 pF; see Figure 24
MHz typ RL = 50 , CL = 5 pF; see Figure 24
pF typ
pF typ
VDD = 3.6 V
A typ Digital inputs = 0 V or 3.6 V
A max

Temperature range for the Y version is 40C to +125C for the TSSOP and LFCSP; temperature range for the B version is 40C to +85C for the WLCSP.
Guaranteed by design, not production tested.

Rev. B | Page 4 of 17

Data Sheet

ADG888

ABSOLUTE MAXIMUM RATINGS

TA = 25C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
Analog Inputs, Digital Inputs1
Peak Current, S or D
5 V operation
Continuous Current, S or D
5 V operation
Operating Temperature Range
Automotive (Y Version)
TSSOP and LFCSP
Industrial (B version)
WLCSP
Storage Temperature Range
Junction Temperature
Thermal Impedance
16-Lead TSSOP
JA (4-Layer Board)
JC
16-Lead WLCSP
JA (4-Layer Board)
16-Lead LFCSP
JA (4-Layer Board)
Reflow Soldering (RoHS Compliant)
Peak Temperature
Time at Peak Temperature
1

Rating
0.3 V to +6 V
0.3 V to VDD + 0.3 V or 30 mA,
whichever occurs first

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

600 mA (pulsed at 1 ms,

10% duty cycle max)

Only one absolute maximum rating can be applied at any one

time.

400 mA

ESD CAUTION

40C to +125C
40C to +85C
65C to +150C
150C

112C/W
27.6C/W
130C/W
30.4C/W
260(+0/5)C
10 sec to 40 sec

Overvoltages at IN, S, or D are clamped by internal diodes. Limit current to

the maximum ratings given.

Rev. B | Page 5 of 17

ADG888

Data Sheet

13 S4A

14 GND

16 S1A

15 VDD

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

D1 1
S1B 2

ADG888

S2B 3

TOP VIEW
(Not to Scale)

11 S4B
10 S3B
9 D3

NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO GROUND.

05432-003

S3A 8

IN2 7

IN1 6

S2A 5

D2 4

VDD

16

GND

S1A

15

S4A

D1

ADG888

14

D4

S1B

TOP VIEW
(Not to Scale)

13

S4B

S2B

12

S3B

D2

11

D3

S2A

10

S3A

IN1

IN2

Figure 3. 16-Lead TSSOP

Pin Configuration

Figure 2. 16-Lead LFCSP

Pin Configuration

Table 4. LFCSP and TSSOP Pin Function Descriptions

LFCSP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0

Pin No.
TSSOP
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
Not applicable

Mnemonic
D1
S1B
S2B
D2
S2A
IN1
IN2
S3A
D3
S3B
S4B
D4
S4A
GND
VDD
S1A
EP

Description
Drain Terminal 1. Can be an input or output.
Source Terminal 1B. Can be an input or output.
Source Terminal 2B. Can be an input or output.
Drain Terminal 2. Can be an input or output.
Source Terminal 2A. Can be an input or output.
Logic Control Input.
Logic Control Input.
Source Terminal 3A. Can be an input or output.
Drain Terminal 3. Can be an input or output.
Source Terminal 3B. Can be an input or output.
Source Terminal 4B. Can be an input or output.
Drain Terminal 4. Can be an input or output.
Source Terminal 4A. Can be an input or output.
Ground (0 V) Reference.
Most Positive Power Supply Potential.
Source Terminal 1A. Can be an input or output.
Exposed Pad. The exposed pad must be connected to ground.

Rev. B | Page 6 of 17

05432-004

12 D4

Data Sheet

ADG888
BALL A1
INDICATOR
B

D4

S4A

S1A

D1

S4B

GND

VDD

S1B

S3B

IN2

IN1

S2B

D3

S3A

S2A

D2

05432-002

ADG888
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
(SOLDER BALLS ON OPPOSITE SIDE)

Figure 4. 16-Ball WLCSP Pin Configuration

Table 5. WLCSP Pin Function Descriptions

WLCSP Pin No.
1A
1B
1C
1D
2A
2B
2C
2D
3A
3B
3C
3D
4A
4B
4C
4D

Mnemonic
D4
S4A
S1A
D1
S4B
GND
VDD
S1B
S3B
IN2
IN1
S2B
D3
S3A
S2A
D2

Description
Drain Terminal 4. Can be an input or output.
Source Terminal 4A. Can be an input or output.
Source Terminal 1A. Can be an input or output.
Drain Terminal 1. Can be an input or output.
Source Terminal 4B. Can be an input or output.
Ground (0 V) Reference.
Most Positive Power Supply Potential.
Source Terminal 1B. Can be an input or output.
Source Terminal 3B. Can be an input or output.
Logic Control Input.
Logic Control Input.
Source Terminal 2B. Can be an input or output.
Drain Terminal 3. Can be an input or output.
Source Terminal 3A. Can be an input or output.
Source Terminal 2A. Can be an input or output.
Drain Terminal 2. Can be an input or output.

Table 6. Truth Table

Logic (IN1/IN2)
0
1

Switch 1A/2A/3A/4A
Off
On

Switch 1B/2B/3B/4B
On
Off

Rev. B | Page 7 of 17

ADG888

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

0.40

0.7

TA = 25C
IDS = 100mA

VDD = 4.2V
0.35

TA = +125C

0.6

VDD = 4.5V
0.30

TA = +85C

VDD = 3V
IDS = 100mA

0.5

VDD = 5V

VDD = 5.5V

0.20

RON ()

RON ()

0.25
0.4
TA = +25C

0.3

TA = 40C

0.15
0.2

0.10

0
2

05432-008

0.1

05432-005

0.05

0
0

0.5

1.0

VS, VD (V)

Figure 5. On Resistance vs. VD (VS), VDD = 4.2 V to 5.5 V

0.6
VDD = 2.7V

VDD = 3V

0.5

1.5

2.0

3.0

2.5

VS, VD (V)

Figure 8. On Resistance vs. VD (VS) for Different

Temperatures, VDD = 3 V
400

TA = 25C
IDS = 100mA

TA = 25C

350
300
VDD = 5V

0.4

QINJ (pC)

RON ()

250

VDD = 3.3V

0.3

VDD = 3.6V

200
150

0.2
100
VDD = 3V

0.1

0
0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.5

1.0

1.5

VS, VD (V)

Figure 6. On Resistance vs. VD (VS), VDD = 2.7 V to 3.6 V

0.45

TA = +85C

0.25

TA = +25C

0.20

TA = 40C

VDD = 3V; SxB CHANNELS

VDD = 5V; SxA CHANNELS

35

VDD = 5V; SxB CHANNELS

25

0.10

10

0.05

0
1.0

1.5

2.0

2.5

3.0

4.5

5.0

3.5

4.0

4.5

tON

20
15

0.5

4.0

VDD = 3V; SxA CHANNELS

40

0.15

3.5

30

TIME (ns)

0.30

05432-007

RON ()

45

TA = +125C

0.35

2.5
3.0
VD (V)

Figure 9. Charge Injection vs. Source Voltage

VDD = 5V
IDS = 100mA

0.40

2.0

tOFF

0
40

5.0

VS, VD (V)

VDD = 3V, 5V; SxB CHANNELS

VDD = 3V, 5V; SxA CHANNELS

20

20
40
60
TEMPERATURE (C)

80

Figure 10. tON/tOFF Times vs. Temperature

Figure 7. On Resistance vs. VD (VS) for Different

Temperatures, VDD = 5 V

Rev. B | Page 8 of 17

100

120

05432-010

05432-009

05432-006

50

Data Sheet

ADG888
0.025

TA = 25C

VDD = 3V, VS = 2V p-p

1
0.020

4
5
6

0.015

VDD = 5V, VS = 3V p-p

100k

1M
FREQUENCY (Hz)

10M

VDD = 5V, VS = 1V p-p

0
0

100M

Figure 11. Bandwidth

2k

4k

6k

8k
10k 12k 14k
FREQUENCY (Hz)

16k

18k

20k

Figure 14. Total Harmonic Distortion + Noise (THD + N)

20

TA = 25C
VDD = 3V, 4.2V, 5V

20

ATTENUATION (dB)

40

60

80

100

TA = 25C
VDD = 3V, 4.2V, 5V
NO DECOUPLING ON SUPPLIES

20

40

60

1k

10k

100k

1M

10M

100
100

100M

FREQUENCY (Hz)

20
ADJACENT CHANNELS (S1A-S2A)
ADJACENT SWITCHES (S1A-S1B)

60
80
100
S1A-S4A
05432-013

120

1k

10k
100k
1M
FREQUENCY (Hz)

10k

100k

Figure 15. AC PSRR

TA = 25C
VDD = 3V, 4.2V, 5V

140
100

1k

FREQUENCY (Hz)

Figure 12. Off Isolation vs. Frequency

40

05432-023

05432-012

80

120
100

05432-014

TA = 25C
VDD = 3V, 4.2V, 5V

10
10k

VDD = 3V, VS = 0.5V p-p

0.005
05432-011

ATTENUATION (dB)

VDD = 3V, VS = 1V p-p

0.010

7
8

ATTENUATION (dB)

VDD = 5V, VS = 4V p-p

THD + N (%)

ON RESPONSE (dB)

10M

100M

Figure 13. Crosstalk vs. Frequency

Rev. B | Page 9 of 17

1M

10M

100M

ADG888

Data Sheet

TEST CIRCUITS
IDS
V1
D

VS
RON = V1/IDS

NC

Figure 18. On Leakage

ID (OFF)

VS

VD

05432-016

A
VD

Figure 16. On Resistance

IS (OFF)

Figure 17. Off Leakage

VDD
0.1F

VDD
S1B
S1A

VS

VOUT

D1
RL
50

IN

50%

VIN

CL
35pF

50%

90%

90%

GND

tON

tOFF

05432-018

VOUT

Figure 19. Switching Times, tON, tOFF

VDD
0.1F
50%
VDD
S1B
S1A

VS

VIN
VOUT

D1

80%

VOUT
RL

IN

50%

0V

CL
35pF

tBBM

tBBM
05432-019

50

80%

GND

Figure 20. Break-Before-Make Time Delay, tBBM

VDD
SW ON
NC

D1
S1A

VOUT
1nF

IN

VOUT

VOUT
QINJ = CL VOUT

GND

Figure 21. Charge Injection

Rev. B | Page 10 of 17

05432-020

VS

SW OFF

VIN

S1B

05432-017

ID (ON)
05432-015

Data Sheet

ADG888
VDD

VDD

0.1F

0.1F
NETWORK
ANALYZER

VDD

S1A

50

50

S1B

50

S1A

VS

VS

D
VOUT
05432-021

RL
50
GND

OFF ISOLATION = 20 log

RL
50

GND

VOUT

INSERTION LOSS = 20 log

VS

Figure 22. Off Isolation

VOUT
05432-022

S1B

NC

NETWORK
ANALYZER

VDD

VOUT WITH SWITCH

VOUT WITHOUT SWITCH

Figure 24. Bandwidth

VDD

0.1F

VDD

RL
50

VOUT

S1B

50

RL
50

NC

VS

CHANNEL-TO-CHANNEL CROSSTALK = 20 log

VOUT
VS

05432-024

VS

NC

D1
50

S1B

CHANNEL-TO-CHANNEL CROSSTALK = 20 log

VOUT
VS

Figure 25. Channel-to-Channel Crosstalk (S1A to S2A)

Figure 23. Channel-to-Channel Crosstalk (S1A to S1B)

Rev. B | Page 11 of 17

NC

S2B

S1A

50

GND

D2

S2A

50

05432-025

VOUT

NETWORK
ANALYZER

S1A

ADG888

Data Sheet

TERMINOLOGY
tOFF
Delay time between the 50% and the 90% points of the digital
input and switch off condition.

IDD
Positive supply current.
VD (VS)
Analog voltage on Terminal D and Terminal S.
RON
Ohmic resistance between Terminal D and Terminal S.

tBBM
On or off time measured between the 80% points of both
switches when switching from one to another.

RFLAT (ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured.

Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during on-off switching.

RON
On resistance match between any two channels.

Off Isolation
A measure of unwanted signal coupling through an off switch.

IS (OFF)
Source leakage current with the switch off.

Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance. This is
specified for two conditions:

ID, IS (ON)
Channel leakage current with the switch on.

VINL
Maximum input voltage for Logic 0.

VINH
Minimum input voltage for Logic 1.

Adjacent channel, that is, S1A to S2A, S1B to S2B, S3A to

S4A, or S3B to S4B.
Adjacent switch, that is, S1A to S1B, S2A to S2B, S3A to
S3B, or S4A to S4B.

3 dB Bandwidth
The frequency at which the output is attenuated by 3 dB.

IINL (IINH)
Input current of the digital input.

On Response
The frequency response of the on switch.

CS (OFF)
Off switch source capacitance. Measured with reference to
ground.

Insertion Loss
The loss due to the on resistance of the switch.

CD, CS (ON)
On switch capacitance. Measured with reference to ground.

THD + N
The ratio of the harmonic amplitudes plus signal noise to the
fundamental.

CIN
Digital input capacitance.
tON
Delay time between the 50% and the 90% points of the digital
input and switch on condition.

Rev. B | Page 12 of 17

Data Sheet

ADG888

OUTLINE DIMENSIONS
0.65
0.59
0.53
SEATING
PLANE

1
A

0.36
0.32
0.28

BALL A1
IDENTIFIER
2.06
2.00 SQ
1.94

0.50
BALL
PITCH

TOP VIEW
(BALL SIDE DOWN)

0.11
0.09
0.07

BOTTOM VIEW
02-03-2012-B

0.28
0.24
0.20

(BALL SIDE UP)

Figure 26. 16-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-16-1)
Dimensions shown in millimeters
5.10
5.00
4.90

16

4.50
4.40
4.30

6.40
BSC
1

PIN 1
1.20
MAX

0.15
0.05

0.20
0.09
0.30
0.19

0.65
BSC

COPLANARITY
0.10

0.75
0.60
0.45

8
0

SEATING
PLANE

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 27. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)
Dimensions shown in millimeters
0.35
0.30
0.25
0.65
BSC

PIN 1
INDICATOR

16

13

12
EXPOSED
PAD

2.25
2.10 SQ
1.95

TOP VIEW
0.80
0.75
0.70
SEATING
PLANE

0.70
0.60
0.50

4
8

0.25 MIN

BOTTOM VIEW

0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.

Figure 28. 16-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm 4 mm Body and 0.75 mm Package Height
(CP-16-23)
Dimensions shown in millimeters

Rev. B | Page 13 of 17

111908-A

PIN 1
INDICATOR

4.10
4.00 SQ
3.90

ADG888

Data Sheet

ORDERING GUIDE
Model 1
ADG888YRUZ
ADG888YRUZ-REEL
ADG888YRUZ-REEL7
ADG888YCPZ-REEL7
ADG888BCBZ-REEL7
1
2

Temperature Range
40C to +125C
40C to +125C
40C to +125C
40C to +125C
40C to +85C

Package Description
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Ball Wafer Level Chip Scale Package [WLCSP]

Z = RoHS Compliant Part.

Branding on these packages is limited to three characters due to space constraints.

Rev. B | Page 14 of 17

Package Option
RU-16
RU-16
RU-16
CP-16-23
CB-16-1

Branding 2

S0D
S02

Data Sheet

ADG888

NOTES

Rev. B | Page 15 of 17

ADG888

Data Sheet

NOTES

Rev. B | Page 16 of 17

Data Sheet

ADG888

NOTES

20052016 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D05432-0-4/16(B)

Rev. B | Page 17 of 17