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XC800 .......................................................................................................................................
Warning ..............................................................................................................................
Troubleshooting ................................................................................................................
SYStem.Up Errors
FAQ .....................................................................................................................................
Configuration .....................................................................................................................
10
11
SYStem
11
Select CPU
11
11
12
SYStem.CPU
SYStem.MemAccess
SYStem.CpuAccess
SYStem.Mode
13
SYStem.LOCK
13
14
SYStem.Option IMASKASM
SYStem.Option IMASKHLL
14
14
15
16
17
SYStem.Option TRAPEN
SYStem.JtagClock
TrOnchip.view
TrOnchip.RESet
TrOnchip.CONVert
17
17
18
18
19
TrOnchip.VarCONVert
XC800 Debugger
Memory Classes
21
Support ...............................................................................................................................
22
Available Tools
22
Compilers
23
24
24
Products .............................................................................................................................
25
Product Information
25
Order Information
25
XC800 Debugger
XC800 Debugger
Version 24-May-2016
General Note
This documentation describes the processor specific settings and features for TRACE32-ICD for the
Infineon XC800 CPU family.
Debugger Basics - Training (training_debugger.pdf): Get familiar with the basic features of a
TRACE32 debugger.
Architecture-specific information:
Processor Architecture Manuals: These manuals describe commands that are specific for the
processor architecture supported by your debug cable. To access the manual for your processor
architecture, proceed as follows:
-
RTOS Debugger (rtos_<x>.pdf): TRACE32 PowerView can be extended for operating systemaware debugging. The appropriate RTOS manual informs you how to enable the OS-aware
debugging.
XC800 Debugger
General Note
Warning
NOTE:
Disconnect the debug cable from the target while the target power is
off.
2.
Connect the host system, the TRACE32 hardware and the debug
cable.
3.
4.
5.
6.
7.
Power down:
1.
2.
3.
4.
XC800 Debugger
Warning
Quick Start
Starting up the debugger is done as follows:
Select the device prompt for the ICD Debugger and reset the system.
B::
The device prompt B:: is normally already selected in the command line. If this is not the case enter B:: to
set the correct device prompt. The RESet command is only necessary if you do not start directly after
booting the TRACE32 development tool.
5.
The default values of all other option are set in such a way that it should be possible to work without
modification. Please consider that this is probably not the best configuration for your target.
6.
subcommands of MAP to define inaccessible memory areas. Bus errors can be removed by
executing SYStem.Up. Make sure that there isnt any T32 window open which accesses to a
inaccessible memory that is not masked out, otherwise the bus error can occur again.
7.
This command resets the CPU and enters debug mode. After this command is executed it is possible
to access memory and registers.
8.
The format of the Data.LOAD command depends on the file format generated by the compiler. Refer
to Supported Compilers to find the command, that is necessary for your compiler. It is
recommended to use the option /verify that verifies all written data. This test discovers a problem with
the electrical connection, wrong chip configurations or linker command file settings.
A detailed description of the Data.LOAD command and all available options is given in the General
Commands Reference.
XC800 Debugger
Quick Start
The start up can be automated using the programming language PRACTICE. A typical start sequence for
the XC888-8FF is shown below:
b::
WinCLEAR
SYStem.CPU XC888
; Select CPU
SYStem.UP
Go main
Data.List
Register /SpotLight
Var.Local
XC800 Debugger
Quick Start
Troubleshooting
SYStem.Up Errors
The SYStem.Up command is the first command of a debug session where communication with the target is
required. If you receive error messages while executing this command this may have the following reasons.
The pull-up resistor between the JTAG[VCCS] pin and the target VCC is too large.
XC800 Debugger
Troubleshooting
FAQ
Debugging via
VPN
XC800 Debugger
FAQ
Setting a
Software
Breakpoint fails
OMF2 symbol
loading
When I load the symbols with Data.LOAD.OMF I get the error "unexpected
end of file".
If you use the extended linker (LX51) and extended assembler (AX51), please
use the commando Data.Load.OMF2 to load the symbols.
XC800 Debugger
FAQ
Configuration
PC
Target
Debug Cable
PODBUS IN
USB
Cable
JTAG
Connector
LAUTERBACH
POWER
TRIG
DEBUG CABLE
DEBUG CABLE
USB
POWER
7-9 V
LAUTERBACH
SELECT
EMULATE
PODBUS OUT
HUB
PC or
Workstation
Target
Debug Cable
TRIG
LAUTERBACH
RECEIVE
COLLISION
PODBUS OUT
DEBUG CABLE
ETHERNET
CON ERR
POWER
7-9 V
LAUTERBACH
TRIGGER
TRANSMIT
DEBUG CABLE
EMULATE
RECORDING
SELECT
USB
Ethernet
Cable
JTAG
Connector
PODBUS IN
POWER
AC/DC Adapter
The processor type must be selected by the SYStem.CPU command before issuing any other target related
commands.
1989-2016 Lauterbach GmbH
XC800 Debugger
10
Configuration
SYStem
Format:
SYStem
Opens a window with settings of CPU specific system commands. Settings can also be changed here.
SYStem.CPU
Select CPU
Format:
SYStem.CPU <cpu>
<cpu>:
SYStem.MemAccess
Format:
SYStem.MemAccess <mode>
<mode>:
CPU
Denied
Default: Denied.
CPU
A run-time memory access is made without CPU intervention while the program
is running. This is only possible on the instruction set simulator.
XC800 Debugger
11
SYStem.CpuAccess
Format:
Default: Denied.
Enable
Denied
Nonstop
Lock all features of the debugger that affect the run-time behavior.
If SYStem.CpuAccess Enable is set, it is possible to read from memory, to write to memory and to set
software breakpoints while the CPU is executing the program. To make this possible, the program execution
is shortly stopped by the debugger. Each stop takes 0.1-100 ms depending on the speed of the JTAG port
and the operations that should be performed. A red S in the state line of the TRACE32 screen warns you,
that the program is no longer running in realtime.
If specific windows, that display memory or variables should be updated while the program is running select
the memory class E: or the format option %E.
Data.dump E:0x100
Var.View %E first
XC800 Debugger
12
SYStem.Mode
Format:
SYStem.Mode <mode>
<mode>:
Down
NoDebug
Go
Attach
Up
Down
NoDebug
Go
Resets the target and enables the debugger and start the program execution.
Program execution can be stopped by the break command or if any break
condition occurs.
Attach
User program remains running (no reset) and the debug mode is activated.
After this command the user program can be stopped with the break command
or if any break condition occurs.
Up
Resets the target, sets the CPU to debug mode and stops the CPU.
After the execution of this command the CPU is stopped and all register are set
to defaults.
SYStem.LOCK
Format:
Default: OFF.
If the system is locked no access to the JTAG port will be performed by the debugger. While locked the JTAG
connector of the debugger is tristated. The intention of the lock command is for example to give JTAG
access to another tool.
XC800 Debugger
13
System Options
SYStem.Option IMASKASM
Format:
Default: OFF.
If enabled, the interrupt mask bits of the CPU will be set during assembler single-step operations. The
interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are
restored to the value before the step.
SYStem.Option IMASKHLL
Format:
Default: OFF.
If enabled, the interrupt mask bits of the CPU will be set during HLL single-step operations. The interrupt
routine is not executed during single-step operations. After single step the interrupt mask bits are restored to
XC800 Debugger
14
System Options
SYStem.Option TRAPEN
Format:
When the SYStem.Option TRAPEN check box is checked, the debugger sets the TRAP_EN flag in the
Extended Operation (EO) register before executing the next GO command.
The XC800 extends the 8051 instruction set with the special command
MOVC @(DPTR++),A
to write data (e.g. from a I2C LPC memory IC) into program RAM. As the 8051 instruction set is
only 8 bit wide, and there were no unused opcodes available, the TRAP opcode 0A5h is re-used
for this instruction.
The functionality of the 0A5h opcode is determined by the bit TRAP_EN in the Extended
Operations (EO) register (usually EO.4).
-
This conflicts with the operation of software breakpoints. Software breakpoints are set by
replacing an instruction with a TRAP instruction. When the processor stops in debug mode, the
original instruction is restored. The next STEP or GO command then executes the instruction.
XC800 Debugger
15
System Options
SYStem.JtagClock
Format:
<frequency>
6 kHz 80 MHz
1250000. | 2500000. | 5000000. | 10000000.
XC800 Debugger
16
System Options
TrOnchip Commands
TrOnchip.view
Format:
TrOnchip.view
TrOnchip.RESet
Format:
TrOnchip.RESet
XC800 Debugger
17
TrOnchip Commands
TrOnchip.CONVert
Format:
The on-chip breakpoints can only cover specific ranges. If a range cannot be programmed into the
breakpoint it will automatically be converted into a single address breakpoint when this option is active. This
is the default. Otherwise an error message is generated.
TrOnchip.CONVert ON
Break.Set 0x1000--0x17ff /Write
Break.Set 0x1001--0x17ff /Write
TrOnchip.CONVert OFF
Break.Set 0x1000--0x17ff /Write
Break.Set 0x1001--0x17ff /Write
TrOnchip.VarCONVert
Format:
The on-chip breakpoints can only cover specific ranges. If you want to set a marker or breakpoint to a
complex variable, the on-chip break resources of the CPU may be not powerful enough to cover the whole
structure. If the option TrOnchip.VarCONVert is ON the breakpoint will automatically be converted into a
single address breakpoint. This is the default setting. Otherwise an error message is generated.
XC800 Debugger
18
TrOnchip Commands
OCDS1 Connector
Signal
TMS
TDO
N/C
TDI
TRSTTCLK
BRKINRESERVED
Pin
1
3
5
7
9
11
13
15
Pin
2
4
6
8
10
12
14
16
Signal
VCCS
GND
GND
RESETBRKOUTGND
N/C
N/C
A standard 2 x 8 pin header (pin to pin spacing: 0.1 inch = 2.54mm) is required on the target.
Do connect all GND pins and all N/C pins for shielding purpose, though they are connected on
the debugger.
VCCS is the processor power supply voltage. It is used to detect if target power is on and its voltage level
determines the output buffer level of the debugger. That means the output voltage of the debugger signals
(TMS, TDI, TCLK, TRST-, BRKIN-) depends directly on VCCS. VCCS can be 2.25 5.5 V. The output
buffer takes about 2 mA.
RESET- is controlled by an open drain driver. An external watchdog must be switched off if the InCircuit Debugger is used.
BRKIN and BRKOUT- must be configured in MCBS (Multi Core Break Switch) for before they can
be used.
VIHmin = 2.0 V, VILmax = 0.8 V for the input pins TDO, BRKOUT-.
For an example design please see the Infineon Evaluation Board schematics.
XC800 Debugger
19
OCDS1 Connector
Pins
Connection
Description
Recommendations
TMS
Test Mode
Select
None.
VCCS
VCC Sense
TDO
4, 6, 12
GND
System
Ground Plan
TDI
Test Data In
RESET
Reset
TRST
Test Reset
10
BRKOUT
Break out
None.
11
TCLK
Test clock
None.
13
BRKIN
Break input
None.
5, 14,
15, 16
NC
Not
Connected
Connect to Ground.
XC800 Debugger
20
OCDS1 Connector
Memory Classes
The following memory classes are available:
Memory Class
Description
The low 128 bytes of the internal data memory can be accessed with the memory classes I and D. The
upper 128 bytes in the memory class D represent the Special Function Registers SFR (standard). The
Special Function Registers (standard, mapped and paged) can be accessed in the peripherie window.
XRAM can be read/written as program memory or external memory
XC800 Debugger
21
OCDS1 Connector
Support
TC260D
TC264D
TC264DA
TC264DE
TC264DU
TC265D
TC265DE
TC265DU
XC866
XC866L
XC878
XC878C
XC878CM
XC878L
XC878M
XC886
XC886C
XC886CLM
XC886CM
XC886LM
XC888
XC888C
XC888CLM
XC888CM
XC888LM
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
POWER
INTEGRATOR
ICD
TRACE
ICD
MONITOR
ICD
DEBUG
FIRE
ICE
CPU
Available Tools
YES
YES
YES
YES
YES
YES
YES
YES
XC800 Debugger
22
Support
Compilers
Language
Compiler
Company
Option
C
C
UVISION3
SDCC
OMF
CDB
8051
Comment
IEEE
XC800 Debugger
23
Support
Tool
Company
ALL
ALL
ALL
ADENEO
X-TOOLS / X32
CODEWRIGHT
ALL
CODE CONFIDENCE
TOOLS
CODE CONFIDENCE
TOOLS
EASYCODE
ECLIPSE
RHAPSODY IN MICROC
RHAPSODY IN C++
CHRONVIEW
LDRA TOOL SUITE
UML DEBUGGER
Adeneo Embedded
blue river software GmbH
Borland Software
Corporation
Code Confidence Ltd
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ATTOL TOOLS
VISUAL BASIC
INTERFACE
LABVIEW
CODE::BLOCKS
C++TEST
RAPITIME
DA-C
TRACEANALYZER
SIMULINK
TA INSPECTOR
UNDODB
VECTORCAST UNIT
TESTING
VECTORCAST CODE
COVERAGE
WINDOWS CE PLATF.
BUILDER
Host
Windows
Windows
Windows
Linux
EASYCODE GmbH
Eclipse Foundation, Inc
IBM Corp.
IBM Corp.
Inchron GmbH
LDRA Technology, Inc.
LieberLieber Software
GmbH
MicroMax Inc.
Microsoft Corporation
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
NATIONAL
INSTRUMENTS
Corporation
Open Source
Parasoft
Rapita Systems Ltd.
RistanCASE
Symtavision GmbH
The MathWorks Inc.
Timing Architects GmbH
Undo Software
Vector Software
Windows
Windows
Windows
Windows
Windows
Windows
Linux
Windows
Vector Software
Windows
Windows
Windows
XC800 Debugger
24
Support
Products
Product Information
OrderNo Code
Text
LA-3732
OCDS-XC800
supports XC800
includes software for Windows, Linux and MacOSX
requires Power Debug Module
debug cable with 16 pin connector
LA-3732A
OCDS-XC800-A
supports XC800
Order Information
Order No.
Code
Text
LA-3732
LA-3732A
OCDS-XC800
OCDS-XC800-A
Additional Options
LA-7756A OCDS-TRICORE-A
XC800 Debugger
25
Products