78K0R/RL78 Debugger

TRACE32 Online Help

TRACE32 Directory
TRACE32 Index
TRACE32 Documents ......................................................................................................................

ICD In-Circuit Debugger ................................................................................................................

Processor Architecture Manuals ..............................................................................................

78K ............................................................................................................................................

78K0R/RL78 Debugger .........................................................................................................

Brief Overview of Documents for New Users .................................................................

Warning ..............................................................................................................................

General Notes/Target Design Requirements/Recommendations .................................

General

Target Design Requirements

Limitations

Quick Start .........................................................................................................................

Troubleshooting ................................................................................................................

Communication between Debugger and Processor can not be established

FAQ .....................................................................................................................................

78K0R/RL78 Specific Implementations ...........................................................................

11

Breakpoints

11

Software Breakpoints

11

On-chip Breakpoints

11

Breakpoints on Data Addresses and Data Values

12

Example for Standard Breakpoints

12

Runtime Measurement

13

Memory Classes

13

General SYStem Commands ............................................................................................

SYStem.CONFIG

Configure debugger according to target topology

14

Select the used CPU

14

Run-time CPU access (intrusive)

15

Set debug clock frequency

16

Lock and tristate the debug port

16

Run-time memory access

17

SYStem.CPU
SYStem.CpuAccess
SYStem.DebugClock
SYStem.LOCK
SYStem.MemAccess
SYStem.Mode

Establish the communication with the target

18

Display SYStem.state window

18

SYStem.state
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78K0R/RL78 Debugger

14

78K0R/RL78 specific SYStem Commands ......................................................................

19

SYStem.Option IMASKHLL

Disable interrupts while HLL single stepping

19

SYStem.Option.KEYCODE

Define 10 byte on-chip security ID

19

SYStem.Option.ResetMASK

Disable internal reset

19

SYStem.Option.SerialFrezze

Stops serial transmissions during break

20

SYStem.Option.TimerFreeze

Stops all internal timers during break

20

Debug Connection ............................................................................................................

21

Support ...............................................................................................................................

22

Available Tools

22

Compilers

37

Realtime Operation Systems

37

3rd Party Tool Integrations

38

Products .............................................................................................................................

38

Product Information

39

Order Information

40

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

78K0R/RL78 Debugger
Version 24-May-2016

Brief Overview of Documents for New Users

Architecture-independent information:

Debugger Basics - Training (training_debugger.pdf): Get familiar with the basic features of a
TRACE32 debugger.

T32Start (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances

for different configurations of the debugger. T32Start is only available for Windows.

General Commands (general_ref_<x>.pdf): Alphabetic list of debug commands.

Architecture-specific information:

Processor Architecture Manuals: These manuals describe commands that are specific for the
processor architecture supported by your debug cable. To access the manual for your processor
architecture, proceed as follows:
-

Choose Help menu > Processor Architecture Manual.

RTOS Debugger (rtos_<x>.pdf): TRACE32 PowerView can be extended for operating systemaware debugging. The appropriate RTOS manual informs you how to enable the OS-aware
debugging.

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

Brief Overview of Documents for New Users

Warning

NOTE:

To prevent debugger and target from damage it is recommended to connect or

disconnect the debug cable only while the target power is OFF.
Recommendation for the software start:
1.

Disconnect the debug cable from the target while the target power is
off.

2.

Connect the host system, the TRACE32 hardware and the debug
cable.

3.

Power ON the TRACE32 hardware.

4.

Start the TRACE32 software to load the debugger firmware.

5.

Connect the debug cable to the target.

6.

Switch the target power ON.

7.

Configure your debugger e.g. via a start-up script.

Power down:
1.

Switch off the target power.

2.

Disconnect the debug cable from the target.

3.

Close the TRACE32 software.

4.

Power OFF the TRACE32 hardware.

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

Warning

General Notes/Target Design Requirements/Recommendations

General

The Lauterbach TRACE32 debugger for 78K0R/RL78 is a on-chip debugging tool (OCD). It uses
the debug function implemented in the target CPU via a serial communication link (no JTAG).

Debug functionality uses a monitor program in flash memory. Due to that some resources are
used by the debugger exclusively (see limitations). Depending on the compiler besides the
activation of debug option some setting have to be done (refer the compiler manual).

Target Design Requirements

Locate the debug connector as close as possible to the processor to minimize the capacitive
influence and cross coupling of noise onto the signals. Do not put any capacitors (or RC
combinations) on the TOOL0/TOOL1 lines.

Reduce the cable length between CPU and Lauterbach connector to a minimum. Best results will
be provided, if a adequate connector will be foreseen directly on the target board.

A Pull-up resistor of about 1,5 kOhm has to adapted between TOOL0 and VDD. This could be
done on the target board or via an adaptation in the debug cable.

Limitations

The last block of internal flash memory is blocked for writing. For a block size of 1 kB (Fx3) and
256 kB of total code flash memory (78F1845) the address range 0x3FC00--0x3FFFF has to be
declared as NOP.

Debug monitor consumes 6 bytes of stack area, right before stack pointer SP. For example for a
SP value of 0xFE00, the memory range 0xFFDFA--0xFFDFF will be written by the debug monitor
before the transition RUN to BREAK.
For accurate debugging SP must always be 6 byte higher than the start address of RAM area. To
avoid impacts from debugger to user data, designated stack area should be least 6 bytes bigger than
nominally necessary.

The first 4 bytes (0x00000--0x00003) of program memory are reserved for debugging issues
and must not be changed.

21 bytes of program memory space (0x000C3--0x000D7) is reserved for debug purposes

(refer the target CPU manual for any details).
At 0x000CE the user reset vector is placed. User program will start from 0x000D8 or at higher
address.

The Pins of TOOL0 and TOOL1 (Port 4) are not usable during debugging.

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

General Notes/Target Design Requirements/

Quick Start
Starting up the debugger is done by the following steps:
1.

Select the device prompt B: for the TRACE32 ICD-Debugger, if the device prompt is not active
after starting the TRACE32 software.,
b::

The device prompt B:: is normally already selected in the command line. If this is not the case enter
B: to set the correct device prompt. A RESet command is useful if you do not start directly after
booting the TRACE32 development tool.
2.

Select the CPU derivate to load the specific settings.

SYStem.CPU 78F1845

The default value for SYStem.CPU is 78K0R, which is not a real existing derivate. This means that
the debugger tries an automatic detection of the connected derivate.
The default values of all other option are set in such a way that it should be possible to work without
modification. Please consider that this is probably not the best configuration for your target.
3.

Enter debug mode.

SYStem.Up

4.

Declare size and type of FLASH memory is recommended doing via script.
DO ~~/demo/78k0r/flash/78k0r_*.cmm

Select the adequate PRACTICE script for the connected target. It will setup the flash memory to allow
writing and setting of software-breakpoints.
If not loaded a program during the execution of the flash script, this can be done as follows:
5.

Load the program.

Data.LOAD sieve.dbg

; sieve.dbg is the file name

The format of the Data.LOAD command depends on the file format generated by the compiler. Refer
to Supported Compilers to find the command, that is necessary for your compiler. Without any
specific format (like in this example), TRACE32 tries to detected the correct format available for
78K0R-debugger depending on the specified file.
A detailed description of the Data.LOAD command and all available options is given in theGeneral
Reference Guide.

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

Quick Start

A typical start sequence is shown below. This sequence can be written to an ASCII file (script file) and
executed with the command DO <filename>.
B::

; Select the ICD-Debugger device prompt

WinCLEAR

; Clear all windows

SYStem.CPU 78F1845

; Select the CPU derivate type

SYStem.Up

; Reset the target and enter debug mode

Data.LOAD.UBROF sieve.d26

; Load the application (here IAR; Compiler)

Register.Set PC main

; Set the PC to function main

Register.Set SP 0xfe20

; Set the stack pointer to address

; 0xfe20

PER.view

; Open a window for the special

; function registers and peripherals *)

Data.List

; Open source code window *)

Register /SpotLight

; Open register window *)

Frame.view /Locals /Caller

; Open the stack frame with

; local variables *)

Var.Watch var1 var2

; Open watch window for variables *)

Var.Local

; Open window with local variables *)

Break.Set 0xffc00 /Program

; Set software breakpoint to address

; 0xffc00 (address in RAM)

Break.Set 0x100 /Onchip

; Set on-chip BP to address 0x100

*) These commands open windows on the screen. The window position can be specified with the WinPOS
command.

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

Quick Start

Troubleshooting

Communication between Debugger and Processor can not be established

Typically the SYStem.Up command is the first command of a debug session where communication with the
target is required. If you receive error messages like debug port fail or debug port time out while executing
this command this may have the reasons below. target processor in reset is just a follow-up error message.
Open the AREA window to see all error messages.

The target has no power or the debug cable is not connected to the target. This results in the
error message target power fail.

You did not select the correct core type SYStem.CPU <type>.

The target is in an unrecoverable state. Re-power your target and try again.

The default debug clock speed is too fast, especially if the target is connect to debugger by a long
cable. Reduce the communication speed with SYStem.DebugClock command and optimize the
speed when you got it working.

The CPU has no clock.

The CPU is kept in reset.

There is a watchdog which needs to be deactivated.

Your target needs special debugger settings. Check the directory \demo\78k0r if there is an
suitable script file *.cmm for your target.

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

Troubleshooting

FAQ

Debugging via
VPN

The debugger is accessed via Internet/VPN and the performance is very

slow. What can be done to improve debug performance?
The main cause for bad debug performance via Internet or VPN are low data
throughput and high latency. The ways to improve performance by the debugger
are limited:
in practice scripts, use "SCREEN.OFF" at the beginning of the script and
"SCREEN.ON" at the end. "SCREEN.OFF" will turn off screen updates.
Please note that if your program stops (e.g. on error) without executing
"SCREEN.OFF", some windows will not be updated.
"SYStem.POLLING SLOW" will set a lower frequency for target state
checks (e.g. power, reset, jtag state). It will take longer for the debugger to
recognize that the core stopped on a breakpoint.
"SETUP.URATE 1.s" will set the default update frequency of Data.List/
Data.dump/Variable windows to 1 second (the slowest possible setting).
prevent unneeded memory accesses using "MAP.UPDATEONCE
[address-range]" for RAM and "MAP.CONST [address--range]" for ROM/
FLASH. Address ranged with "MAP.UPDATEONCE" will read the specified
address range only once after the core stopped at a breakpoint or manual
break. "MAP.CONST" will read the specified address range only once per
SYStem.Mode command (e.g. SYStem.Up).

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

FAQ

Setting a
Software
Breakpoint fails

What can be the reasons why setting a software breakpoint fails?

Setting a software breakpoint can fail when the target HW is not able to
implement the wanted breakpoint.
Possible reasons:
The wanted breakpoint needs special features that are only possible to
realize by the trigger unit inside the controller.
Example: Read, write and access (Read/Write) breakpoints ("type" in Break.Set
window). Breakpoints with checking in real-time for data-values ("Data").
Breakpoints with special features ("action") like TriggerTrace, TraceEnable,
TraceOn/TraceOFF.
TRACE32 can not change the memory.
Example: ROM and Flash when no preparation with FLASH.Create,
FLASH.TARGET and FLASH.AUTO was made. All type of memory if the
memory device is missing the necessary control signals like WriteEnable or
settings of registers and SpecialFunctionRegisters (SFR).
Contrary settings in TRACE32.
Like: MAP.BOnchip for this memory range. Break.SELect.<breakpoint-type>
Onchip (HARD is only available for ICE and FIRE).
RTOS and MMU:
If the memory can be changed by Data.Set but the breakpoint doesn't work it
might be a problem of using an MMU on target when setting the breakpoint to a
symbolic address that is different than the writable and intended memory
location.

78k0r

What can be the reasons why setting a software breakpoint fails?

software
breakpoint in
program
memory / flash

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78K0R/RL78 Debugger

10

FAQ

78K0R/RL78 Specific Implementations

Breakpoints
Two types of breakpoints are available for 78K0R/RL78 architecture: Software breakpoints and one on-chip
breakpoint.

Software Breakpoints
To set a software breakpoint, before resuming the CPU, the debugger replaces the instruction at the
breakpoint address with a breakpoint code instruction.
There is no restriction in the number of software breakpoints. But it must be considered, that by the usage of
software breakpoint flash memory will be change, if program is run in flash memory.

On-chip Breakpoints
If on-chip breakpoints are used, the resources to set the breakpoints are provided by the CPU. To set
breakpoints on code in read-only memory, only the on-chip instruction address breakpoints are available.
With the command MAP.BOnchip <range> it is possible to declare memory address ranges for use with
on-chip breakpoints to the debugger.
Besides the restricted number of on-chip breakpoint, the biggest disadvantage of 78K0R/RL78 architecture
is that the breakpoints is effected after execution. It means that not only the corresponding opcode will be
executed, instead the whole instruction pipeline will be executed eventually.

On-chip breakpoints: Total amount of available on-chip breakpoints.

Instruction breakpoints: Number of on-chip breakpoints that can be used to set program
breakpoints into ROM/FLASH/EPROM.

Read/Write breakpoints: Number of on-chip breakpoints that can be used as Read or Write
breakpoints.

Data breakpoint: Number of on-chip data breakpoints that can be used to stop the program
when a specific data value is written to an address or when a specific data value is read from an
address.

Core type:

On-chip
Breakpoints

Instruction
Address
Breakpoints

Data Address
Breakpoints

Data Value
Breakpoints

78K0R/RL78

1 Instruction or
1 Read/Write

1 breakpoint

1 single
address above
0xF0000

1 single value
-- or -1 value mask

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78K0R/RL78 Debugger

11

78K0R/RL78 Specific Implementations

You can check your currently set breakpoints with the command Break.List.
If no more on-chip breakpoints are available you will get an error message on trying to set a new on-chip
breakpoint.

Breakpoints on Data Addresses and Data Values

Breakpoints on data addresses are bound to several conditions:
1.

The source of the data access (read and/or write) must be the CPU, as the data address
breakpoints are part of the CPU. Any other accesses from on-chip or off-chip peripherals (DMA
etc.) will not be recognized by the data address breakpoints.

2.

The data being targeted must be qualified by an address in memory in the range 0xF000-0xFFFFF. It is not possible to set a data address breakpoint to GPR, SPR etc.

3.

The CPU stops the application execution only if the address and the access width in the field
DATA of the Break.Set window match. An empty access width is equal to standard width, which is
Word.

4.

Per default the break will be done independently of the value (empty DATA field of Break.Set
window).

Example for Standard Breakpoints

Assume you have a target (78F1845) with:

Code flash memory from 0x00000--0x3ffff

RAM from 0xfbf00--0xffedf

The following standard breakpoint combinations are possible without activated auto flash mode:
1.

2.

Unlimited breakpoints in RAM and one breakpoint in ROM/FLASH

Break.Set 0xfcf00 /Program

; Software breakpoint 1

Break.Set 0xfd000 /Program

; Software breakpoint 2

Break.Set addr /Program

; Software breakpoint 3

Break.Set 0x100 /Program

; On-chip breakpoint

Unlimited breakpoints in RAM and one breakpoint on a read or write access

Break.Set 0xfcf00 /Program

; Software breakpoint 1

Break.Set 0xfd000 /Program

; Software breakpoint 2

Break.Set addr /Program

; Software breakpoint 3

Break.Set 0xfef47 /Write

; On-chip breakpoint

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78K0R/RL78 Debugger

12

78K0R/RL78 Specific Implementations

With activated auto flash mode even in code flash memory unlimited breakpoints are allowed:
1.

Unlimited breakpoints in ROM/FLASH

Break.Set 0x00200 /Program

; Software breakpoint 1

Break.Set 0x01000 /Program

; Software breakpoint 2

Break.Set addr /Program

; Software breakpoint 3

Break.Set 0x00100 /Program

; On-chip breakpoint

Runtime Measurement
The command RunTime allows run time measurement based on polling the CPU run status by software.
Therefore the result will be about few milliseconds higher than the real value.
If the signal DBGACK on the JTAG connector is available, the measurement will automatically be based on
this hardware signal which delivers very exact results.

Memory Classes
Even if the 78K0R/RL78 as Von Neumann architecture has a linear memory space. The following 78K0R/
RL78 specific memory classes are available:
Memory Class

Description

Program Memory

Data Memory

VM

Virtual Memory (memory on the debug system)

Run-time memory access

(see SYStem.CpuAccess and SYStem.MemAccess)

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

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78K0R/RL78 Specific Implementations

General SYStem Commands

SYStem.CONFIG

Configure debugger according to target topology

Format:

SYStem.CONFIG <parameter>

<parameter>:

state
DRPRE <bits>
DRPOST <bits>
IRPRE
<bits>
IRPOST <bits>
TAPState <state>
TCKLevel <level>
TriState [ON | OFF]
Slave [ON | OFF]

For the 78K0R/RL78 architecture this command is not usable.

SYStem.CPU

Select the used CPU

Format:

SYStem.CPU <cpu>

<cpu>:

78K0R | 78F1xxx | 78F8xxx

Selects the processor type. The first entry 78K0R stands for an automatic detection of the right CPU. If your
chip is not listed, try the default value or contract technical support.
Default selection: 78K0R

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78K0R/RL78 Debugger

14

General SYStem Commands

SYStem.CpuAccess

Run-time CPU access (intrusive)

Format:

SYStem.CpuAccess <mode>

<mode>:

Enable | Denied | Nonstop

This option declares if an intrusive memory access can take place while the CPU is executing code. To
perform this access, the debugger stops the CPU shortly, performs the access and then restarts the CPU.
The run-time memory access has to be activated for each window by using the memory class E: (e.g.
Data.dump E:0xffe20) or by using the format option %E (e.g. Var.View %E var1).
Enable

In order to perform a memory read or write while the CPU is executing the
program the debugger stops the program execution shortly.
Each short stop takes 1 100 ms depending on the speed of the CPU and
debug interface and on the size of the read/write accesses required.

Denied

No intrusive memory read or write is possible while the CPU is executing the
program.

Nonstop

Nonstop ensures that the program execution can not be stopped and that the
debugger does not affect the real-time behavior of the CPU.
Nonstop reduces the functionality of the debugger to:

run-time access to memory and variables (not available for 78K0R/RL78)

trace display (not available for 78K0R/RL78)

The debugger inhibits the following:

to stop the program execution

all features of the debugger that are intrusive (e.g. spot breakpoints, performance analysis via StopAndGo, conditional breakpoints etc.)

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78K0R/RL78 Debugger

15

General SYStem Commands

SYStem.DebugClock

Set debug clock frequency

Format:

SYStem.DebugClock <rate>

<rate>:

1/4 1/256

Selects the frequency for the debug interface. The value represents the quotient of the division: Debug
communication frequency divided by the frequency of TOOL1 (half of CPU frequency). As long as no
problems occur it is recommend not change the default value.
In the case of unstable debug connection between debugger and target, lower values (towards 1/256) could
help. Higher values (towards 1/4) effect in a faster debug communication, but the higher frequencies on the
TOOL0 cable could lead to unstable debug connection.
Default value: 1/16
Example: Target frequency is 4 MHz, DebugClock is 1/16, transmission rate (nominal) is:
0.5 * 4 MHz / 16 = 125 kHz = 125 kbit/s

SYStem.LOCK

Format:

Lock and tristate the debug port

SYStem.LOCK [ON | OFF]

Default: OFF.
If the system is locked, no access to the debug port will be performed by the debugger. While locked, the
debug connector of the debugger is tristated. The main intention of the lock command is to give debug
access to another tool.
The command has no effect for the simulator.

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

16

General SYStem Commands

SYStem.MemAccess

Run-time memory access

Format:

SYStem.MemAccess <mode>
SYStem.ACCESS (deprecated)

<mode>:

CPU
Denied

Default: Denied.
If SYStem.MemAccess is not Denied, it is possible to read from memory, to write to memory and to set
software breakpoints while the CPU is executing the program. This requires one of the following monitors.
CPU

A run-time memory access is made without CPU intervention while the program
is running. This is only possible on the instruction set simulator.

Denied

No memory access is possible while the CPU is executing the program.

If specific windows, that display memory or variables should be updated while the program is running select
the memory class E: or the format option %E.
Data.dump E:0x100
Var.View %E first

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

17

General SYStem Commands

SYStem.Mode

Establish the communication with the target

Format:

SYStem.Mode <mode>

<mode>:

Down | NoDebug | Go | Up

Select target reset mode.

Down

Disables the debugger. The state of the CPU remains unchanged.

NoDebug

Resets the target with debug mode disabled. In this mode no debugging is
possible. The CPU state keeps in the state of NoDebug.

Go

Resets the target with debug mode enabled and prepares the CPU for debug
mode entry. After this command the CPU is in the SYStem.Up mode and
running. Now, the processor can be stopped with the break command or any
break condition.

Up

Resets the target and sets the CPU to debug mode. After execution of this
command the CPU is stopped and prepared for debugging. All register are set
to the default value.

NOTE:

The system modes Attach and StandBy are not available for this architecture.

SYStem.state

Format:

Display SYStem.state window

SYStem.state

Displays the SYStem.state window of the 78K0R/RL78 debugger.

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

18

General SYStem Commands

78K0R/RL78 specific SYStem Commands

SYStem.Option IMASKHLL

Format:

Disable interrupts while HLL single stepping

SYStem.Option IMASKHLL [ON | OFF]

Default: OFF.
If enabled, the interrupt mask bits of the cpu will be set during HLL single-step operations. The interrupt
routine is not executed during single-step operations. After single step the interrupt mask bits are restored to
the value before the step.

SYStem.Option.KEYCODE

Format:

Define 10 byte on-chip security ID

SYStem.Option.KEYCODE <sec_id>

The default value for a plain CPU is set during SYStem.Up. If flash contains already a program with
activated security ID the correct ID has to be insert before the SYStem.Up command, otherwise it is
impossible to establish a debug connection.
The key code will automatically updated if a program will be loaded with activated security ID option.
<sec_id>

Any ID code of 10 bytes (20 hexadecimals).

SYStem.Option.ResetMASK

Format:

Disable internal reset

SYStem.Option.RESETMASK [ON | OFF]

Default: OFF.
If enabled, all internal resets are masked out and do not take any effects. This is for example useful when
internal watch dog is activated.

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78K0R/RL78 Debugger

19

78K0R/RL78 specific SYStem Commands

SYStem.Option.SerialFrezze

Format:

Stops serial transmissions during break

SYStem.Option.SerialFrezze [ON | OFF]

Default: OFF.
If activated serial transmission will be stopped if the target is stopped.

SYStem.Option.TimerFreeze

Format:

Stops all internal timers during break

SYStem.Option.TimerFreeze [ON | OFF]

Default: OFF.
If activated the counting operations all internal timers will be stopped if the target is stopped.

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

20

78K0R/RL78 specific SYStem Commands

Debug Connection
Pinout of the 16-pin Debug Cable:
Signal
VSS
TOOL0
N/C
N/C
N/C
N/C
N/C
TRESET-

Pin
1
3
5
7
9
11
13
15

Pin
2
4
6
8
10
12
14
16

Signal
RESETVDD
N/C
N/C
N/C
N/C
FLMD0
TOOL1

For details on logical functionality, physical connector, alternative connectors, electrical characteristics,
timing behavior and printing circuit design hints refer to the application note JTAG Interface Specification.

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

21

Debug Connection

Support

R5F1006A
R5F1006C
R5F1006D
R5F1006E
R5F1007A
R5F1007C
R5F1007D
R5F1007E
R5F1008A
R5F1008C
R5F1008D
R5F1008E
R5F100AA
R5F100AC
R5F100AD
R5F100AE
R5F100AF
R5F100AG
R5F100BA
R5F100BC
R5F100BD
R5F100BE
R5F100BF
R5F100BG
R5F100CA
R5F100CC
R5F100CD
R5F100CE
R5F100CF
R5F100CG
R5F100EA
R5F100EC
R5F100ED
R5F100EE

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU

Available Tools

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

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78K0R/RL78 Debugger

22

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
R5F100EF
R5F100EG
R5F100EH
R5F100FA
R5F100FC
R5F100FD
R5F100FE
R5F100FF
R5F100FG
R5F100FH
R5F100FJ
R5F100FK
R5F100FL
R5F100GA
R5F100GC
R5F100GD
R5F100GE
R5F100GF
R5F100GG
R5F100GH
R5F100GJ
R5F100GK
R5F100GL
R5F100JC
R5F100JD
R5F100JE
R5F100JF
R5F100JG
R5F100JH
R5F100JJ
R5F100JK
R5F100JL
R5F100LC
R5F100LD
R5F100LE
R5F100LF
R5F100LG
R5F100LH
R5F100LJ
R5F100LK
R5F100LL

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

23

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
R5F100MF
R5F100MG
R5F100MH
R5F100MJ
R5F100MK
R5F100ML
R5F100PF
R5F100PG
R5F100PH
R5F100PJ
R5F100PL
R5F100SH
R5F100SJ
R5F100SK
R5F100SL
R5F1016A
R5F1016C
R5F1016D
R5F1016E
R5F1017A
R5F1017C
R5F1017D
R5F1017E
R5F1018A
R5F1018C
R5F1018D
R5F1018E
R5F101AA
R5F101AC
R5F101AD
R5F101AE
R5F101AF
R5F101AG
R5F101BA
R5F101BC
R5F101BD
R5F101BE
R5F101BF
R5F101BG
R5F101CA
R5F101CC

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

24

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
R5F101CD
R5F101CE
R5F101CF
R5F101CG
R5F101EA
R5F101EC
R5F101ED
R5F101EE
R5F101EF
R5F101EG
R5F101EH
R5F101FA
R5F101FC
R5F101FD
R5F101FE
R5F101FF
R5F101FG
R5F101FH
R5F101FJ
R5F101FK
R5F101FL
R5F101GA
R5F101GC
R5F101GD
R5F101GE
R5F101GF
R5F101GG
R5F101GH
R5F101GJ
R5F101GK
R5F101GL
R5F101JC
R5F101JD
R5F101JE
R5F101JF
R5F101JG
R5F101JH
R5F101JJ
R5F101JK
R5F101JL
R5F101LC

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

25

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
R5F101LD
R5F101LE
R5F101LF
R5F101LG
R5F101LH
R5F101LJ
R5F101LK
R5F101LL
R5F101MF
R5F101MG
R5F101MH
R5F101MJ
R5F101MK
R5F101ML
R5F101PF
R5F101PG
R5F101PH
R5F101PJ
R5F101PK
R5F101PL
R5F101SH
R5F101SJ
R5F101SK
R5F101SL
R5F10266
R5F10267
R5F10268
R5F10269
R5F1026A
R5F10277
R5F10278
R5F10279
R5F1027A
R5F102A7
R5F102A8
R5F102A9
R5F102AA
R5F10366
R5F10367
R5F10368
R5F10369

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

26

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
R5F1036A
R5F10377
R5F10378
R5F10379
R5F1037A
R5F103A7
R5F103A8
R5F103A9
R5F103AA
R5F104AA
R5F104AC
R5F104AD
R5F104AE
R5F104AF
R5F104AG
R5F104BA
R5F104BC
R5F104BD
R5F104BE
R5F104BF
R5F104BG
R5F104CA
R5F104CC
R5F104CD
R5F104CE
R5F104CF
R5F104CG
R5F104EA
R5F104EC
R5F104ED
R5F104EE
R5F104EF
R5F104EG
R5F104EH
R5F104FA
R5F104FC
R5F104FD
R5F104FE
R5F104FF
R5F104FG
R5F104FH

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

27

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
R5F104FJ
R5F104GA
R5F104GC
R5F104GD
R5F104GE
R5F104GF
R5F104GG
R5F104GH
R5F104GJ
R5F104JC
R5F104JD
R5F104JE
R5F104JF
R5F104JG
R5F104JH
R5F104JJ
R5F104LC
R5F104LD
R5F104LE
R5F104LF
R5F104LG
R5F104LH
R5F104LJ
R5F104MF
R5F104MG
R5F104MH
R5F104MJ
R5F104PF
R5F104PG
R5F104PH
R5F104PJ
R5F1076C
R5F107AC
R5F107AE
R5F107BC
R5F107DE
R5F10968
R5F1096A
R5F1096B
R5F1096C
R5F1096D

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

28

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
R5F1096E
R5F109AA
R5F109AB
R5F109AC
R5F109AD
R5F109AE
R5F109BA
R5F109BB
R5F109BC
R5F109BD
R5F109BE
R5F109GA
R5F109GB
R5F109GC
R5F109GD
R5F109GE
R5F109LA
R5F109LB
R5F109LC
R5F109LD
R5F109LE
R5F10A6A
R5F10A6C
R5F10A6D
R5F10A6E
R5F10AAA
R5F10AAC
R5F10AAD
R5F10AAE
R5F10ABA
R5F10ABC
R5F10ABD
R5F10ABE
R5F10AGA
R5F10AGC
R5F10AGD
R5F10AGE
R5F10AGF
R5F10AGG
R5F10ALC
R5F10ALD

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

29

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
R5F10ALE
R5F10ALF
R5F10ALG
R5F10AME
R5F10AMF
R5F10AMG
R5F10BAC
R5F10BAD
R5F10BAE
R5F10BAF
R5F10BAG
R5F10BBC
R5F10BBD
R5F10BBE
R5F10BBF
R5F10BBG
R5F10BGC
R5F10BGD
R5F10BGE
R5F10BGF
R5F10BGG
R5F10BLC
R5F10BLD
R5F10BLE
R5F10BLF
R5F10BLG
R5F10BME
R5F10BMF
R5F10BMG
R5F10CGB
R5F10CGC
R5F10CGD
R5F10CLD
R5F10CMD
R5F10CME
R5F10DGC
R5F10DGD
R5F10DGE
R5F10DLD
R5F10DLE
R5F10DMD

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

30

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
R5F10DME
R5F10DMF
R5F10DMG
R5F10DMJ
R5F10DPE
R5F10DPF
R5F10DPG
R5F10DPJ
R5F10E8A
R5F10E8C
R5F10E8D
R5F10E8E
R5F10EBA
R5F10EBC
R5F10EBD
R5F10EBE
R5F10EGA
R5F10EGC
R5F10EGD
R5F10EGE
R5F10ELC
R5F10ELD
R5F10ELE
R5F10FLC
R5F10FLD
R5F10FLE
R5F10FMC
R5F10FMD
R5F10FME
R5F10JBC
R5F10JGC
R5F10KBC
R5F10KGC
R5F10LGA
R5F10LGC
R5F10LGD
R5F10LGE
R5F10PAD
R5F10PAE
R5F10PBD
R5F10PBE

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

31

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
R5F10PGD
R5F10PGE
R5F10PGF
R5F10PGG
R5F10PGH
R5F10PGJ
R5F10PLE
R5F10PLF
R5F10PLG
R5F10PLH
R5F10PLJ
R5F10PME
R5F10PMF
R5F10PMG
R5F10PMH
R5F10PMJ
R5F10PPE
R5F10PPF
R5F10PPG
R5F10PPH
R5F10PPJ
R5F10RB8
R5F10RBA
R5F10RBC
R5F10RF8
R5F10RFA
R5F10RFC
R5F10RG8
R5F10RGA
R5F10RGC
R5F10RJ8
R5F10RJA
R5F10RJC
R5F10RLA
R5F10RLC
R5F10TPJ
R5F10TPK
R5F10TPL
R5F10TSK
R5F10TSL
R5F10UGA

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

32

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
R5F10UGC
R5F10UGD
R5F10UGE
R5F10WLA
R5F10WLC
R5F10WLD
R5F10WLE
R5F10WLF
R5F10WLG
R5F10WMA
R5F10WMC
R5F10WMD
R5F10WME
R5F10WMF
R5F10WMG
R5F10Y14
R5F10Y16
R5F10Y44
R5F10Y46
R5F10Y47
R5F110ME
R5F110MF
R5F110MG
R5F110MH
R5F110MJ
R5F110PE
R5F110PF
R5F110PG
R5F110PH
R5F110PJ
R5F111ME
R5F111MF
R5F111MG
R5F111MH
R5F111MJ
R5F111PE
R5F111PF
R5F111PG
R5F111PH
R5F111PJ
UPD78F1000

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

33

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
UPD78F1001
UPD78F1002
UPD78F1003
UPD78F1004
UPD78F1005
UPD78F1006
UPD78F1007
UPD78F1008
UPD78F1009
UPD78F1010
UPD78F1011
UPD78F1012
UPD78F1013
UPD78F1014
UPD78F1016
UPD78F1017
UPD78F1018
UPD78F1031
UPD78F1032
UPD78F1033
UPD78F1034
UPD78F1035
UPD78F1036
UPD78F1037
UPD78F1038
UPD78F1039
UPD78F1040
UPD78F1041
UPD78F1042
UPD78F1043
UPD78F1044
UPD78F1045
UPD78F1046
UPD78F1047
UPD78F1048
UPD78F1049
UPD78F1050
UPD78F1142
UPD78F1143
UPD78F1144
UPD78F1145

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

34

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
UPD78F1146
UPD78F1152
UPD78F1153
UPD78F1154
UPD78F1155
UPD78F1156
UPD78F1162
UPD78F1163
UPD78F1164
UPD78F1165
UPD78F1166
UPD78F1167
UPD78F1168
UPD78F1174
UPD78F1175
UPD78F1176
UPD78F1177
UPD78F1178
UPD78F1184
UPD78F1185
UPD78F1186
UPD78F1187
UPD78F1188
UPD78F1201
UPD78F1203
UPD78F1211
UPD78F1213
UPD78F1214
UPD78F1215
UPD78F1223
UPD78F1224
UPD78F1225
UPD78F1233
UPD78F1234
UPD78F1235
UPD78F1500
UPD78F1501
UPD78F1502
UPD78F1503
UPD78F1504
UPD78F1505

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

35

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
UPD78F1506
UPD78F1507
UPD78F1508
UPD78F1804
UPD78F1805
UPD78F1806
UPD78F1807
UPD78F1808
UPD78F1809
UPD78F1810
UPD78F1811
UPD78F1812
UPD78F1813
UPD78F1814
UPD78F1815
UPD78F1816
UPD78F1817
UPD78F1818
UPD78F1819
UPD78F1820
UPD78F1821
UPD78F1822
UPD78F1823
UPD78F1824
UPD78F1825
UPD78F1826
UPD78F1827
UPD78F1828
UPD78F1829
UPD78F1830
UPD78F1831
UPD78F1832
UPD78F1833
UPD78F1834
UPD78F1835
UPD78F1836
UPD78F1837
UPD78F1838
UPD78F1839
UPD78F1840
UPD78F1841

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

36

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
UPD78F1842
UPD78F1843
UPD78F1844
UPD78F1845
UPD78F1846
UPD78F1847
UPD78F1848
UPD78F1849
UPD78F8040
UPD78F8041
UPD78F8042
UPD78F8043
UPD78F8056
UPD78F8057
UPD78F8058
UPD78F8070

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

Compilers
Language

Compiler

Company

Option

CC78K0R

XCOFF

C/C++

ICC78K0R

Renesas Technology,
Corp.
IAR Systems AB

Comment

UBROF

Realtime Operation Systems

No operation systems supported.

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

37

Support

3rd Party Tool Integrations

CPU

Tool

Company

ALL
ALL
ALL

ADENEO
X-TOOLS / X32
CODEWRIGHT

ALL

CODE CONFIDENCE
TOOLS
CODE CONFIDENCE
TOOLS
EASYCODE
ECLIPSE
RHAPSODY IN MICROC
RHAPSODY IN C++
CHRONVIEW
LDRA TOOL SUITE
UML DEBUGGER

Adeneo Embedded
blue river software GmbH
Borland Software
Corporation
Code Confidence Ltd

ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL

ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL

ATTOL TOOLS
VISUAL BASIC
INTERFACE
LABVIEW

CODE::BLOCKS
C++TEST
RAPITIME
DA-C
TRACEANALYZER
SIMULINK
TA INSPECTOR
UNDODB
VECTORCAST UNIT
TESTING
VECTORCAST CODE
COVERAGE
WINDOWS CE PLATF.
BUILDER

Host
Windows
Windows
Windows

Code Confidence Ltd

Linux

EASYCODE GmbH
Eclipse Foundation, Inc
IBM Corp.
IBM Corp.
Inchron GmbH
LDRA Technology, Inc.
LieberLieber Software
GmbH
MicroMax Inc.
Microsoft Corporation

Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows

NATIONAL
INSTRUMENTS
Corporation
Open Source
Parasoft
Rapita Systems Ltd.
RistanCASE
Symtavision GmbH
The MathWorks Inc.
Timing Architects GmbH
Undo Software
Vector Software

Windows

Windows
Windows
Windows
Windows
Windows
Windows
Linux
Windows

Vector Software

Windows

Windows

Windows

Products

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

38

Products

Product Information
OrderNo Code

Text

LA-3777

Debugger for 78K0R/RL78 (ICD)

DEBUG-78K0R/RL78

supports 78K0R and RL78 cores (16-bit)

includes software for Windows, Linux and MacOSX
requires Power Debug Interface USB 2.0/USB 3.0,
Power Debug Ethernet, Power Debug II or
PowerDebug PRO

LA-3865

Converter ARM-20 to 78K-16

CON-ARM-78K

Converter 20 pin JTAG ARM to

78K 16 pin NEC

LA-3866

Converter ARM-20 to RL78-14

CON-ARM-RL78

Converter 20 pin JTAG ARM to

RL78 14 pin Renesas

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

39

Products

Order Information
Order No.

Code

Text

LA-3777
LA-3865
LA-3866

DEBUG-78K0R/RL78
CON-ARM-78K
CON-ARM-RL78

Debugger for 78K0R/RL78 (ICD)

Converter ARM-20 to 78K-16
Converter ARM-20 to RL78-14

1989-2016 Lauterbach GmbH

78K0R/RL78 Debugger

40

Products