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ADF4007
Data Sheet
FEATURES
GENERAL DESCRIPTION
APPLICATIONS
Satellite communications
Broadband wireless access
CATV
Instrumentation
Wireless LANs
VDD
ADF4007
CPGND
REFERENCE
R COUNTER
2
RFINA
N COUNTER
8, 16,
32, 64
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
MUXOUT
MUX
N2
N1
GND
M2
CP
M1
04537-001
REFIN
RFINB
RSET
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
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Comparable Parts
Reference Materials
Evaluation Kits
ADF4007 Evaluation Board
Documentation
Application Notes
AN-30: Ask the Applications Engineer - PLL Synthesizers
AN-873: Lock Detect on the ADF4xxx Family of PLL
Synthesizers
Data Sheet
ADF4007: High Frequency Divider/PLL Synthesizer Data
Sheet
User Guides
UG-158: Evaluation Board for the 7.5 GHz PLL Frequency
Synthesizer
Design Resources
Discussions
Tools and Simulations
ADIsimPLL
ADIsimRF
Technical Support
Submit a technical question or find your regional support
number
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
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frequently modified.
ADF4007
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Prescaler P ......................................................................................9
R Counter .......................................................................................9
MUXOUT ................................................................................... 10
Specifications..................................................................................... 3
REVISION HISTORY
7/12Rev. A to Rev. B
Changes to Figure 2 .......................................................................... 5
Changed Applications Section to Applications Information
Section .............................................................................................. 11
Updated Outline Dimensions (Changed CP-20-1 to CP-20-6)...... 14
Changes to Ordering Guide .......................................................... 14
12/09Rev. 0 to Rev. A
Added Exposed Pad Notation to Figure 2 and Table 3.................5
Changes to Table 5.............................................................................6
Changes to Ordering Guide .......................................................... 14
2/04Revision 0: Initial Version
Rev. B | Page 2 of 16
Data Sheet
ADF4007
SPECIFICATIONS
AVDD = DVDD = 3 V 10%, AVDD VP 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 k, dBm referred to 50 ,
TA = TMAX to TMIN, unless otherwise noted.
Table 1.
Parameter
RF CHARACTERISTICS
RF Input Frequency (RFIN)
RF Input Frequency
REFIN CHARACTERISTICS
REFIN Input Sensitivity
REFIN Input Frequency
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency 3
MUXOUT
MUXOUT Frequency3
CHARGE PUMP
ICP Sink/Source
Absolute Accuracy
RSET Range
ICP Three-State Leakage
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VIH, Input High Voltage
VIL, Input Low Voltage
IINH, IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
DVDD
VP
IDD 4 (AIDD + DIDD)
IP
NOISE CHARACTERISTICS
Normalized Phase Noise Floor 5
B Version 1
Unit
Test Conditions/Comments
1.0/7.0
0.5/7.5
GHz min/max
GHz min/max
0.8/VDD
20/240
10
100
V p-p min/max
MHz min/max
pF max
A max
Biased at AVDD/2 2
For f < 20 MHz, use square wave (slew rate > 50 V/s)
120
MHz max
200
MHz max
CL = 15 pF
5.0
2.5
3.0/11
10
2
1.5
2
mA typ
% typ
k typ
nA max
% typ
% typ
% typ
1.4
0.6
1
10
V min
V max
A max
pF max
VDD 0.4
0.4
V min
V max
2.7/3.3
AVDD
AVDD/5.5
17
2.0
V min/max
219
dBc/Hz typ
V min/max
mA max
mA max
TA = 85C
0.5 V VCP VP 0.5 V
0.5 V VCP VP 0.5 V
VCP = VP/2
TA = 25C
IOH = 100 A
IOL = 500 A
AVDD VP 5.5 V
15 mA typ
TA = 25C
Rev. B | Page 3 of 16
ADF4007
Data Sheet
Rating
0.3 V to +3.6 V
0.3 V to +0.3 V
0.3 V to +5.8 V
0.3 V to +5.8 V
0.3 V to VDD + 0.3 V
0.3 V to VP + 0.3 V
0.3 V to VDD + 0.3 V
40C to +85C
65C to +125C
150C
122C/W
ESD CAUTION
215C
220C
6425
303
Rev. B | Page 4 of 16
Data Sheet
ADF4007
20
19
18
17
16
CP
RSET
VP
DVDD
DVDD
1
2
3
4
5
ADF4007
TOP
VIEW
15
14
13
12
11
MUXOUT
M1
M2
N1
N2
NOTES
1. THE LFCSP HAS AN EXPOSED PADDLE THAT
MUST BE CONNECTED TO GROUND.
04537-002
AVDD 6
AVDD 7
REFIN 8
DGND 9
DGND 10
CPGND
AGND
AGND
RFINB
RFINA
Mnemonic
CPGND
AGND
RFINB
5
6, 7
RFINA
AVDD
REFIN
9, 10
11, 12
13, 14
15
16, 17
DGND
N2, N1
M2, M1
MUXOUT
DVDD
18
VP
19
RSET
Description
Charge Pump Ground. The ground return path of the charge pump.
Analog Ground. The ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF.
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
Analog Power Supply. This pin can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
Reference Input. A CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 k.
This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
Digital Ground.
These two bits set the N value. See Table 4.
These two bits set the status of MUXOUT and PFD polarity. See Table 5.
This multiplexer output allows either the N divider output or the R divider output to be accessed externally.
Digital Power Supply. This pin can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
Charge Pump Power Supply. This pin should be greater than or equal to VDD. In systems where VDD is 3 V, it can be
set to 5 V and used to drive a VCO with a tuning range of up to 5 V.
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal
voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
I CPMAX =
20
CP
21
EP
25.5
R SET
Rev. B | Page 5 of 16
ADF4007
Data Sheet
Table 5. M Truth Table
N1
0
1
0
1
N Value
8
16
32
64
M2
0
M1
0
Rev. B | Page 6 of 16
Operation
CP
MUXOUT
PFD polarity
CP
MUXOUT
PFD polarity
CP
MUXOUT
PFD polarity
CP
MUXOUT
PFD polarity:
Description
Active
VDD
+ve
Three-state
R divider output/2
+ve
Active
N divider output
+ve
Active
GND
ve
Data Sheet
ADF4007
MagS11
0.87693
0.85834
0.85044
0.83494
0.81718
0.80229
0.78917
0.77598
0.75578
0.74437
0.73821
0.72530
0.71365
0.70699
0.70380
0.69284
0.67717
0.67107
0.66556
0.65640
0.63330
0.61406
0.59770
0.56550
0.54280
0.51733
0.49909
0.47309
0.45694
0.44698
0.43589
0.42472
0.41175
0.41055
0.40983
0.40182
0.41036
AngS11
19.9279
23.5610
26.9578
30.8201
34.9499
39.0436
42.3623
46.3220
50.3484
54.3545
57.3785
60.6950
63.9152
66.4365
68.4453
70.7986
73.7038
75.8206
77.6851
80.3101
82.5082
85.5623
87.3513
89.7605
93.0239
95.9754
99.1291
102.208
106.794
111.659
117.986
125.620
133.291
140.585
147.970
155.978
162.939
Frequency1
4.30000
4.40000
4.50000
4.60000
4.70000
4.80000
4.90000
5.00000
5.10000
5.20000
5.30000
5.40000
5.50000
5.60000
5.70000
5.80000
5.90000
6.00000
6.10000
6.20000
6.30000
6.40000
6.50000
6.60000
6.70000
6.80000
6.90000
7.00000
7.10000
7.20000
7.30000
7.40000
7.50000
Rev. B | Page 7 of 16
MagS11
0.41731
0.43126
0.42959
0.42687
0.43450
0.42275
0.40662
0.39103
0.37761
0.34263
0.30124
0.27073
0.23590
0.17550
0.12739
0.09058
0.06824
0.04465
0.04376
0.06621
0.08498
0.10862
0.12161
0.12917
0.12716
0.11678
0.10533
0.09643
0.08919
0.08774
0.09289
0.10803
0.13956
AngS11
168.232
174.663
179.797
174.379
171.537
167.201
163.534
159.829
157.633
152.815
147.632
144.304
138.324
131.087
124.568
119.823
114.960
84.4391
34.2210
4.70571
12.6228
26.6069
38.5860
47.1990
55.8515
63.0234
66.9967
75.4961
89.2055
103.786
127.153
150.582
170.971
ADF4007
Data Sheet
VDD = 3V
VP = 3V
10
15
20
TA = +85C
25
TA = +25C
30
30
20
10
TA = 40C
40
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 106MHz
LOOP BANDWIDTH = 1MHz
RES BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 2.5s
AVERAGES = 30
50
60
70
91.0dBc/Hz
04537-007
80
35
90
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
RF INPUT FREQUENCY (GHz)
100
04537-003
40
212
106
6780
106
FREQUENCY (MHz)
212
Figure 6. Reference Spurs (6.78 GHz RFOUT, 106 MHz PFD, and 1 MHz Loop
Bandwidth)
120
VDD = 3V
VP = 5V
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 106kHz
LOOP BANDWIDTH = 1MHz
RES BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9s
AVERAGES = 10
30
40
130
50
60
70
99dBc/Hz
90
100
2k
1k
6780M
FREQUENCY (Hz)
1k
150
160
170
04537-005
80
140
180
10k
2k
Figure 4. Phase Noise (6.78 GHz RFOUT, 106 MHz PFD, and 1 MHz Loop
Bandwidth)
100k
1M
10M
PHASE DETECTOR FREQUENCY (Hz)
10dB/DIV
RL = 40dBc/Hz
RMS NOISE = 4.2
5
4
VP = 5V
ICP = 5mA
60
3
70
80
ICP (mA)
90
100
1
0
1
2
110
120
04537-006
130
140
10k
100k
1M
10M
FREQUENCY OFFSET FROM CARRIER (Hz)
04537-014
120M
40
50
04537-013
20
10
5
6
0
100M
Figure 5. Integrated Phase Noise (6.78 GHz RFOUT, 106 MHz PFD, and 1 MHz
Loop Bandwidth)
Rev. B | Page 8 of 16
0.5
1.0
1.5
2.0
2.5
3.0
VCP (V)
3.5
4.0
4.5
5.0
Data Sheet
ADF4007
THEORY OF OPERATION
REFERENCE INPUT SECTION
PRESCALER P
The prescaler, operating at CML levels, takes the clock from the
RF input stage and divides it down to a manageable frequency
for the PFD. The prescaler can be selected to be either 8, 16, 32,
or 64, and is effectively the N value in the PLL synthesizer. The
terms N and P are used interchangeably in this data sheet. N1
and N2 set the prescaler values. The prescaler value should be
chosen so that the prescaler output frequency is always less than
or equal to 120 MHz, the maximum specified PFD frequency.
Thus, with an RF frequency of 4 GHz, a prescaler value of 64 is
valid, but a value of 32 or less is not valid.
POWER-DOWN
CONTROL
NC
100k
SW2
REFIN
TO R COUNTER
NC
SW1
f VCO = [N ]
BUFFER
f REFIN
2
R COUNTER
SW3
04537-015
NO
RF INPUT STAGE
The RF input stage is shown in Figure 10. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
BIAS
GENERATOR
500
1.6V
AVDD
500
RFINA
CHARGE
PUMP
LOGIC HI
D1
Q1
UP
RFINB
U1
CLR1
3ns
DELAY
AGND
U3
CP
LOGIC HI
CLR2 DOWN
D2 Q2
U2
N DIVIDER
CPGND
Rev. B | Page 9 of 16
04537-017
04537-016
R DIVIDER
ADF4007
Data Sheet
MUXOUT
PFD Polarity
DVDD
CP Output
The CP output state is also controlled by the state of M2 and M1. It
can be set either to active (so that the loop can be locked) or to
three-state (open the loop). The normal state is CP output active.
DVDD
R COUNTER OUTPUT
MUX
CONTROL
MUXOUT
N COUNTER OUTPUT
DGND
04537-018
DGND
Rev. B | Page 10 of 16
Data Sheet
ADF4007
APPLICATIONS INFORMATION
FIXED HIGH FREQUENCY LOCAL OSCILLATOR
KD = 5 mA
KV = 100 MHz/V
Loop Bandwidth = 300 kHz
FPFD = 106 MHz
N = 64
All these specifications are needed and used with the ADIsimPLL
to derive the loop filter component values shown in Figure 13.
The circuit in Figure 13 gives a typical phase noise performance
of 100 dBc/Hz at 10 kHz offset from the carrier. Spurs are
heavily attenuated by the loop filter and are below 90 dBc.
The loop filter output drives the VCO, which, in turn, is fed
back to the RF input of the PLL synthesizer and also drives the
RF output terminal. A T-circuit configuration provides 50
matching between the VCO output, the RF output, and the RFIN
terminal of the synthesizer.
The charge pump output of the ADF4007 drives the loop filter.
In calculating the loop filter component values, a number of items
need to be considered. In this example, the loop filter was designed
so that the overall phase margin for the system is 45.
VCC = 3.3V
AVDD = 3.3V
18k
7
16
18
17
5
4
RFINA
1k
AD820
CP 20
10pF
22
100pF 18
18 100pF
RFOUT
VCO
100MHz/V
47nF
ADF4007
100pF
FREFIN
REFIN
LOGIC HI
11 N2
LOGIC HI
12 N1
LOGIC LO
13 M2
LOGIC LO
14 M1
MUXOUT 15
19 RSET
GND
100pF
NOTE
DECOUPLING CAPACITORS (0.1mF/10pF) ON AVDD, DVDD, AND VP OF THE ADF4007 AND ON
VCC OF THE AD820 AND THE HMC358MS8G HAVE BEEN OMITTED FROM THE DIAGRAM
TO AID CLARITY.
Rev. B | Page 11 of 16
04537-019
GND
GND 10
RSET
5.1k
GND
51
HMC358MS8G
RFINB
5.6nF
100pF
18
VCC = 12V
1k
VP
ADF4007
Data Sheet
VDD
VDD
VVCO
LOCK
DETECT
4.7k
10mF
21
RSET
20
23
MUXOUT VTUNE
CE
14 CN
13k
CHARGE
PUMP
CP 24
1nF 1nF
FREFIN
CP
VP
M2
AVDD DVDD
M1
16 REF
IN
6.8nF
470pF
51
PHASE
FREQUENCY
DETECTOR
MUXOUT
CMOS OUTPUT
MUX
220pF
6.2k
17 CLK
ADF4360-7
18 DATA
VVCO
12 C
C
51
13 RSET
1nF
RFOUTA 4
4.7k
CPGND
1
AGND
3
DGND
11
22
15
L1
L2
10
RFOUTB 5
51
REFIN R COUNTER
2
RFINA
100pF
RFINB
100pF
CPGND GND
2.2nH
N COUNTER
8, 16
32, 64
N1
N2
ADF4007
2.2nH
04537-020
19 LE
Figure 14. Using the ADF4007 to Divide-Down the Output of the ADF4360-7
Rev. B | Page 12 of 16
Data Sheet
ADF4007
Rev. B | Page 13 of 16
ADF4007
Data Sheet
OUTLINE DIMENSIONS
0.30
0.25
0.18
0.50
BSC
PIN 1
INDICATOR
20
16
15
1
EXPOSED
PAD
2.30
2.10 SQ
2.00
11
TOP VIEW
0.80
0.75
0.70
0.65
0.60
0.55
5
10
0.20 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
08-16-2010-B
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
ORDERING GUIDE
Model 1
ADF4007BCPZ
ADF4007BCPZ-RL
ADF4007BCPZ-RL7
EVAL-ADF4007EBZ1
1
Temperature Range
40C to +85C
40C to +85C
40C to +85C
Package Description
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board
Rev. B | Page 14 of 16
Package Option
CP-20-6
CP-20-6
CP-20-6
Data Sheet
ADF4007
NOTES
Rev. B | Page 15 of 16
ADF4007
Data Sheet
NOTES
Rev. B | Page 16 of 16