Instruction Set 1 Rev.

INSTRUCTION SET
Instruction set defines the basic operation that a programmer can specify to the device to perform.
The instruction set of 8086 is divided into five main groups those are:
1.
DATA TRANSFER INSTRUCTIONS
2.
ARITHMETIC and BIT MANIPULATION INSTRUCTIONS
3.
STRING INSTRUCTIONS
4.
PROGRAM EXECUTION TRANSFER INSTRUCTIONS
5.
PROCESS CONTROL INSTRUCTIONS
1. Data Transfer Instructions:
Data Transfer Instructions copy values from one location to an another
1.GENERAL PURPOSE BYTE OR WORD TRANSFER INSTRUCTIONS:
(MOV, PUSH, POP, XCHG, XLAT)
MOV Instruction - The MOV instruction copies a word or a byte of data from a specified source to
a specified destination without modifying the contents of the source.
MOV op1, op2
It will not update any flags

Example:
MOV CX, 037AH ; MOV 037AH into the CX.
MOV AX, BX
;Copy the contents of register BX to AX
MOV DL,[BX] ;Copy byte from memory at BX to DL , BX contains the offset of byte
in DS.
PUSH Instruction - PUSH instruction decrements the stack pointer by 2 and copies a word from a
specified source to the location in the stack segment where the stack pointer points.
PUSH will not update any flags

Example:
PUSH BX ;Decrement SP by 2 and copy BX to stack
PUSH DS ;Decrement SP by 2 and copy DS to stack
PUSH TABLE[BX] ;Decrement SP by 2 and copy word from memory in DS at EA = TABLE + [BX] to stack .
POP Instruction - POP instruction copies the word at the current top of the stack to the operand
specified by op then increments the stack pointer to point to the next stack.
POP will not update any flags

Example:
POP DX
;Copy a word from top of the stack to DX and increments SP by 2.
POP DS
;Copy a word from top of the stack to DS and increments SP by 2.
POP TABLE [BX] ;Copy a word from top of stack to memory in DS with EA = TABLE + [BX].
XCHG Instruction - The Exchange instruction exchanges the contents of the register with the
contents of another register (or) the contents of the register with the contents of the memory
location. Direct memory to memory exchange are not supported.
XCHG will not update any flags
XCHG op1, op2
The both operands must be the same size and one of the operand must always be a register .
Example:
XCHG AX, DX ;Exchange word in AX with word in DX
XCHG BL, CH ;Exchange byte in BL with byte in CH
XCHG AL, Money [BX] ;Exchange byte in AL with byte in memory at EA = Money + BX in DS.
XLAT Instruction: Translate byte from table.
Copy the value of memory byte at DS:[BX + unsigned AL] to AL register.
After execution of the instruction AL = DS:[BX + unsigned AL]
XLAT will not update any flags
Example:
ORG 100h
LEA BX, data

MOV AL, 2
XLATB
; AL = 33h
RET
data DB 11h, 22h, 33h, 44h, 55h
2.SIMPLE INPUT AND OUTPUT PORT TRANSFER INSTRUCTIONS:
(IN, OUT)
IN Instruction - This IN instruction will copy data from a port to the AL or AX register.
For the Fixed port IN instruction an 8 bit address of a port is specified directly in the
instruction.
IN will not update any flags

Example:
IN AL,0C8H
;Input a byte from port 0C8H to AL
IN AX, 34H ;Input a word from port 34H to AX
;A_TO_D EQU 4AH
IN AX, A_TO_D ;Input a word from port 4AH to AX
For a variable port IN instruction, the port address is loaded in DX register before IN instruction.
DX is a16 bit register so, Port address range from 0000H FFFFH.
Example:
MOV DX, FF78H ;Initialize DX point to port
IN AL, DX
;Input a byte from a 8 bit ;port FF78H to AL
IN AX, DX
;Input a word from 16 bit ; port to FF78H to AX.
OUT Instruction - The OUT instruction copies a byte from AL or a word from AX to Out port specified
by op.
Two forms of OUT instruction are available :
(1) Port number is specified by an immediate byte constant, ( 0 - 255 ).It is also called as fixed
port form.
(2) Port number is provided in the DX register ( 0 65535 ). It is also called as Variable port
address.
OUT will not update any flags

Example: (1)
OUT 3BH,AL ;Copy the contents of the AL to port 3Bh
OUT 2CH,AX ;Copy the contents of the AX to port 2Ch
Example (2)
MOV DX, FFF8H ;Load desired port address in DX
OUT DX, AL
; Copy the contents of AL to FFF8h
OUT DX, AX
;Copy content of AX to port FFF8H
3. SPECIAL ADDRESS TRANSFER INSTRUCTIONS
(LEA, LDS, LES)
LEA Instruction
This instruction copies the offset of the variable or memory location named as the source and
put this offset in the indicated 16 bit register.
LEA will not update any flags
Example:
LEA BX, PRICE
;Load BX with offset of PRICE in DS
LEA BP, SS:STACK ;Load BP with offset of STACK in SS
LEA CX, [BX][DI]
;Load CX with EA=BX + DI
LDS Instruction - Load register and DS with words from memory
LDS register, memory address of first word
LDS Instruction loads a far pointer from the memory address specified by op2 into the DS
segment register and the op1 in the register.
LDS will not update any flags
LDS op1, op2

Example:
LDS BX, [4326] ; copy the contents of the memory at displacement 4326H in DS to BL,
contents of the 4327H to BH. Copy contents of 4328H and 4329H in DS to DS register.
LES Instruction - Load register and ES with words from memory
LES register, memory address of first word.
LES Instruction loads a far pointer from the memory address specified by op2 into the ES
segment register and the op1 a register.
LES will not update any flags
LES op1, op2

Example:
LES BX, [1234] ;copy the contents of the memory at displacement 1234H in DS to BL,
contents of the 1235H to BH. Copy contents of 1236H and 1237H in DS to ES register.
4. FLAG TRANSFER INSTRUCTIONS:
(LAHF, SAHF, PUSHF, POPF)
LAHF Instruction -Copy low byte of flags register to AH
LAHF instruction copies the value of SF, ZF, AF, PF, CF, into bits of 7, 6, 4, 2, 0 respectively of
AH register.
This LAHF instruction was provided to make conversion of assembly language programs written
for 8080 and 8085 to 8086 easier.
LAHF & PUSH AX will simulate the 8085 PUSH PSW instruction
LAHF will not update any flags

SAHF Instruction Copy AH register to low byte of flag register
SAHF Instruction - SAHF copies the value of bits 7, 6, 4, 2, 0 of the AH register into the SF, ZF,
AF, PF, and CF respectively. This instruction was provided to make easier conversion of assembly
language program written for 8080 and 8085 to 8086.
POP AX & SAHF is used to simulate the 8085 POP PSW instruction.
All flags SF, ZF, AF, PF, and CF are updated

PUSHF Instruction- Push flag register on the stack
PUSHF Instruction decrements the SP by 2 and copies the word in flags register to the memory
location pointed to by SP.
PUSHF will not update any flags

POPF Instruction POP the word from top of the stack to flags register.
POPF Instruction copies a word from the two memory locations at the top of the stack to flags
register and increments the stack pointer by 2.
POP updates all the flags
Arithmetic Instructions
1. ADDITION INSTRUCTIONS:
(ADD, AAA, ADC, DAA, INC)
ADD Instruction - ADD destination, source ADC Instruction Add
with carry.
ADD Instruction - These instructions add a number from source to a number in the destination
and put the result in the specified destination.
The add with carry instruction ADC, also adds the status of the carry flag into the result.
The source and destination must be of same type, means they must be a byte location or a
word location.
If you want to add a byte to a word, you must copy the byte to a word location and fill the upper
byte of the word with zeroes before adding.
ADD and ADC update all flags

Example:
ADD AL,74H
;Add immediate number 74H to content of AL ADC CL,BL ;Add contents of BL

plus carry status to contents of CL. Results in CL
ADD DX, BX ;Add contents of BX to contents of DX
ADD DX, [SI] ;Add word from memory at offset [SI] in DS to contents of DX;
Addition of Un Signed numbers
ADD CL, BL ;CL = 0111 0011(73H) =115 decimal + BL = 0100 1111(4FH) = 79 decimal
;Result in CL = 1100 0010(C2H)= 194 decimal CF=0, ZF=0, SF=1, AF=1, PF=0,
OF=1
Addition of Signed numbers
ADD CL, BL ;CL = 0111 0011(73H) = + 115 decimal + BL = 0100 1111(4FH) =
decimal
;Result in CL = 1100 0010(C2H) = - 62 decimal
; Incorrect because result is too large to fit in 7 bits.
+79
INC Instruction - Increments destination.
INC Instruction adds one to the operand and sets the flags according to the result.
INC instruction is treated as an unsigned binary number. INC updates all flags except
CF
Example:
AX = 7FFFh
INC AX
;After this instruction AX = 8000h INC BL ;Add 1 to the contents of BL register
INC CX
;Add 1 to the contents of CX register.
AAA Instruction - ASCII Adjust after Addition
Corrects result in AH and AL after addition when working with unpacked BCD values.
AAA Instruction - AAA converts the result of the addition of two valid unpacked BCD digits to a
valid 2-digit BCD
number and takes
the AL register as its
implicit operand.
Two operands of the addition must have its lower 4 bits contain a number in the range
from 0-9.
The AAA instruction then adjust AL, so that it contains a correct BCD digit.
If the addition produce carry (AF=1), the AH register is incremented and the carry CF and auxiliary carry AF flags are set to 1.
If the addition did not produce a decimal carry, CF and AF are cleared to 0 and AH is not altered. In both cases the higher 4 bits of AL are cleared to 0.
AF and CF are updated remaining flags are undefined
It works according to the following Algorithm:

if low nibble(AL.0F) of AL > 9 or AF = 1 then:
AL = AL + 6
AH = AH + 1
AF = 1
CF = 1
else
AF = 0
CF = 0
In both the cases it clears the high nibble of AL
Example:
MOV AH,0
MOV AL,6
ADD AL,5
AAA
CF=1 and AF=1
;Clear AH for MSD

;BCD 6 in AL
00000110
;Add BCD 5 to digit in AL +00000101(= 00001011=0BH)
00000110
00010001
;AH=1, AL=1 representing BCD 11.
DAA Instruction - Decimal Adjust Accumulator

Decimal adjust After Addition.
Corrects the result of addition of two packed BCD values.
DAA updates SF, ZF, PF, CF and AF
OF is undefined
Algorithm:
if low nibble of AL > 9 or AF = 1 then:
AL = AL + 6
AF = 1
if AL > 9Fh or CF = 1 then:
AL = AL + 60h
CF = 1
Example:
MOV AL, 09h ;AL = 09h
ADD AL,06h
; add 06 to AL, result in AL=0Fh DAA
RET
; AL = 15 Decimal
2. SUBTRACTION INSTRUCTIONS:
(SUB, SBB, DEC, NEG, CMP, AAS, DAS)
SUB Instruction Subtract source from destination
SBB Instruction Subtracts source from destination with borrow.
SUB destination, source
SBB destination, source
SBB Instruction subtracts op2 from op1, then subtracts 1 from op1 if CF flag is set, and the
result is stored in op1.
SUB and SBB update all the six flags.

Example:
SUB CX, BX ;CX BX . Result in CX
SBB CH, AL ; Subtract contents of AL and contents of CF from contents of CH.Result in CH
SUB AX, 3427H ;Subtract immediate number from AX
Example:
Subtracting unsigned number
; CL = 1001 1100 = 156 decimal
; BH = 0011 0111 = 55 decimal
SUB CL, BH ; CL = 0110 0101 = 101 decimal

; CF, AF, SF, OF, ZF = 0, PF = 1
Subtracting signed number
; CL = 0010 1110 = + 46 decimal
; BH = 0100 1010 = + 74 decimal
SUB CL, BH ; CL = 1110 0100 = - 28 decimal
;CF = 1, AF, ZF =0,OF=0, PF=1
;SF = 1 result negative
DEC Instruction - Decrement destination register or memory
DEC destination.
DEC updates all the flags except CF.
Decrement Algorithm: Operand = operand - 1

Example:
MOV AL, 255 ; AL = 0FFh =1111 1111 (255 or -1)
DEC AL
; AL = 0FEh =1111 1110 (254 or -2)
RET
SF=1, AF=0, PF=0, OF=0,ZF=0, CF =?
NEG Instruction - From 2s complement
NEG destination
NEG Instruction converts the number into twos complement by subtraction of the operand from
zero and sets the flags according to the result.
NEG updates all the flags
Carry flag will set for non zero operand and reset for zero operand.
Example:
;AX = 2CBh (0000 0010 1100 1011)
NEG AX ;after executing NEG result AX =FD35h. AX= 1111 1101 0011 0101
SF=1,ZF=0,CF=1,AF=1,PF=1,OF=0 (not -32,768,or -128)
NEG AL ;Replace number in AL with its 2s complement
NEG BX ;Replace word in BX with its 2s complement
NEG BYTE PTR[BX] ; Replace byte at offset BX in DS with its 2s complement
CMP Instruction - Compare byte or word
CMP destination, source.
Compare performs subtraction of source operand from destination operand CMP updates all
flags
Algorithm:
operand1 - operand2
Result is not stored anywhere, flags are set (OF, SF, ZF, AF, PF, CF) according to result.
Example:
MOV AL, 5
MOV BL, 5
CMP AL, BL ; AL = 5,
RET
SF=0, CF=0,AF=0, PF=1,OF=0, ZF = 1 (so equal!)
AAS Instruction - ASCII Adjust for Subtraction

AAS Instruction - AAS converts the result of the subtraction of two valid unpacked BCD digits
to a single valid BCD number and takes the AL register as an implicit operand.
The two operands of the subtraction must have its lower 4 bits in the range from 0 to 9 .
The AAS instruction then adjust AL so that it contain a correct BCD digit.
AF and CF are updated
OF,SF,ZF and PF are undefined
Example
(a)
SUB AL, BL
AAS
;AL =0011 1001 =ASCII 9

;BL=0011 0101=ASCII 5
;(9 - 5) Result :
;AL = 0000 0100 = BCD 04,CF = 0
;Result :
;AL=00000100 =BCD 04
;CF = 0 NO Borrow required
(b)
;AL = 0011 0101 =ASCII5
;BL= 0011 1001 = ASCII 9
SUB AL, BL ;( 5 - 9 ) Result :
;AL = 1111 1100 = - 4 in 2s complement and CF = 1
AAS
;Results :
;AL = 0000 0100 =BCD 04 ;CF = 1 borrow needed .
DAS Instruction - Decimal Adjust after Subtraction
Decimal adjust After Subtraction Corrects the result of subtraction of two packed BCD values.
All flags are updated except OF

Algorithm:
if low nibble of AL > 9 or AF = 1 then:

AL = AL - 6
AF = 1
if AL > 9Fh or CF = 1 then:
AL = AL - 60h CF = 1
Example:
MOV AL, 49(BCD) ; AL = 49(BCD)
=0100 1001
SUB AL, 72(BCD)
; subtract 72 from 49; 0111 0010
result in AL=D7h
=
1101 0111 CF=1
DAS
;
(-60)
0110 0000
RET ;AL = 77 BCD
0111 0111
Higher nibble is greater than 9 so 60 should be subtracted
CF = 1 indicates barrow is needed that means result is in 9s complement form SF, ZF, CF, AF,
PF are updated but OF is undefined
3. MULTIPLICATION INSTRUCTIONS:
(MUL, IMUL, AAM)
MUL Instruction - Multiply unsigned bytes or words
MUL source
MUL Instruction multiplies an unsigned number in the accumulator by the operand specified by
op. The op may be a register or memory operand .
MUL op
MUL updates OF and CF remaining flags are undefined
OF & CF will set if high byte(AH) or high word(DX) of the result is not zero OF & CF will reset
otherwise.
Example:
;AL = 21h (33 decimal) ;BL = A1h(161 decimal )
MUL BL
;AX =14C1h (5313 decimal) ; since AH0, CF and OF will set to 1.
MUL BH ; AL times BH, result in AX
MUL CX ;AX times CX, result high word in DX, low word in AX.
IMUL Instruction - Multiply signed numbers
IMUL Source
IMUL Instruction performs a signed multiplication.
IMUL op ;
In this form the accumulator is the multiplicand and op is the multiplier. op may be a register or a
memory operand.
IMUL op1, op2 ;In this form op1 is always be a register operand and op2 may be a register or
a memory operand.
IMUL updates OF and CF remaining flags are undefined
If the upper byte of the 16-bit result or the upper word of the 32-bit result contains only the
copies of the sign bit(all 0s or all1s), then CF and OF will both be 0, If the upper byte of the 16bit result or the upper word of the 32-bit result contains part of the product, CF and OF will both
be 1.
Example:
IMUL BH ;Signed byte in AL times by
;signed byte in BH and result in AX .
Numerical example (a)
; 69 * 14
; AL = 01000101 = 69 decimal
; BL = 00001110 = 14 decimal
IMUL BL ;AX = 03C6H = + 966 decimal
;MSB = 0 because positive result
(b)
; - 28 * 59
; AL = 11100100 = - 28 decimal
; BL = 00111011 = +59 decimal
IMUL BL ; AX = F98Ch = - 1652 decimal
; MSB = 1 because negative result
AAM Instruction - ASCII adjust after Multiplication
AAM Instruction converts the result of the multiplication of two valid unpacked BCD digits into a
valid 2-digit unpacked BCD number and takes AX as an implicit operand.
To give a valid result the digits that have been multiplied must be in the range of 0 9 and the
result should have been placed in the AX register.
Because both operands of multiplication are required to be 9 or less, the result must be less
than 81 and thus is completely contained in AL.
AAM unpacks the result by dividing AX by 10, placing the quotient (MSD) in AH and the
remainder (LSD) in AL.
AAM updates SF, ZF and PF
OF,AF and CF are undefined

Example:
MOV AL, 5
MOV BL, 7
MUL BL ;Multiply AL by BL , result in AX
AAM
;After AAM, AX =0305h (BCD 35)
4. DIVISION INSTRUCTIONS:
(DIV ,IDIV, AAD, CBW, CWD)
DIV Instruction - Unsigned divide
DIV source
DIV Instruction is used to divide an Unsigned word by a byte or to divide an unsigned double
word by a word.
When dividing a word by a byte , the word must be in the AX register.
After the division AL will contains an 8- bit result (quotient) and AH will contain an 8- bit
remainder.
If an attempt is made to divide by 0 or the quotient is too large to fit in AL ( greater than FFH ),
the 8086 will automatically do a type 0 interrupt .
All the flags are undefined

Example:
DIV BL
;Word in AX / byte in BL
;Quotient in AL
;Remainder in AH.
When a double word is divided by a word, the most significant word of the double word must be
in DX and the least significant word of the double word must be in AX.
After the division AX will contain the 16 bit result (quotient ) and DX will contain a 16 bit
remainder.
Again , if an attempt is made to divide by zero or quotient is too large to fit in AX ( greater than
FFFFH ) then 8086 will do a type 0 interrupt .
Example:
DIV CX
; (Quotient) AX= (DX:AX)/CX
; (Reminder) DX=(DX:AX)%CX
For DIV the dividend must always be in AX or DX and AX, but the source of the divisor can be a
register or a memory location specified by one of the 24 addressing modes.
If you want to divide a byte by a byte, you must first put the dividend byte in AL and fill AH with
all 0s .
The SUB AH,AH instruction is a quick way to do.
If you want to divide a word by a word, put the dividend word in AX and fill DX with all 0s.
The SUB DX,DX instruction does this quickly.

Example:
DIV BH
; AX = 37D7H = 14, 295 decimal

; BH = 97H = 151 decimal
;AX / BH
; AL = Quotient = 5EH = 94 decimal
; AH = Remainder = 65H = 101 decimal
IDIV Instruction - Divide by signed byte or word IDIV source
IDIV Instruction - This instruction is used to divide a signed word by a signed byte or to divide a
signed double word by a signed word.
All the flags are undefined

Example:
IDIV BL ;Signed word in AX is divided by signed byte in BL
IDIV BP ;Divide a Signed double word in DX and AX by signed word in BP
IDIV BYTE PTR[BX] ; divide AX by a byte at offset [BX] in DS
A signed word divided by a signed byte

;AX = 00000011 10101011 = 03ABH=939 decimal
;BL = 11010011 = D3H = - 2DH = - 45 decimal
IDIV BL
;Quotient AL= ECH = - 14H = -20 decimal
;Remainder AH = 27H = + 39 decimal
AAD Instruction - ASCII adjust before Division
AAD Instruction converts unpacked BCD digits in the AH and AL register into a single binary
number in the AX register in preparation for a division operation.
Before executing AAD, place the Most significant BCD digit in the AH register and Least
significant in the AL register.
When AAD is executed, the two BCD digits are combined into a single binary number by setting
AL=(AH*10)+AL and clearing AH to 0.
AAD updates SF, ZF and PF
OF,AF and CF are undefined

Example:
MOV AX,0205h
;The unpacked BCD number 25
AAD
;After AAD , AH=0 and ;AL=19h (25)
After the division AL will then contain the unpacked BCD quotient and AH will contain the
unpacked BCD remainder.
Example:
;AX=0607 unpacked BCD for 67 decimal
;CH=09H
AAD
;Adjust to binary before division
;AX=0043 = 43H =67 decimal
DIV CH ;Divide AX by unpacked BCD in CH
;AL = quotient = 07 unpacked BCD
;AH = remainder = 04 unpacked BCD
CBW Instruction - Convert signed Byte to signed word
CBW Instruction converts the signed value in AL register into an equivalent 16 bit signed value
in the AX register by duplicating the sign bit to the left.
This instruction copies the sign of a byte in AL to all the bits in AH. AH is then said to be the sign
extension of AL.
None of the flags are updated

Example:
;AH = 00000000
;AL = 10011011 = - 155 decimal
CBW ;Convert signed byte in AL to signed to word in AX.
;Result in AX = 11111111 10011011
; = - 155 decimal
CWD Instruction - Convert Signed Word to - Signed Double word
CWD Instruction converts the 16 bit signed value in the AX register into an equivalent 32 bit
signed value in DX: AX register pair by duplicating the sign bit to the left.
The CWD instruction sets all the bits in the DX register to the same sign bit of the AX register.
The effect is to create a 32- bit signed result that has same integer value as the original 16 bit
operand.

Example:
Assume AX contains C435h. If the CWD instruction is executed, DX will contain FFFFh since bit
15 (MSB) of AX was 1.
Both the original value of AX (C435h) and resulting value of DX : AX (FFFFC435h) represents
the same signed Number
Example:
;DX = 00000000 00000000
;AX = 11110000 11000111 = - 3897 decimal
CWD
;Convert signed word in AX to signed double ;word in DX:AX

;Result DX = 11111111 11111111
;AX = 11110000 11000111 = -3897 decimal
.
Bit Manipulation Instructions:
1. LOGICAL INSTRUCTIONS:
(NOT, AND, OR, XOR, TEST)
NOT Instruction - Invert each bit of operand
NOT destination
NOT Instruction perform the bitwise complement of op and stores the result back into op.
NOT op

Example :
NOT BX
NOT DX
;Complement contents of BX register.

;DX =F038h
;after the instruction DX = 0FC7h
AND Instruction It logically ANDs the corresponding bits of two operands
AND Instruction Performs a bitwise Logical AND of two operands. The result of the operation is
stored in the op1 and used to set the flags.
SF,ZF and PF are updated according to the result, CF& OF are reset and AF is undefined
AND op1, op2
To perform a bitwise AND of the two operands, each bit of the result is set to 1 if and only if the
corresponding bit in both of the operands is 1, otherwise the bit in the result is cleared to 0 .
Example:
AND BH, CL
;AND byte in CL with byte in BH

;result in BH
AND BX,00FFh ;AND word in BX with immediate
;00FFH. Mask upper byte, leave
;lower unchanged
Example
AND CX,[SI]
; AND word at offset [SI] in data

;segment with word in CX ;register . Result in CX register .
;BX = 10110011 01011110
AND BX,00FFh ;Mask out upper 8 bits of BX
;Result BX = 00000000 01011110 ;CF =0 , OF = 0, PF = 0, SF = 0 , ZF = 0
OR Instruction - Logically OR corresponding of two operands OR destination, source.

OR Instruction perform the bit wise logical OR of two operands .
Each bit of the result is cleared to 0 if and only if both corresponding bits in each operand are 0,
other wise the bit in the result is set to 1.
OR op1, op2
SF,ZF and PF are updated according to the result, CF and OF are reset and AF is
undefined
Examples :
OR AH, CL
;CL ORed with AH, result in AH.

;CX = 00111110 10100101
OR CX,FF00h
;OR CX with immediate FF00h

;result in CX = 11111111 10100101
;Upper byte are all 1s lower bytes are unchanged.
SF=1, ZF=0, and PF=1, CF& OF=0
XOR Instruction - Exclusive OR corresponding bits of two operands .

XOR destination, source
XOR Instruction performs a bit wise logical XOR of the operands specified by op1 and op2. The
result of the operand is stored in op1 and is used to set the flag.
XOR op1, op2
undefined
Example : ( Numerical )
; BX = 00111101 01101001
; CX = 00000000 11111111
XOR BX, CX ;Exclusive OR CX with BX ;Result BX = 00111101 10010110
TEST Instruction AND operand to update flags
TEST Instruction ANDs the contents of a source byte or word with the contents of specified
destination byte or word. Flags are updated but neither operand is changed .
TEST instruction is often used to set flags before a condition jump instruction
undefined
Examples:
TEST AL, BH ;AND BH with AL. no result is stored . Update PF, SF, ZF
TEST CX, 0001H
;AND CX with immediate number

;no result is stored,
Updates ZF,PF&SF
Example :
TEST AL, 80H
;AL = 01010001
;AND immediate 80H with AL to test MSB of AL is 1 or 0
;ZF = 1 since MSB of AL = 0
;AL = 01010001 (unchanged)
;PF = 0 , SF = 0 & ZF = 1 because ANDing produced is 00
2. SHIFT INSTRUCTIONS:
(SHL / SAL, SHR, SAR)
SHL/SAL Instruction - Shift operand bits left, put zero in LSB(s)
SHL/SAL destination, count
SHL / SAL Instruction shifts the bits in the operand specified by op1 to its left by the count
specified in op2.
As a bit is shifted out of LSB position a 0 is kept in LSB position.
CF will contain MSB bit.
CF, PF, SF and ZF are updated, AF is undefined and OF is undefined if count >1.
PF will have meaning only for an 8-bit operand
SAL op1,op2
Example:
;CF = 0, BX = 1110 0101 1101 0011
SAL BX, 1
;Shift BX register contents by 1 bit position towards left
;CF = 1, BX = 1100 1011 1010 0110

SHR Instruction - Shift operand bits right, put zero in MSB
SHR Instruction shifts the bits in op1 to right by the number of times specified by op2 .
CF, PF, and ZF are updated, AF is undefined and OF is undefined if count >1.
PF will have meaning only for an 8-bit destination.

Example: (1)
SHR BP, 1 ; Shift word in BP by 1 bit position to right and 0 is kept to MSB
Example (2)
MOV CL, 03H ;Load desired number of shifts into CL
SHR BYTE PTR[BX], CL ;Shift bytes in DS at offset BX and rotate 3 bits to right and keep three 0s in MSB
Example (3)
;SI = 10010011 10101101 , CF = 0
SHR SI, 1 ; Result: SI = 01001001 11010110 ; CF = 1, OF = 1, ZF = 0
SAR Instruction - Shift operand bits right, new MSB = old MSB
SAR destination, count.
SAR Instruction shifts the bits in the operand specified by op1 towards right by count specified
in op2.As bit is shifted out a copy of old MSB is taken in MSB position and LSB is shifted to CF.
CF, PF, and ZF are updated, AF is undefined and OF is undefined if count >1.
For a count of one, OF will be a 1 if the two MSBs are not the same.
PF will have meaning only for an 8-bit destination.
SAR op1, op2

Example: (1)
; AL = 00011101 = +29 decimal, CF = 0
SAR AL, 1
;Shift signed byte in AL towards right ( divide by 2 )
;AL = 00001110 = + 14 decimal, CF = 1, OF=0
Example ( 2 )
;BH = 11110011 = - 13 decimal, CF = 1
SAR BH, 1
;Shifted signed byte in BH to right
;BH = 11111001 = - 7 decimal, CF = 1
3. ROTATE INSTRUCTIONS:
(ROL, ROR, RCL, RCR)
ROL Instruction - Rotate all bits of operand left, MSB to LSB
ROL destination, count.
ROL Instruction rotates the bits in the operand specified by op1 towards left by the count
specified in op2. ROL moves each bit in the operand to next higher bit position. The higher
order bit is moved to lower order position. Last bit rotated is copied into carry flag.
CF is updated and OF undefined if Count>1
ROL op1, op2

Example: ( 1 )
ROL AX, 1
;Word in AX is moved to left by 1 bit and MSB bit is to LSB, and CF
;CF =0 ,BH =10101110
ROL BH, 1
;Result: CF =OF =1 , BH = 01011101
Example : ( 2 )
;BX = 01011100 11010011
;CL = 8 bits to rotate
ROL BH, CL ;Rotate BX 8 bits towards left
;CF =0, BX =11010011 01011100
ROR Instruction - Rotate all bits of operand right, LSB to MSB
ROR destination, count
ROR Instruction rotates the bits in the operand op1 to wards right by count specified in op2. The
last bit rotated is copied into CF.
ROR op1, op2

Example: ( 1 )
ROR BL, 1
;Rotate all bits in BL towards right by 1 bit position, LSB bit is moved to MSB
;and CF has last rotated bit.
Example( 2 )
;CF =0, BX = 00111011 01110101
ROR BX, 1 ;Rotate all bits of BX of 1 bit position towards right and CF =OF=1, BX = 10011101 10111010
Example ( 3 )
;CF = 0, AL = 10110011,
MOV CL, 04H ; Load CL with the count
ROR AL, CL ;Rotate all bits of AL towards right
;by 4 bits, CF = 0 ,AL = 00111011
RCL Instruction - Rotate operand around to the left through CF
RCL destination, source.
RCL Instruction rotates the bits in the operand specified by op1 towards left by the count
specified in op2.
The operation is circular, the MSB of operand is rotated into the carry flag and the bit in the CF
is rotated around into the LSB of operand.
RCR op1, op2

Example:
CLC
;put 0 in CF
RCL AX, 1
;save higher-order bit of AX in CF
RCL DX, 1
;save higher-order bit of DX in CF
ADC AX, 0
;set lower order bit if needed.
Example :
RCL DX, 1 ;Word in DX of 1 bit is moved to left, and MSB of word is given to CF and CF to LSB.
; CF=0, BH = 10110011
RCL BH, 1 ;Result : BH =01100110
;CF = 1, OF = 1 because MSB changed
;CF =1,AX =00011111 10101001
MOV CL, 2 ;Load CL for rotating 2 bit position
RCL AX, CL ;Result: CF =0, OF undefined
;AX = 01111110 10100110
RCR Instruction
Rotate operand around to the right through CF
RCR destination, count
RCR Instruction rotates the bits in the operand specified by op1 towards right by the count
specified in op2.
RCR op1, op2

Example:( 1)
RCR BX, 1 ;Word in BX is rotated by 1 bit towards ;right and CF will contain MSB bit and
;LSB contain CF bit .
Example ( 2)
;CF = 1, BL = 00111000
RCR BL, 1 ;Result: BL = 10011100, CF =0
;OF = 1 because MSB is changed to 1.
.
String Instructions:
REP
REPE / REPZ
REPNE / REPNZ
MOVS / MOVSB / MOVSW
COMPS / COMPSB / COMPSW
SCAS / SCASB / SCASW
LODS / LODSB / LODSW
STOS / STOSB / STOSW
REP:
Repeat is a Prefix.
Repeat String instruction repeats as long as CX 0
Repeat following MOVSB, MOVSW, LODSB, LODSW, STOSB, STOSW instructions CX times.
Algorithm:
check_cx:
if CX 0 then
do following chain instruction
CX = CX - 1
go back to check_cx
else
exit from REP cycle
ZF is updated
REPE/REPZ
Repeat String instruction repeats until specified condition exists.
Repeat following CMPSB, CMPSW, SCASB, SCASW
instructions while ZF = 1 (result is Equal/zero), maximum CX times. Algorithm: check_cx:
if CX 0 then
CX = CX - 1
if ZF = 1 then:
go back to check_cx
else
exit from REPE cycle
ZF is updated
REPNE/REPNZ:
Repeat String instruction repeats until specified condition exist
Repeat following CMPSB, CMPSW, SCASB, SCASW
instructions while ZF = 0 (result is Not Equal/ Not Zero), maximum CX times.
Algorithm:
check_cx:
if CX 0 then
CX = CX - 1
if ZF = 0 then:
go back to check_cx
else
exit from REPNE cycle

ZF is updated
MOVS/MOVSB/ MOVSW Instruction - Move string byte or string word

MOVS destination, Source
Copy byte at DS:[SI] to ES:[DI]. Or Copy word at DS:[SI] to ES:[DI]. Update SI and DI.
Algorithm:
ES:[DI] = DS:[SI]
if DF = 0 then
SI = SI + 1 and DI = DI + 1 for byte transfer or SI = SI + 2 and DI = DI + 2 for word transfer
else
SI = SI - 1 and DI = DI - 1 for byte transfer or SI = SI - 2 and DI = DI - 2 for word transfer
All the flags are unchanged
Example:
a1 DB 1,2,3,4,5 / DW 1, 2, 3, 4, 5
a2 DB 5 DUP(0)/ DW 5DUP(0)
ORG 100h
CLD
LEA SI, a1
LEA DI, a2
MOV CX, 5
REP MOVSB/ MOVSW
RET
a1 1, 2, 3, 4, 5
a2 1, 2, 3, 4, 5
CMPS/CMPSB/CMPSW Instruction - Compare string bytes or string words

Compare bytes/ words: ES:[DI] from DS:[SI].
Algorithm:
DS:[SI] - ES:[DI]
Set all flags according to result:
if DF = 0 then
SI = SI + 1 and DI = DI + 1 for byte strings or
SI=SI+2 and DI=DI+2 for word strings else
SI = SI - 1 and DI = DI - 1 for byte strings or SI=SI2 and DI=DI-2 for word strings
Example:
MOV SI, Offset line
; Address of the line
MOV DI, Offset Table
; Address of the table
CLD
; auto increment
MOV CX,10
; Counter
REPE CMPSB
; Search
RET
This program compares two sections of memory searching for a match. This causes the
search to continue as long as an equal condition exists
SCAS/SCASB/SCASW
Compare bytes in AL or words in AX with bytes or words in the memory ES:[DI].
Algorithm:
ES:[DI] AL for byte operation or ES:[DI] AX for word operation
sets all flags according to result:
if DF = 0 then
DI = DI + 1 for byte operation or DI +2 for word operation else

DI = DI - 1 for byte operation or DI 2 for word operation
Example: (1)
MOV DI, Offset Block ; address data
CLD
; auto increment
MOV CX, 100
; load counter
XOR AL, AL
; clear AL
REPNE SCASB
; search
This program checks a part of memory if it contains 00H using SCASB
Repeats as long as CX0 and ZF =0, and comes out of loop when CX=0 and ZF=0 means
there is no 00H in the string or CX0 and ZF=1 means that 00H is present in the string and
DI is pointed to memory location next to the location which contains 00H
Example (2)
CLD
; Auto increment
MOV CX, 256
; Counter
MOV AL, 20H
; get data 20H (Space)
REPE SCASB
; search
RET
CX=0 and ZF=1; or CX 0 and ZF=0 are two conditions which stop repetition
LODS/LODSB/LODSW Instruction
This instruction copies a byte from a string location pointed by SI to AL or a word from a string
location pointed by SI to AX.
If DF is cleared to 0,SI will automatically incremented to point to the next element of string.
Load byte/word at DS:[SI] into AL/AX. Update SI.
then SI = SI + 1 for byte operation or SI=SI+2 for word operation else

SI = SI - 1 for byte operation or SI=SI - 2 for word operation
Example:
ORG 100h
LEA SI, a1
MOV CX, 5 m: LODSB
INT 10h
LOOP m
RET
a1 DB 'H', 'e', 'l', 'l', 'o'
Example:
ORG 100h
LEA SI, a1
MOV CX, 5
REP LODSW
RET
a1 dw 111h, 222h, 333h, 444h, 555h ; finally there will be 555h in AX.
STOS/STOSB/STOSW:
Store byte in AL/AX into ES:[DI]. Update DI.
Algorithm:
ES:[DI] = AL
if DF = 0
then DI = DI + 1 for byte operation and DI=DI+2 for word operation else
DI = DI - 1 for byte operation and DI=DI -2 for word operation
Example:
a1 DB 5 dup(0)
ORG 100h
LEA DI, a1
MOV AL, 12h
MOV CX, 5
REP STOSB
RET
a1 12,12,
12,12,12
12, 12
Example:
a1 DW 5 dup(0)
ORG 100h
LEA DI, a1
MOV AX, 1234h
MOV CX, 5
REP STOSW
RET
a1 1234,1234, 1234, 1234, 1234
Program Execution Transfer Instructions:
1. UNCONDITIONAL TRANSFER INSTRUCTIONS:
(CALL, RET, JMP)
CALL Instruction
Direct within-segment (near or intrasegment)

Indirect within-segment (near or intrasegment)
Direct to another segment (far or intersegment)
Indirect to another segment (far or intersegment)
CALL Instruction - This Instruction is used to transfer execution to a subprogram or procedure
There are two basic types of CALL s : Near and Far.
A Near CALL is a call to a procedure which is in the same code segment as the CALL
instruction .
When 8086 executes the near CALL instruction it decrements the stack pointer by two and
copies the offset of the next instruction after the CALL on the stack.
This offset saved on the stack is referred as the return address, because this is the address
that execution will return after the procedure executes.
A near CALL instruction will also load the instruction pointer with the offset of the first instruction
in the procedure
A RET instruction at the end of the procedure will return execution to the instruction after the
CALL by coping the offset saved on the stack back to IP.
A Far CALL is a call to a procedure which is in a different segment from that which contains the
CALL instruction .
When 8086 executes the Far CALL instruction it decrements the stack pointer by two and
copies the content of CS register to the stack.
It then decrements the stack pointer by two again and copies the offset of the instruction after
the CALL to the stack.
Finally it loads CS with segment base of the segment which contains the procedure and IP with
the offset of the first instruction of the procedure in the segment.
A RET instruction at end of procedure will return to the next instruction after the CALL by
restoring the saved CS and IP from the stack.
All the flags are unchanged with CALL
Direct within-segment ( near or intra segment )
Example:
CALL MULTO ;MULTO is the name of the procedure.

The assembler determines displacement of MULTO from the instruction after the CALL and
codes this displacement as part of the instruction .
Indirect within-segment ( near or intrasegment )

Example:
CALL BX ; BX contains the offset of the first instruction of the procedure.
Replaces contents of word in IP with contents of register BX.
Example
CALL WORD PTR[BX] ;Offset of first instruction of procedure is in two memory addresses in
DS.
Replaces contents of IP with contents of word memory location in DS pointed by BX.
Direct to another segment- far or intersegment.
CALL SMART ;SMART is the name of the Procedure

SMART PROC FAR ; Procedure must be declare as far
An Indirect call to another segment- Far or intersegment call new value for CS is fetched from [BX]&
[BX+1] for IP from [BX+2]&[BX+3]
Example: CALL DWORD PTR[BX]
RET Instruction Return execution from procedure to calling program.
Return instruction removes 16 bits number (near return) from the stack and places it into IP or
32 bit number (far return) and places it into IP and CS.
The near and far return instructions are both defined in the procedures PROC directive
Example:
ORG 100h
CALL p1
ADD AX, 1
RET
p1 PROC
MOV AX, 1234h
RET
ENDP
; for COM file.

; return to OS.
; procedure declaration.
; return to caller. P1
JMP Instruction - Unconditional jump to - specified destination
This is the main program control instruction.

Jump (JMP) allows the programmer to skip a section of a program and branch to any part of
the memory for next instruction.
There are three types of unconditional jump instructions, those are:
Short jump, Near jump, and Far jump.
Short jump is a 2- byte instruction that allows jumps or branches to memory locations within
+127 and -128 bytes from the address following the jump
The 3- byte near jump allows a branch or jump within 32K bytes (any where in the current
segment) from the instruction in current code segment.
Remember that the segment are cyclical means that one location above FFFFH is offset
address 0000H.
Finally 5 byte far jump allows a jump to any location within the entire real memory (1MB)
system.
The short and near jumps are often called as intra segment jumps , and the far jump is called
as inter segment jump.
Unconditional Jump Transfers control to another part of the program.
4-byte address may be entered in this form: 1234h:5678h, first value is a segment second
value is an offset.
Algorithm: always jump

Example:
ORG 100h
MOV AL, 5
JMP label1
PRINT
MOV AL, 0
Label1:
RET
; jump over 2 lines!

; 'Not Jumped!
PRINT
;'Got Here!
2. CONDITIONAL TRANSFER INSTRUCTIONS:

Conditional jump instructions are always short jumps in 8086 through 80286 processors. this
limits the range of jump to within +127 bytes and -128 bytes from the location following the
conditional jump. In 80386 and above the conditional jump can be to any location within the
current segment.
Conditional Jump instructions test the flag bits.

Because both signed and unsigned numbers are used in the programs, there are two sets of
conditional jump instructions for magnitude comparisons.
When signed numbers are compared, The terms greater than and less than are used.
The terms above and below refers to unsigned numbers
The number 0111 is above 0010 in unsigned numbers
The number 0000 0111 is greater than 1110 1010 in signed numbers
JA/JNBE Instruction - Jump if above/Jump if not below nor equal.
This instruction performs the Jump if above (or) Jump if not below or equal operations
according to the condition, if CF and ZF = 0 .
Example: (1)
CMP AX, 4371H ;Compare by subtracting 4371H from AX
JA RUN_PRESS ;Jump to label RUN_PRESS if AX above 4371H
Example: (2)
CMP AX, 4371H
;Compare ( AX 4371H)
JNBE RUN_PRESS ;Jump to label RUN_PRESS if AX not below or equal to
4371H
JAE/JNB/JNC Instructions - Jump if above or equal/Jump if not below/Jump if no carry.
This instruction performs the Jump if above or equal (or) Jump if not below operations
according to the condition, if CF=0
Example: ( 1 )
CMP AX, 4371H
JAE RUN_PRESS
;Compare by subtracting 4371H from AX

;Jump to label RUN_PRESS if AX above or equal to 4371H
Example ( 2 )
CMP AX, 4371H
JNB RUN_PRESS
;Jump to label RUN_PRESS if AX not below to 4371H
CMP AX, 4371H

JNC RUN_PRESS
;Jump to label RUN_PRESS if CF=0
Example (3)
JB/JC/JNAE Instruction - Jump if below/Jump if carry/

Jump if not above nor equal
This instruction performs the Jump if below (or) Jump if carry (or) Jump if not above/ equal
operations according to the condition,
if CF = 1
Example:
1. CMP AX, 4371H ;Compare ( AX 4371H )
JB RUN_P
;Jump to label RUN_P if AX is below 4371H
2. ADD BX, CX
;Add two words and Jump to
JC ERROR
; label ERROR if CF = 1
JBE/JNA Instructions - Jump if below or equal
Jump if not above
This instruction performs the Jump if below or equal (or) Jump if not above operations
according to the condition, if CF or ZF = 1
Example:
CMP AX, 4371H
JBE RUN
CMP AX, 4371H
JNA RUN_R
;Compare ( AX 4371H )
;Jump to label RUN if AX is below or equal to 4371H
;Compare ( AX 4371H )
;Jump to label RUN_R if AX is ;not above than 4371H
JE/JZ Instruction - Jump if equal/Jump if zero

This instruction performs the Jump if equal (or) Jump if zero operations according to the
condition if ZF = 1
Example: (1)
NXT: CMP BX, DX
JE DONE
SUB BX, AX
INC CX
JUMP NXT
DONE: MOV AX, CX
;Compare ( BX DX )
;Jump to DONE if BX = DX,
;Else subtract Ax
;Increment counter
;Check again
;Copy count to AX
Example: (2)
IN AL, 8FH
SUB AL, 30H
JZ STATR
;read data from port 8FH

;Subtract minimum value
; Jump to label if result of subtraction was 0
JG/JNLE Instruction - Jump if greater/Jump if not less than nor equal

This instruction performs the Jump if greater (or) Jump if not less than or equal operations
according to the condition if ZF =0 and SF = OF
Example:
CMP BL, 39H
JG NEXT1
CMP BL, 39H
JNLE NEXT2
;Compare by subtracting 39H from BL

;Jump to label if BL is more positive than 39H
;Jump to label if BL is not less than or equal 39H
JGE/JNL Instruction - Jump if greater than or equal/ Jump if not less than
This instruction performs the Jump if greater than or equal / Jump if not less than operation
according to the condition if SF = OF
Example:
CMP BL, 39H
JGE NEXT11
CMP BL, 39H
JNL NEXT22
; Compare by the subtracting 39H from BL

; Jump to label if BL is more positive than 39H or equal to 39H
; Compare by subtracting 39H from BL
; Jump to label if BL is not less than 39H
JL/JNGE Instruction - Jump if less than/Jump if not greater than or equal

This instruction performs the Jump if less than / Jump if not greater than or equal operation
according to the condition, if
SF OF
Example: (1)
CMP BL, 39H
JL AGAIN
;Jump to the label if BL is more negative than 39H
Example (2)
CMP BL, 39H
JNGE AGAIN1
;Compare by subtracting 39H ;from BL

; Jump to the label if BL is not more positive than 39H or not equal
to 39H
JLE/JNG Instruction - Jump if less than or equal/ Jump if not greater

This instruction performs the Jump if less than or equal / Jump if not greater operation
according to
the condition, if ZF=1 or SF OF
Example: (1)
CMP BL, 39h
; Compare by subtracting 39h from BL
;Jump to the label if BL is more negative than 39h or equal
JLE NXT1
to 39h
Example (2)
CMP BL, 39h
JNG AGAIN2
;Compare by subtracting 39h ;from BL

; Jump to the label if BL is not ;more positive than 39h
JNE/JNZ Instruction - Jump if not equal /Jump if not zero

This instruction performs the Jump if not equal / Jump if not zero operation according to the
condition, if ZF=0
Example: (1)
NXT:
IN AL, 0F8H
;Read data value from port
CMP AL, 72
;Compare ( AL 72 )
JNE NXT
;Jump to NXT if AL 72
Example (2)
IN AL, 0F9H
MOV BX, 2734H
NXT_1: ADD AX, 0002H
DEC BX
JNZ NXT_1
;Read next port when AL = 72

; Load BX as counter
;Add count factor to AX
;Decrement BX
;Repeat until BX = 0
JNO Instruction Jump if no overflow

This instruction performs the Jump if no overflow operation according to the condition, if OF=0
Example:
ADD AL, BL
JNO DONE
MOV AL, 00H
DONE: OUT 24H, AL
; Add signed bytes in AL and BL

;Process done if no overflow ;Else load error code in \AL
; Send result to display
JNP/JPO Instruction Jump if no parity/ Jump if parity odd

This instruction performs the Jump if no parity /Jump if parity odd operation according to the
condition, if PF=0
Example:
IN AL, 0F8H
;Read ASCII char from UART
OR AL, AL
;Set flags
JPO ERROR1 ;If even parity executed, if not ;send error message
JNS Instruction - Jump if not signed (Jump if positive)
This instruction performs the Jump if not signed (Jump if positive)
operation according to the condition, if SF=0
Example:
DEC AL
JNS REDO
;Decrement counter
; Jump to label REDO if counter has not decremented to FFH
JO Instruction - Jump if overflow

This instruction performs Jump if overflow operation according to the condition OF = 1
Example:
ADD AL, BL
;Add signed bits in AL and BL
JO ERROR
;Jump to label if overflow occur in addition
MOV SUM, AL ; else put the result in memory location named SUM
JPE/JP Instruction
This instruction performs the Jump if parity even / Jump if parity operation according to the
condition, if PF=1
Example:
IN AL, 0F8H
OR AL, AL
JPE ERROR2
;Read ASCII char from UART

;Set flags
;odd parity is expected, if not ;send error message
JS Instruction
This instruction performs the Jump if sign operation according to the condition, if SF=1
Example:
ADD BL, DH ;Add signed bytes DH to BL
JS TOO_COLD ;Jump to label if result is negative
Process Control Instructions:
1. FLAG SET / CLEAR INSTRUCTIONS:
(STC, CLC, CMC, STD, CLD, STI,CLI)
There are three instructions that control the contents of carry flag. They are 1. STC, 2.CLC, and
3. CMC.
STC Instruction - Set the carry flag to 1
This instruction Sets Carry flag. STC does not
affect any other flags except CF
After execution of this instruction CF = 1
CLC Instruction - Clear the carry flag
CLC instruction clears the carry flag ( CF ) to 0. This instruction has no affect on the processor,
registers, or other flags.
It is often used to clear the CF before returning from a procedure to indicate a successful
termination.
It is also used to clear the CF during rotate operation involving the CF such as ADC, RCL, RCR
.
Example:
CLC
;Clear carry flag.
This instruction resets the Carry flag to 0.
It will not affect any other flags After execution of this instruction
CF = 0
CMC Instruction - Complement the carry flag
Complement Carry flag. Inverts value of CF.
If the carry flag CF is a zero before this instruction, it will be set to a one after the instruction.
If the carry flag is one before this instruction, it will be reset to a zero after the instruction
executes.
CMC has no effect on other flags.
Example:
CMC
;Invert the carry flag.
Algorithm: if CF = 1
then CF =0 & if CF
= 0 then CF = 1
STD Instruction - Set the direction flag to 1
STD is used to set the direction flag to a 1 so that SI and DI will automatically be decremented
to point to the next string element when one of the string instructions is executed.
If Direction flag is set ,SI and DI will be decremented by 1 for byte strings , and by 2 for word
strings
STD affects no other flags.
After execution of this instruction DF = 1
Example :
STD ; Set direction flag so that string pointers auto decrement
CLD Instruction - This instruction reset the direction flag to zero.
This instruction has no effect on the registers or other flags.
When the direction flag is cleared /reset, SI and DI will automatically be incremented when
one of the string instruction such as MOVS, CMPS, SCAS, MOVSB and STOSB executes.
After execution of this instruction
DF=0
Example :
CLD
;Clear direction flag so that string
pointers auto increment
STI Instruction - Set interrupt flag ( IF)
Setting the interrupt flag to a 1 enables the INTR interrupt input of 8086.
The instruction will not take effect until after the next instruction of STI.
When INTR input is enabled, an interrupt signal on this input will then cause the 8086 to
interrupt program execution, push the return address and flags on to the stack, and execute
an interrupt service procedure.
An IRET at the end of the interrupt service procedure, will restore the flags which were pushed
onto the stack, and return execution to the interrupted program.
STI does not affect any other flags
IF = 1
CLI Instruction - Clear interrupt flag
This instruction resets the interrupt flag to zero.
No other flags are affected.
If the interrupt flag is reset , the 8086 will not respond to an interrupt signal on its INTR input.
This instruction disables hardware interrupts
This CLI instruction has no effect on the Non maskable interrupt input, NMI
IF = 0
2. EXTERNAL HARDWARE SYNCHRONIZATION INSTRUCTIONS:

HLT
WAIT
ESC
LOCK
NOP
HLT Instruction - HALT processing

The HLT instruction will cause the 8086 to stop fetching and executing instructions.
The 8086 will enter into a halt state.
The only way to get the processor out of the halt state are with an interrupt signal on the
INTR pin or an interrupt signal on NMI pin or a reset signal on the RESET input
Example: MOV AX, 5

HLT
WAIT Instruction - Wait for test signal or interrupt signal
When this WAIT instruction executes, the 8086 enters an idle condition.
This will stay in this state until a signal is asserted on TEST input pin or a valid interrupt signal is
received on the INTR or NMI pin.
Example:
FSTSW STATUS
;copy 8087 status word to memory
FWAIT
;wait for 8087 to finish before- doing next 8086 instruction
MOV AX,STATUS
;copy status word to AX to check bits
In this code we are adding up of FWAIT instruction so that it will stop the execution of the
command until the above instruction finishes its work. so that you are not loosing data and
after that you will allow to continue the execution of instructions.
ESC Instruction
Escape instruction is used to pass instruction to a coprocessor such as the 8087 math
coprocessor which shares the address and data bus with an 8086.
Instructions for the coprocessor are represented by a
6 bit code embedded in the escape instruction. As the 8086 fetches instruction byte, the
coprocessor also catches these bytes from data bus and puts them in its queue.
The coprocessor treats all of the 8086 instruction as an NOP.
When 8086 fetches an ESC instruction , the coprocessor decodes the instruction and carries
out the action specified by the 6 bit code.
In most of the cases 8086 treats ESC instruction as an
NOP.
LOCK Instruction - Assert bus lock signal
Many microcomputer systems contain several microprocessors. Each microprocessor has its
own local buses and memory.
Individual microprocessors are connected together by a system bus so that each can have
access to system resources.
The LOCK prefix allows a microprocessor to make sure that another processor does not take
control of the system bus while it is in the middle of a critical instruction which uses the system
bus.
The LOCK prefix is put in front of the critical instruction.
When LOCK prefix is executed, 8086 will assert its bus lock signal output.
This signal is connected to an external bus controller device, which prevents any other
processor taking over the system bus.
Lock affect no flags
NOP Instruction - Performs no operation.
This instruction simply uses up the three clock cycles and increments the instruction pointer to
point to the next instruction.
NOP does not change the status of any flag.
The NOP instruction is used to increase the delay of a delay loop.
GENERAL DEFINITIONS
A Computer is a programmable machine.
The two principal characteristics of a computer are:
It responds to a specific set of instructions in a well defined manner.
It can execute a prerecorded list of instructions (aprogram ).
Modern computers are electronic and digital .
The actual machinery wires, transistors, and circuits is called hardware. the instructions and
data are called software.
All general-purpose computers require the following hardware components:

Memory: Enables a computer to store, at least temporarily, data and programs.
Mass storage device :Allows a computer to permanently retain large amounts of data.
Common mass storage devices include disk drives and tape drives.
Input device: Usually a keyboard and mouse are the input device through which data and
instructions enter a computer.
Output device: A display screen, printer, or other device that lets you see what the computer
has accomplished.
Central processing unit (CPU): The heart of the computer, this is the component that actually
executes instructions.
In addition to these components, many others make it possible for the basic components to
work together efficiently.
For example, every computer requires a bus that transmits data from one part of the computer
to another.
Computers can be generally classified by size and power as follows, though there is
considerable overlap:
Personal computer: A small, single-user computer based on a microprocessor.
In addition to the microprocessor, a personal computer has a keyboard for entering data, a
monitor for displaying information, and a storage device for saving data.
Workstation : A powerful, single-user computer.
A workstation is like a personal computer, but it has a more powerful microprocessor and a
higherquality monitor.
Minicomputer : A multi-user computer capable of supporting from 10 to hundreds of users

simultaneously.
Mainframe : A powerful multi-user computer capable of supporting many hundreds or
thousands of users simultaneously.
Supercomputer : An extremely fast computer that can perform hundreds of millions of
instructions per second.
Minicomputer:
A midsized computer. In size and power, minicomputers lie between workstations and
mainframes .
A minicomputer, a term no longer much used, is a computer of a size intermediate between a
microcomputer and a mainframe.
Typically, minicomputers have been stand-alone computers (computer systems with attached
terminals and other devices) sold to small and midsize businesses for general business
applications and to large enterprises for department-level operations.
In recent years, the minicomputer has evolved into the "mid-range server" and is part of a
network. IBM's AS/400e is a good example.
The AS/400 - formally renamed the "IBM iSeries," but still commonly known as AS/400 - is a
midrange server designed for small businesses and departments in large enterprises have now
redesigned so that it will work well in distributed networks with Web applications.
Workstation:
1) A type of computer used for engineering applications (CAD/CAM), desktop publishing,
software development, and other types of applications that require a moderate amount of
computing power and relatively high quality graphics capabilities.
Workstations generally come with a large, high resolution graphics screen, at least 64 MB of
RAM, built-in network support, and a graphical user interface
Most workstations also have a mass storage device such as a disk drive, but a special type of
workstation, called a diskless workstation, comes without a disk drive.
The most common operating systems for workstations are UNIX and Windows NT.
In terms of computing power, workstations lie between personal computers and minicomputers,
although the line is fuzzy on both ends.
High-end personal computers are equivalent to low-end workstations.
And high-end workstations are equivalent to minicomputers.
Like personal computers, most workstations are single user computers.
However, workstations are typically linked together to form a local-area network, although they
can also be used as standalone systems.
In networking, workstation refers to any computer connected to a local-area network. It could be
a workstation or a personal computer.
Mainframe:
A very large and expensive computer capable of supporting hundreds, or even
thousands, of users simultaneously.
In the hierarchy that starts with a simple microprocessor (in watches, for example) at the bottom
and moves to supercomputer at the top, mainframes are just below supercomputers.
In some ways, mainframes are more powerful than supercomputers because they support more
simultaneous programs.
But supercomputers can execute a single program faster than a mainframe.
The distinction between small mainframes and minicomputers is vague, depending really on
how the manufacturer wants to market its machines.
Microcomputer: The term microcomputer is generally synonymous with personal computer, or
a computer that depends on a microprocessor.
Microcomputers are designed to be used by individuals, whether in the form of PCs,
workstations or notebook computers.
A microcomputer contains a CPU on a microchip (the microprocessor), a memory system

(typically ROM and RAM), a bus system and I/O ports, typically housed in a motherboard.
Microprocessor: A silicon chip that contains a CPU. In the world of personal computers, the
terms microprocessor and CPU are used interchangeably.
A microprocessor (sometimes abbreviated P) is a digital electronic component with
miniaturized transistors on a single semiconductor integrated circuit (IC).
One or more microprocessors typically serve as a central processing unit (CPU) in a computer
system or handheld device.
Microprocessors made possible the advent of the microcomputer.
At the heart of all personal computers and most working stations sits a microprocessor.
Microprocessors also control the logic of almost all digital devices, from clock radios to fuelinjection systems for automobiles.
Three basic characteristics differentiate microprocessors:
Instruction set: The set of instructions that the microprocessor can execute.
Bus width : The number of bits processed in a single instruction.
Clock speed : Given in megahertz (MHz), the clock speed determines how many instructions
per second the processor can execute.
In both cases, the higher the value, the more powerful the CPU. For example, a 32 bit
microprocessor that runs at 50MHz is more powerful than a 16-bit microprocessor that runs at
50MHz.
In addition to bus width and clock speed, microprocessors are classified as being either RISC
(reduced instruction set computer) or CISC (complex instruction set computer).
Supercomputer: A supercomputer is a computer that performs at or near the currently highest
operational rate for computers.
A supercomputer is typically used for scientific and engineering applications that must handle
very large databases or do a great amount of computation (or both).
At any given time, there are usually a few well-publicized supercomputers that operate at the
very latest and always incredible speeds.
The term is also sometimes applied to far slower (but still impressively fast) computers.
Most supercomputers are really multiple computers that perform parallel processing.
In general, there are two parallel processing approaches:
symmetric multiprocessing (SMP) and massively parallel processing (MPP).
Development of microprocessors (Visible)Microprocessors have undergone significant
evolution over the past four decades. This development is clearly perceptible to a common
user, especially, in terms of phenomenal growth in capabilities of personal computers.
Development of some of the microprocessors can be given as follows.
"We always overestimate the change that will occur in the next two years and underestimate the
change that will occur in the next ten.
In November, 1971, 40 years ago, Intel placed an ad in Electronic News introducing the 4004,
the first microprocessor.
"A micro-programmable computer on a chip!" the headline shouted. None of the engineers
believed the hype.
Intel's best effort at the time had resulted in the 1103 DRAM, which stored just 1 kilobit of data.
The leap to a computer on a chip seemed impossible.
And so it turned out, as the 4004 needed a variety of extra components before it could actually
do anything.
But the 4004 heralded a new day in both computers and electronics.
The 4004's legacy wasn't that of a single-chip computer. That came within a few years.
Rather, it gave birth to the age of ubiquitous and cheap computing.
Yes, the era of the personal computer came a decade later and entirely as a result of the
microprocessor, but the 4004 immediately ushered in the age of embedded systems.
In the decade between the micro's invention and the first IBM PC, thousands, perhaps millions,
of products hit the market with embedded intelligence.
Forty years ago few people had actually seen a computer; today, almost every person is using
more than one computer.
Embedded Systems Design magazine and the entire embedded systems industry that employs
so many of us couldn't exist without the microprocessor.
In the four decades since its birth, everything we know about electronics has changed. And so,
for this, let us look back at the story of this astonishing invention.
The history of the micro is really the story of electronics, which is the use of active elements
(such as transistors, tubes, diodes) to transform signals.
And the microcomputer is all about using massive quantities of active elements.
But electrical deviceseven radios and TVexisted long before electronics
November marks the 40th anniversary of the microprocessor, the circuit element that truly
revolutionized the world and gave birth to the field of embedded systems.
John Mauchly and J. Presper Eckert were building the ENIAC, a general-purpose monster of a
machine containing nearly 18,000 vacuum tubes during 1947. It weighed 30 tons and
consumed 150 KW of electricity, and had five million hand-soldered joints. ENIAC's purpose
was to compute artillery firing tables, which it accelerated by three orders of magnitude over
other contemporary approaches.
ENIAC long held the title of the first programmable electronic computer.
It, too, used patch panels rather than a stored program, although later improvements gave it a
ROM-like store.
One source complained it could take "as long as three weeks to reprogram and debug a
program.
We all know how in 1947 Shockley, Bardeen, and Brattain invented the transistor, ushering in
the age of semiconductors.
But that common knowledge is wrong. Julius Lilienfeld patented devices that resembled fieldeffect transistors (although they were based on metals rather than modern semiconductors) in
the 1920s and 30s (he also patented the electrolytic capacitor). Indeed, the United States
Patent and Trademark Office rejected early patent applications from the Bell Labs boys, citing
Lilienfeld's work as prior art.
IBM's first transistorized computer was the 7070, introduced in 1958.
This was the beginning of the company's important 7000 series, which dominated mainframes
for a time.
A variety of models were sold, with the 7094 for a time occupying the "fastest computer in the
world" node.
The 7094 used over 50,000 transistors.
Operators would use another, smaller, computer to load a magnetic tape with many programs
from punched cards, and then mount the tape on the 7094.
The largest 7000-series machine was the 7030 "Stretch," a $100 million supercomputer that
wasn't super enough.
It missed its performance goals by a factor of three, and was soon withdrawn from production.
Only nine were built.
The machine had a staggering 169,000 transistors on 22,000 individual printed circuit boards.
Just think of the cost and complexity of the Stretch. Can you imagine wiring up 169,000
transistors.
Thankfully Jack Kilby and Robert Noyce independently invented the IC in 1958/9.
The IC was so superior to individual transistors that soon they formed the basis of most
commercial computers.
the ICs in the Apollo computer were identical: 2,800 dual three-input NOR gates, using three
transistors per gate. But the schematics show two kinds of NOR gates, "regular" versions and
"expander" gates.
The market for computers remained relatively small till the PDP-8 brought prices to a more
reasonable level.
By the late 1960s everyone was building computers.
The PDP-11 debuted in 1970 for about $11k with 4k words of core memory.
Before the microprocessor, it was absurd to consider adding a computer to a product;
Now, in general, only the quirky build anything electronic without embedded intelligence
Everyone knows how Intel invented the computer on a chip in 1971, introducing the 4004 in an
ad in a November issue of Electronic News. But everyone might be wrong.
It was a four-bit machine packing 2,300 transistors into a 16-pin package
Why 16 pins? Because that was the only package Intel could produce at the time. Today
fabrication folk are wrestling with the 22-nanometer process node.
The 4004 used 10,000-nm geometry. The chip itself cost about $1,100 in today's dollars, or
about half a buck per transistor.
CompUSA currently lists some netbooks for about $200, or around 10 microcents per transistor.
And that's ignoring the keyboard, display, 250-GB hard disk, and all the other components and
software that go with the netbook.
In parallel with the 4004's development, Intel was working with Datapoint on a computer, and in
early 1970, Ted Hoff and Stanley Mazor started work on what would become the 8008
processor.
In April, 1972, just months after releasing the 4004, Intel announced the 8008.
It had 3,500 transistors and cost $650.
This 18-pin part was also constrained by the packages the company knew how to build, so it
multiplexed data and addresses over the same connections.
By the mid-70s the history of the microprocessor becomes a mad jumble of product
introductions by dozens of companies. A couple are especially notable.
Intel's 8080 was a greatly improved version of the 8008
The 8080 required three different power supplies (+5, -5 and +12) as well as a two-phase clock.
A startup named Zilog improved the 8080's instruction set considerably and went to a singlesupply, single-clock design.
Their Z80 hugely simplified the circuits needed to support a microprocessor and was used in a
stunning number of embedded systems as well as personal machines, like Radio Shack's TRS80.
some micros today contain 3 billion transistors on a single die; memory parts are even denser.
And on the low end, a simple 8-bitter costs tens of cents, not bad compared with the millions of
dollars needed for a machine just a few decades ago.
But how often do we stand back and think about the implications of this change?
Active elements have shrunk in length by about a factor of a million, but an IC is a twodimensional structure so the effective shrink is more like a trillion.
The cost per GFLOP has fallen by a factor of about 10 billion since 1945.
It's claimed the iPad 2 has about the compute capability of the Cray 2, 1985's leading
supercomputer.
The Cray cost $35 million more than the iPad.
Apple's product runs 10 hours on a charge; the Cray needed
150 KW and liquid Flourinert cooling
The best guess pegs an iPhone at 100 billion transistors.
If we built one using the ENIAC's active element technology, the phone would be about the size
of 170 Vertical Assembly Buildings
Without the microprocessor there would be no Google. No Amazon. No Wikipedia, no web,
even. No smart thermostats, no remote controls, no HDTV.
Instead of an iPad, you'd have a pad of paper. CAT scans, MRIs, PET scanners, and most of
modern medicine wouldn't exist.
Intel 4004
4 bit (2300 PMOS transistors)
1971
Intel 8080
8 bit (NMOS)
1974
8085
8 bit
Intel 8088
16 bit
8086
16 bit
1978
Intel 80186
16 bit
80286
16 bit
1982
Intel 80386
32 bit (275000 transistors)
1985
Intel 80486 SX
32 bit
1989
Intel 80586
DX
32 bit (built in floating point unit)
64 bit
1993
MMX
1997
Celeron II
1999
III
IV
2000
Z-80 (Zilog)
Motorola Power PC 601
602
603
8 bit
1976
32-bit
1993
1995
Microcontroller: A highly integrated chip that contains all the components comprising a controller.
Typically this includes a CPU, RAM, some form of ROM, I/O ports, and timers.
Unlike a general-purpose computer, which also includes all of these components, a

microcontroller is designed for a very specific task - to control a particular system.
A microcontroller differs from a microprocessor, which is a general-purpose chip that is used to

create a multifunction computer or device and requires multiple chips to handle various tasks.
A microcontroller is meant to be more selfcontained and independent, and functions as a tiny,

dedicated computer.
The great advantage of microcontrollers, as opposed to using larger microprocessors, is that the
parts-count and design costs of the item being controlled can be kept to a minimum.
They are typically designed using CMOS (complementary metal oxide semiconductor)
technology, an efficient fabrication technique that uses less power and is more immune to
power spikes than other techniques.
Controller: A device that controls the transfer of data from a computer to a peripheral device
and vice versa.
For example, disk drives, display screens, keyboards and printers all require controllers.
In personal computers, the controllers are often single chips.
When you purchase a computer, it comes with all the necessary controllers for standard
components, such as the display screen, keyboard, and disk drives
If you attach additional devices, however, you may need to insert new controllers that come on
expansion boards.
Controllers must be designed to communicate with the computer's expansion bus.
There are three standard bus architectures for PCs - the AT bus, PCI (Peripheral Component
Interconnect ) and SCSI.
When you purchase a controller, therefore, you must ensure that it conforms to the bus
architecture that your computer uses Embedded system: A specialized computer system that
is part of a larger system or machine.
Typically, an embedded system is housed on a single microprocessor board with the programs
stored in ROM.
Virtually all appliances that have a digital Interface watches, microwaves, VCRs, cars utilize
embedded systems.
Some embedded systems include an operating system, but many are so specialized that the
entire logic can be implemented as a single program.
8086 Microprocessor
It is a 16-bit P.
8086 has a 20 bit address bus can access up to 2**20 memory locations (1 MB).
It can support up to 64K I/O ports.
It is having FOURTEEN, 16 -bit registers.
It has multiplexed address and data bus AD0AD15 and A16 A19.
It requires single phase clock with 33% duty cycle to provide internal timing.
8086 is designed to operate in two modes, Minimum and Maximum.
It can pre-fetches upto 6 instruction bytes from memory and queues them up in order to speed
up instruction execution.
It requires +5V power supply.
A 40 pin dual in line package Minimum and Maximum Modes The minimum mode is selected
by applying logic 1 to the MN / MX Bar input pin.
This is a single microprocessor configuration.
The maximum mode is selected by applying logic 0 to the MN / MX Bar input pin. This is a multi
micro processors configuration
Internal Architecture of 8086
Internal Architecture of 8086 8086 has two

blocks BIU and EU.
The BIU performs all bus operations such as instruction fetching, reading and writing operands
for memory and calculating the addresses of the memory operands. The instruction bytes are
transferred to the instruction queue.
EU executes instructions from the instruction system byte queue.
Both units operate asynchronously to give the 8086 an overlapping instruction fetch and
execution mechanism which is called as Pipelining. This results in efficient use of the system
bus and system performance.
BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder.
EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register.
Minimum and Maximum Modes
It provides a full 16 bit bidirectional data bus and 20 bit address bus.
The bus interface unit is responsible for performing all external bus operations.
Specifically it has the following functions:
Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus
control.
The BIU uses a mechanism known as an instruction stream queue to implement a pipeline
architecture.
This queue permits prefetch of up to six bytes of instruction code. When ever the queue of the
BIU is not full, it has room for at least two more bytes and at the same time the EU is not
requesting it to read or write operands from memory, the BIU is free to look ahead in the
program by prefetching the next sequential instruction.
These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU
fetches two instruction bytes in a single memory cycle.
After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO
to the empty location nearest the output.
The EU accesses the queue from the output end. It reads one instruction byte after the other
from the output of the queue. If the queue is full and the EU is not requesting access to
operand in memory.
These intervals of no bus activity, which may occur between bus cycles are known as Idle state
If the BIU is already in the process of fetching an instruction when the EU request it to read or
write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle
before initiating the operand read / write cycle.
The BIU also contains a dedicated adder which is used to generate the 20bit physical address
that is output on the address bus. This address is formed by adding an appended 16 bit
segment address and a 16 bit offset address.
For example: The physical address of the next instruction to be fetched is formed by combining
the current contents of the code segment CS register and the current contents of the instruction
pointer IP register.
The BIU is also responsible for generating bus control signals such as those for memory read or
write and I/O read or write.
EXECUTION UNIT
The Execution unit is responsible for decoding and executing all instructions.
The EU extracts instructions from the top of the queue in the BIU, decodes them, generates
operands if necessary, passes them to the BIU and requests it to perform the read or write bus
cycles to memory or I/O and perform the operation specified by the instruction on the operands.
During the execution of the instruction, the EU tests the status and control flags and updates
them based on the results of executing the instruction.
If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top
of the queue.
When the EU executes a branch or jump
instruction, it transfers control to a location corresponding to another set of sequential
instructions.
Whenever this happens, the BIU automatically resets the queue and then begins to fetch
instructions from this new location to refill the queue.
Signal Description of 8086
The Microprocessor 8086 is a 16-bit CPU available in different clock rates and packaged in a 40
pin CERDIP or plastic package.
The 8086 operates in single processor or multiprocessor configuration to achieve high

performance. The pins serve a particular function in minimum mode (single processor mode)
and other function in maximum mode configuration (multiprocessor mode ).
The 8086 signals can be categorized in three groups. The first are the signal having common
functions in minimum as well as maximum mode.
The second are the signals which have special functions for minimum mode and third are the
signals having special functions for maximum mode.
The following signal descriptions are common for both modes:

AD15-AD0: These are the time multiplexed memory I/O address and data lines.
Address remains on the lines during T1 state, while the data is available on the data bus during
T2, T3, Tw and T4.
These lines are active high and float to a tri-state during interrupt acknowledge and local bus
hold acknowledge cycles.
A19/S6,A18/S5,A17/S4,A16/S3: These are the time multiplexed address and status lines.
During T1 these are the most significant address lines for memory operations.
During I/O operations, these lines are low. During memory or I/O operations, status information
is available on those lines for T2,T3,Tw and T4.
S5 indicates the condition of IF flag bit.The status of the interrupt enable flag bit is updated at
the beginning of each clock cycle.
The S4 and S3 combinedly indicate which segment register is presently being used for memory
accesses as in below fig.
These lines float to tri-state during the local bus hold acknowledge. The status line S6 is always
low.
The address bits are separated from the status bit using latches controlled by the ALE signal.
BHE/S7: The bus high enable is used to indicate the transfer of data over the higher order
( D15-D8 ) data bus as shown in table. It goes low for the data transfer over D15-D8 and is
used to derive chip selects of odd address memory bank or peripherals. BHE is low during T1
for read, write and interrupt acknowledge cycles, whenever a byte is to be transferred on higher
byte of data bus. The status information is available during T2, T3 and T4. The signal is active
low and tristated during hold. It is low during T1 for the first pulse of the interrupt acknowledges
cycle.
RD Read: This signal on low indicates the peripheral that the processor is performing memory
or I/O read operation. RD is active low and shows the state for T2, T3, Tw of any read cycle.
The signal remains tristated during the hold acknowledge.
READY: This is the acknowledgement from the slow device or memory that they have
completed the data transfer. The signal made available by the devices is synchronized by the
8284A clock generator to provide ready input to the 8086. the signal is active high.
INTR-Interrupt Request: This is a triggered input. This is sampled during the last clock cycles
of each instruction to determine the availability of the request. If any interrupt request is
pending, the processor enters the interrupt acknowledge cycle.
This can be internally masked by resulting the interrupt enable flag. This signal is active high
and internally synchronized.
TEST This input is examined by a WAIT instruction. If the TEST pin goes low, execution will
continue, else the processor remains in an idle state. The input is synchronized internally
during each clock cycle on leading edge of clock.
CLK- Clock Input: The clock input provides the basic timing for processor operation and bus
control activity. Its an asymmetric square wave with 33% duty cycle.
MN/MX: The logic level at this pin decides whether the processor is to operate in either
minimum or maximum mode.
The following pin functions are for the minimum mode operation of 8086.
M/IO Memory/IO: This is a status line logically equivalent to S2 in maximum mode. When it
is low, it indicates the CPU is having an I/O operation, and when it is high, it indicates that the
CPU is having a memory operation. This line becomes active high in the previous T4 and
remains active till final T4 of the current cycle. It is tristated during local bus hold acknowledge
.
INTA Interrupt Acknowledge: This signal is used as a read strobe for interrupt acknowledge
cycles. i.e. when it goes low, the processor has accepted the interrupt.
ALE Address Latch Enable: This output signal indicates the availability of the valid address
on the address/data lines, and is connected to latch enable input of latches. This signal is
active high and is never tristated.
DT/R Data Transmit/Receive: This output is used to decide the direction of data flow
through the transreceivers (bidirectional buffers). When the processor sends out data, this
signal is high and when the processor is receiving data, this signal is low.
DEN Data Enable: This signal indicates the availability of valid data over the address/data
lines. It is used to enable the transreceivers ( bidirectional buffers ) to separate the data from
the multiplexed address/data signal. It is active from the middle of T2 until the middle of T4.
This is tristated during hold acknowledge cycle.
HOLD, HLDA- Acknowledge: When the

HOLD line goes high, it indicates to the processor that another master is requesting the bus
access.
The processor, after receiving the HOLD request, issues the hold acknowledge signal on HLDA
pin, in the middle of the next clock cycle after completing the current bus cycle.
At the same time, the processor floats the local bus and control lines. When the processor
detects the HOLD line low, it lowers the HLDA signal. HOLD is an asynchronous input, and it
should be externally synchronized.
If the DMA request is made while the CPU is performing a memory or I/O cycle, it will release
the local bus during T4 provided:
1.The request occurs on or before T2 state of the current cycle.
2.The current cycle is not operating over the lower byte of a word.
3.The current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A Lock instruction is not being executed.
The following pin function are applicable for maximum mode operation of :
S2, S1, S0 Status Lines: These are the status lines which reflect the type of operation, being
carried out by the processor. These become activity during T4 of the previous cycle and active
during T1 and T2 of the current bus cycles
LOCK This output pin indicates that other system bus master will be prevented from gaining
the system bus, while the LOCK signal is low.
The LOCK signal is activated by the LOCK prefix instruction and remains active until the
completion of the next instruction. When the CPU is executing a critical instruction which
requires the system bus, the LOCK prefix instruction ensures that other processors connected
in the system will not gain the control of the bus.
QS1, QS0 Queue Status: These lines give information about the status of the code-prefetch
queue. These are active during the CLK cycle after the queue operation is performed.
The 8086 architecture has 6-byte instruction prefetch queue. Thus even the largest (6-bytes)
instruction can be prefetched from the memory and stored in the queue. This results in a faster
execution of the instructions.
In 8085 an instruction is fetched, decoded and executed and only after the execution of this
instruction, the next one is fetched.
By prefetching the instruction, there is a considerable speeding up in instruction execution in
8086. This is known as instruction pipelining.
This modification in a simple fetch and execute architecture of a conventional microprocessor
offers an added advantage of pipelined processing of the instructions.
At the starting the CS:IP is loaded with the required address from which the execution is to be
started. Initially, the queue will be empty and the microprocessor starts a fetch operation to
bring one byte (the first byte) of instruction code, if the CS:IP address is odd or two bytes at a
time, if the CS:IP address is even.
The first byte is a complete opcode in case of some instruction (one byte opcode instruction)
and is a part of opcode, in case of some instructions ( two byte opcode instructions), the
remaining part of code lie in second byte.
The second byte is then decoded in continuation with the first byte to decide the instruction
length and the number of subsequent bytes to be treated as instruction data.
The queue is updated after every byte is read from the queue but the fetch cycle is initiated by
BIU only if at least two bytes of the queue are empty and the EU may be concurrently
executing the fetched instructions.
The next byte after the instruction is completed is again the first opcode byte of the next
instruction. A similar procedure is repeated till the complete execution of the program.
The fetch operation of the next instruction is overlapped with the execution of the current
instruction. As in the architecture, there are two separate units, namely Execution unit and Bus
interface unit.
While the execution unit is busy in executing an instruction, after it is completely decoded, the
bus interface unit may be fetching the bytes of the next instruction from memory, depending
upon the queue status.
RQ/0GT,RQ/1GT Request/Grant: These pins are used by the other local bus master in
maximum mode, to force the processor to release the local bus at the end of the processor
current bus cycle.
Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1.
The request and grant pulses are active low.
If the bus request received while 8086 is performing memory or I/O cycle, granting of the bus is
governed by the rules as in case of HOLD and HLDA in minimum mode.
General Bus Operation:
The 8086 has a combined address and data bus commonly referred as a time multiplexed
address and data bus.
The main reason behind multiplexing address and data over the same pins is the maximum
utilization of processor pins and it facilitates the use of 40 pin standard DIP package
The bus can be demultiplexed using a few latches and transreceivers, when ever required.
Basically, all the processor bus cycles consist of at least four clock cycles. These are referred to
as
T1, T2, T3, T4. The address is transmitted by the processor during T1. It is present on the bus
only for one cycle.
The negative edge of this ALE pulse is used to separate the address and the data or status
information. In maximum mode, the status lines S0, S1 and S2 are used to indicate the type of
operation.
Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal.
Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4.
General Bus Operation Cycle in Maximum Mode
Minimum Mode 8086 System

In this mode, all the control signals are given out by the microprocessor chip itself. There is a
single microprocessor in the minimum mode system.
The remaining components in the system are latches, transreceivers, clock generator, memory
and I/O devices. Some type of chip selection logic may be required for selecting memory or I/O
devices, depending upon the address map of the system.
Latches are generally buffered output D-type flipflops like 74LS373 or 8282. They are used for
separating the valid address from the multiplexed address/data signals and are controlled by
the ALE signal generated by 8086.
Transreceivers are the bidirectional buffers and some times they are called as data amplifiers.
They are required to separate the valid data from the time multiplexed address/data signals.
They are controlled by two signals namely, DEN and DT/R.
The DEN signal indicates the direction of data, i.e. from or to the processor. The system
contains memory for the monitor and users program storage.
Usually, EPROMs are used for monitor storage, while RAM is used program storage. A system
may contain I/O devices.
The working of the minimum mode configuration system can be better described in terms of the
timing diagrams rather than qualitatively describing the operations.
The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in
two parts, the first is the timing diagram for read cycle and the second is the timing diagram for
write cycle.
The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also M /
IO signal. During the negative going edge of this signal, the valid address is latched on the
local bus.
The BHE and A0 signals address low, high or both bytes. From T1 to T4 , the M/IO signal
indicates a memory or I/O operation.
At T2, the address is removed from the local bus and is sent to the output. The bus is then
tristated. The read (RD) control signal is also activated in T2.
The read (RD) signal causes the address device to enable its data bus drivers. After RD goes
low, the valid data is available on the data bus.
The addressed device will drive the READY line high. When the processor returns the read
signal to high level, the addressed device will again tristate its bus drivers.
A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO
signal is again asserted to indicate a memory or I/O operation. In T2, after sending the address
in T1, the processor sends the data to be written to the addressed location.
The data remains on the bus until middle of T4 state. The WR becomes active at the beginning
of T2 (unlike RD is somewhat delayed in T2 to provide time for floating).
The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to
be read or write.
The M/IO, RD and WR signals indicate the type of data transfer as specified in table below.
Write Cycle Timing Diagram for Minimum Mode
Hold Response sequence: The HOLD pin is checked at leading edge of each clock pulse. If it
is received active by the processor before T4 of the previous cycle or during T1 state of the
current cycle, the CPU activates HLDA in the next clock cycle and for succeeding bus cycles,
the bus will be given to another requesting master.
The control of the bus is not regained by the processor until the requesting master does not
drop the HOLD pin low. When the request is dropped by the requesting master, the HLDA is
dropped by the processor at the trailing edge of the next clock.
Bus Request and Bus Grant Timings in Minimum

Mode System
Maximum Mode 8086 System

In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.
In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus
controller derives the control signal using this status information.
In the maximum mode, there may be more than one microprocessor in the system
configuration.
The components in the system are same as in the minimum mode system.
The basic function of the bus controller chip IC8288, is to derive control signals like RD and WR
( for memory and I/O devices), DEN, DT/R, ALE etc. using the information by the processor
on the status lines.
The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are driven by
CPU.
It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and AIOWC. The
AEN, IOB and CEN pins are specially useful for multiprocessor systems.
AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance of the
MCE/PDEN output depends upon the status of the IOB pin.
If IOB is grounded, it acts as master cascade enable to control cascade 8259A, else it acts as
peripheral data enable used in the multiple bus configurations.
INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an
interrupting device.
IORC, IOWC are I/O read command and I/O write command signals respectively. These signals
enable an IO interface to read or write the data from or to the address port.
The MRDC, MWTC are memory read command and memory write command signals
respectively and may be used as memory read or write signals.
All these command signals instructs the memory to accept or send data from or to the bus.
For both of these write command signals, the advanced signals namely AIOWC and AMWTC
are available.
Here the only difference between in timing diagram between minimum mode and maximum
mode is the status signals used and the available control and advanced command signals.
S0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse to the
ALE and apply a required signal to its DT / R pin during T1.
In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate MRDC or
IORC. These signals are activated until T4. For an output, the AMWC or AIOWC is activated
from T2 to T4 and MWTC or IOWC is activated from T3 to T4.
The status bit S0 to S2 remains active until T3 and become passive during T3 and T4.
If reader input is not activated before T3, wait state will be inserted between T3 and T4.
Memory Read Timing in Maximum Mode
Memory Write Timing in Maximum mode
RQ/GT Timings in Maximum Mode
When a request is detected and if the condition for HOLD request are satisfied, the processor
issues a grant pulse over the RQ/GT pin immediately during T4 (current) or T1 (next) state.
When the requesting master receives this pulse, it accepts the control of the bus, it sends a
release pulse to the processor using RQ/GT pin.
Maximum Mode 8086 System
Minimum Mode Interface
When the Minimum mode operation is selected, the 8086 provides all control signals needed to
implement the memory and I/O interface.
The minimum mode signal can be divided into the following basic groups: address/data bus,
status, control, interrupt and DMA.
Address/Data Bus: these lines serve two functions. As an address bus is 20 bits long and
consists of signal lines A0 through A19. A19 represents the MSB and A0 LSB. A 20bit address
gives the 8086 a 1Mbyte memory address space. More over it has an independent I/O address
space which is 64K bytes in length.
The 16 data bus lines D0 through D15 are actually multiplexed with address lines A0 through
A15 respectively. By multiplexed we mean that the bus work as an address bus during first
machine cycle and as a data bus during next machine cycles. D15 is the MSB and D0 LSB.
When acting as a data bus, they carry read/write data for memory, input/output data for I/O
devices, and interrupt type codes from an interrupt controller.
Block Diagram of the Minimum Mode 8086 MPU
Status signal
The four most significant address lines A19 through A16 are also multiplexed but in this case
with status signals S6 through S3. These status bits are output on the bus at the same time that
data are transferred over the other bus lines.
Bit S4 and S3 together from a 2 bit binary code that identifies which of the 8086 internal segment
registers are used to generate the physical address that was output on the address bus during
the current bus cycle.
Code S4S3 = 00 identifies a register known as extra segment register as the source of the
segment address. Status line S5 reflects the status of another internal characteristic of the 8086.
It is the logic level of the interrupt enable flag. The last status bit S6 is always at the logic 0 level.
Status line S5 reflects the status of another internal characteristic of the 8086. It is the logic level
of the internal enable flag. The last status bit S6 is always at the logic 0 level
Memory segment status codes Control Signals:

The control signals are provided to support the 8086 memory I/O interfaces. They control
functions such as: when the bus is to carry a valid address, in which direction data are to be
transferred over the bus, when valid write data are on the bus and when to put read data on the
system bus.
ALE is a pulse to logic 1 that signals external circuitry when a valid address word is on the bus.
This address must be latched in external circuitry on the 1-to-0 edge of the pulse at ALE.
Another control signal that is produced during the bus cycle is BHE bank high enable. Logic 0 on
this is used as a memory enable signal for the most significant byte half of the data bus.
Using the M/IO and DT/R lines, the 8086 signals which type of bus cycle is in progress and in
which direction data are to be transferred over the bus.
The logic level of M/IO tells external circuitry whether a memory or I/O transfer is taking place
over the bus. Logic 1 at this output signals a memory operation and logic 0 an I/O operation.
The direction of data transfer over the bus is signaled by the logic level output at DT/R. When
this line is logic 1 during the data transfer part of a bus cycle, the bus is in the transmit mode.
Therefore, data are either written into memory or output to an I/O device.
On the other hand, logic 0 at DT/R signals that the bus is in the receive mode. This corresponds
to reading data from memory or input of data from an input port.
The signal read RD and write WR indicates that a read bus cycle or a write bus cycle is in
progress. The 8086 switches WR to logic 0 to signal external device that valid write or output
data are on the bus.
On the other hand, RD indicates that the 8086 is performing a read data from the bus. During
read
operations, one other control signal is also supplied. This is DEN ( data enable) and it signals
external devices when they should put data on the bus.
There is one other control signal that is involved with the memory and I/O interface. This is the
READY signal.
READY signal is used to insert wait states into the bus cycle such that it is extended by a
number of clock periods. This signal is provided by an external clock generator device and can
be supplied by the memory or I/O subsystem to signal the 8086 when they are ready to permit
the data transfer to be completed.
Interrupt signals: The key interrupt interface signals are interrupt request (INTR) and interrupt
acknowledge ( INTA).
INTR is an input to the 8086 that can be used by an external device to signal that it need to be
serviced.
Logic 1 at INTR represents an active interrupt request.
When an interrupt request has been recognized by the 8086, it indicates this fact to external
circuit with pulse to logic 0 at the INTA output.
The TEST input is also related to the external interrupt interface. Execution of a WAIT instruction
causes the 8086 to check the logic level at the TEST input.
If a logic 1 is found, the MPU suspend operation and goes into the idle state. The 8086 no longer
executes instructions, instead it repeatedly checks the logic level of the TEST input waiting for its
transition back to logic 0.
As TEST switches to 0, execution resume with the next instruction in the program. This feature
can be used to synchronize the operation of the 8086 to an event in external hardware.
There are two more inputs in the interrupt interface: the nonmaskable interrupt NMI and the
reset interrupt RESET.
On the 0-to-1 transition of NMI control is passed to a nonmaskable interrupt service routine. The
RESET input is used to provide a hardware reset for the 8086. Switching RESET to logic 0
initializes the internal register of the 8086 and initiates a reset service routine.
DMA Interface signals:The direct memory access DMA interface of the 8086 minimum mode
consist of the HOLD and HLDA signals.
When an external device wants to take control of the system bus, it signals to the 8086 by
switching HOLD to the logic 1 level. At the completion of the current bus cycle, the 8086 enters
the hold state. In the hold state, signal lines AD0 through AD15, A16/S3 through A19/S6, BHE,
M/IO, DT/R, RD, WR, DEN and INTR are all in the high Z state. The 8086 signals external device
that it is in this state by switching its HLDA output to logic 1 level.
Maximum Mode Interface
When the 8086 is set for the maximum-mode configuration, it provides signals for implementing
a Multiprocessor / Coprocessor system environment.
By multiprocessor environment we mean that more than one microprocessor exists in the
system and that each processor is executing its own program.
Usually in this type of system environment, there are some system resources that are common
to all processors.
They are called as global resources. There are also other resources that are assigned to
specific processors. These are known as local or private resources.
Coprocessor also means that there is a second processor in the system. In this two processor
does not access the bus at the same time.
One passes the control of the system bus to the other and then may suspend its operation.
In the maximum-mode 8086 system, facilities are provided for implementing allocation of global
resources and passing bus control to other microprocessor or coprocessor.
8086 Maximum mode Block Diagram
8288 Bus Controller Bus Command and Control Signals

8086 does not directly provide all the signals that are required to control the memory, I/O and
interrupt interfaces.
Specially the WR, M/IO, DT/R, DEN, ALE and INTA, signals are no longer produced by the
8086. Instead it outputs three status signals S0, S1, S2 prior to the initiation of each bus cycle.
This 3- bit bus status code identifies which type of bus cycle is to follow.
S2S1S0 are input to the external bus controller device, the bus controller generates the
appropriately timed command and control signals.
Bus Status Codes
The 8288 produces one or two of these eight command signals for each bus cycles. For
instance, when the 8086 outputs the code S2S1S0 equals 001, it indicates that an I/O read
cycle is to be performed.
If the code 111 is output by the 8086, it is signaling that no bus activity is to take place.
The control outputs produced by the 8288 are DEN, DT/R and ALE. These 3 signals provide the
same functions as those described for the minimum system mode. This set of bus commands
and control signals is compatible with the Multi-bus and industry standard for interfacing
microprocessor systems.
The output of 8288 are bus arbitration signals:
Bus busy (BUSY), common bus request (CBRQ), bus priority out (BPRO), bus priority in
(BPRN), bus request (BREQ) and bus clock (BCLK).
They correspond to the bus exchange signals of the Multi-bus and are used to lock other
processor off the system bus during the execution of an instruction by the 8086.
In this way the processor can be assured of uninterrupted access to common system resources
such as global memory.
Status Signals: Two new signals that are produced by the 8086 in the maximum-mode system
are queue status outputs QS0 and QS1. Together they form a 2-bit queue status code, QS1QS0.
Following table shows the four different queue status.
Queue status codes
Local Bus Control Signal Request / Grant Signals: In a maximum mode configuration, the
minimum mode HOLD, HLDA interface is also changed. These two are replaced by request/grant
lines RQ/ GT0 and RQ/ GT1, respectively. They provide a prioritized bus access mechanism for
accessing the local bus.
Internal Registers of 8086

The 8086 has four groups of the user accessible internal registers. They are the instruction
pointer, four data registers, four pointer and index register, four segment registers.
The 8086 has a total of fourteen 16-bit registers including a 16 bit register called the status
register, with 9 of bits implemented for status and control flags.
Most of the registers contain data/instruction offsets within 64 KB memory segment. There are
four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1
MB of processor memory these 4 segments are located in the processor uses four segment
registers:
Register names
Accumulator
Base
Count
Data
Stack Pointer
Base Pointer
Destination index
Source index
Instruction Pointer
Flags
Segment registers
Code
Data
Extra
Stack
Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor
instructions. The processor uses CS segment for all accesses to instructions referenced by
instruction pointer (IP) register. CS register cannot be changed directly. The CS register is
automatically updated during far jump, far call and far return instructions.
Stack segment (SS) is a 16-bit register containing address of 64KB segment with program
stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and
base pointer (BP) registers is located in the stack segment. SS register can be changed directly
using POP instruction.
Data segment (DS) is a 16-bit register containing address of 64KB segment with program data.
By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX)
and index register (SI, DI) is located in the data segment. DS register can be changed directly
using POP and LDS instructions.
Accumulator register consists of two 8-bit registers AL and AH, which can be combined together
and used as a 16-bit register AX. AL in this case contains the low-order byte of the word, and AH
contains the high-order byte. Accumulator can be used for I/O operations and string
manipulation.
Base register consists of two 8-bit registers BL and BH, which can be combined together and
used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH
contains the high-order byte. BX register usually contains a data pointer in based, based indexed
or register indirect addressing.
Count register consists of two 8-bit registers CL and CH, which can be combined together and
used as a 16-bit register CX. When combined, CL register contains the low-order byte of the
word, and CH contains the highorder byte. Count register can be used in Loop, shift/rotate
instructions and as a counter in string manipulation,.
Data register consists of two 8-bit registers DL and DH, which can be combined together and
used as a 16-bit register DX. When combined, DL register contains the low-order byte of the
word, and DH contains the high-order byte. Data register can be used as a port number in I/O
operations. In integer 32-bit multiply and divide instruction the DX register contains highorder
word of the initial or resulting number.
The following registers are both general and index register
Stack Pointer (SP) is a 16-bit register pointing to program stack.

Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually
used for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect
addressing, as well as a source data address in string manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register
indirect addressing, as well as a destination data address in string manipulation instructions.
Other registers
Instruction Pointer (IP) is a 16-bit register.
Flags Register is a 16-bit register containing 9 one bit flags.

Overflow Flag (OF) - set if the result is too large positive number, or is too small negative
number to fit into destination operand.
Direction Flag (DF) - if set then string manipulation instructions will auto-decrement index
registers. If cleared then the index registers will be auto-incremented.
Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.
Single-step Flag (TF) - if set then single-step interrupt will occur after the next instruction
Sign Flag (SF) - set if the most significant bit of the result to Zero.
Zero Flag (ZF) - set if the result is zero.
Auxiliary carry Flag (AF) - set if there was a carry to or borrow from bits 3-4 in the AL register.
Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is even.
Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit during last
result calculation.
80X86 Addressing Modes
1. Register
2. Immediate
3. Direct
4. Register indirect
5. Based relative
6. Indexed relative
7. Based indexed relative
Register Addressing Mode:
Registers are used to hold the data
Memory is not accessed (hence is fast)
Source and destination registers must match in size

Exp:
MOV BX,DX
MOV ES,AX
ADD AL,BH
MOV CL,AX(error)
Immediate Addressing Mode:
The source operand is a constant
can be used to load information to any registers except the segment registers and flag registers
(can be done indirectly)
operands come immediately after the opcode

EXP:
MOV AX,2550H MOV CX,625
MOV BL,40H
How about MOV DS, 0123H?
Program Segments
Code segment
Data segment
Stack segment
Why segment?
Q.How many address pins in 8086 chip?
Q.In 8085, only 16 pins for address lines. Whats the size of physical memory can be pointed to in one
instruction?
Q.What is the size of the physical memory 8086 can handle?
Q.How does 8086 handle the physical memory using the extra pins it is given?
Logical Address, Offset address & Physical address
Direct Addressing Mode

The data is in memory
The address of the operand is provided in the instruction directly
The address is the offset address
The physical address can be calculated using the content in the DS register
Exp1: MOV DL,[2400]
Exp2: MOV AL,99H
MOV [3518],AL
Register Indirect Addressing Mode

instruction specifies a register containing an address, where data is located. This addressing mode
works with SI, DI, BX and BP registers.
The address of the memory location is in a register (SI, DI, BX, or BP only)
The physical address is calculated using the content of DS
EXP: MOV CL,[SI] MOV
[DI],AH
MOV [SI],AX ;
Based Relative Addressing Mode

8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP), the resulting
value is a pointer to location where data resides
effective address: [BX]+disp, or [BP]+disp
The physical address is calculated using DS for
[BX]+disp, and SS for [BP]+disp
Exp: MOV CX,[BX]+10
MOV AL,[BP]+5
Index Relative Addressing Mode
8-bit or 16-bit instruction operand is added to the contents of an index register (SI or DI), the
resulting value is a pointer to location where data resides
Similar to the based relative addressing mode
DI and SI are used to hold the offset address
DS is used for calculating physical address

EXP: MOV DX,[SI]+5
MOV CL,[DI]+20
Based Indexed Addressing Mode
the contents of a base register (BX or BP) is added to the contents of an index register (SI or
DI), the resulting value is a pointer to location where data resides
Combining the previous two modes
One base register and one index register are used
for physical address calculation, DS is used for BX; SS is used for BP
EXP: MOV CL,[BX][DI]
MOV AH,[BP][SI]
Based indexed relative
8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP) and
index register (SI or DI), the resulting value is a pointer to location where data resides.
EXP: MOV CL,[BX][DI]+8
MOV AH,[BP][SI]+29
(Scale*Index) + Displacement (Scaled Index)
[ Scale * Index + Displacement]
Product of Index Register and a constant scaling factor (2, 4 or 8) added to specified
Displacement to give offset.
EXP: MOV EAX, [4 * ECX + 4]
MOV List[2 * EBX],CX
MOV List[2 * EBX+32],DX
MOV AX, [2 * EDI+Age]
Only Pentium Supports efficient access to array elements when the element size is 2, 4 or 8
bytes,
e.g. Displacement = offset to beginning of array.
Index Register = position of desired element,
Scale = element size in bytes
Memory
Program, data and stack memories occupy the same memory space. As the most of the processor
instructions use 16-bit pointers the processor can effectively address only 64 KB of memory.
To access memory outside of 64 KB the CPU uses special segment registers to specify where
the code, stack and data 64 KB segments are positioned within 1 MB of memory.
16-bit pointers and data are stored as: address: low-order byte address+1: highorder byte
Program memory - program can be located anywhere in memory. Jump and call instructions can
be used for short jumps within currently selected 64 KB code segment, as well as for far jumps
anywhere within 1 MB of memory.
All conditional jump instructions can be used to jump within approximately +127 to -127 bytes
from current instruction.
Data memory - the processor can access data in any one out of 4 available segments, which limits
the size of accessible memory to 256 KB (if all four segments point to different 64 KB blocks).
Accessing data from the Data, Code, Stack or Extra segments can be usually done by prefixing
instructions with the DS:, CS:, SS: or ES: (some registers and instructions by default may use the
ES or SS segments instead of DS segment).
Word data can be located at odd or even byte boundaries. The processor uses two memory
accesses to read 16-bit word located at odd byte boundaries. Reading word data from even byte
boundaries requires only one memory access.
Stack memory can be placed anywhere in memory. The stack can be located at odd memory
addresses, but it is not
recommended for performance reasons (see "Data Memory" above). Reserved locations:
0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer in
format segment: offset.
FFFF0h - FFFFFh - after RESET the processor always starts program execution at the FFFF0h
address.
Interrupts:
The processor has the following interrupts
INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using STI/CLI
instructions or using more complicated method of updating the FLAGS register with the help of
the POPF instruction.
When an interrupt occurs, the processor stores FLAGS register into stack, disables further
interrupts, fetches from the bus one byte representing interrupt type, and jumps to interrupt
processing routine address of which is stored in location 4 * <interrupt type>. Interrupt processing
routine should return with the IRET instruction.
NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR interrupt.
Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is stored in location
0008h. This interrupt has higher priority then the maskable interrupt.
Software interrupts can be caused by:

INT instruction - breakpoint interrupt. This is a type 3 interrupt.
INT <interrupt number> instruction - any one interrupt from available 256 interrupts.
INTO instruction - interrupt on overflow
Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When the CPU
processes this interrupt it clears TF flag before calling the interrupt processing routine.
Processor exceptions: Divide Error (Type 0), Unused Opcode (type 6) and Escape opcode (type 7).
Software interrupt processing is the same as for the hardware interrupts.

Instruction Set 1 Rev.

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INSTRUCTION SET

MOV op1, op2

It will not update any flags

PUSH will not update any flags

POP will not update any flags

XCHG will not update any flags

XCHG op1, op2

LEA BX, data

IN will not update any flags

Two forms of OUT instruction are available :

OUT will not update any flags

LDS Instruction - Load register and DS with words from memory

LDS register, memory address of first word

LDS will not update any flags

LDS op1, op2

LES register, memory address of first word.

LES will not update any flags

LES op1, op2

LAHF will not update any flags

All flags SF, ZF, AF, PF, and CF are updated

PUSHF will not update any flags

POP updates all the flags

ADD and ADC update all flags

;Add immediate number 74H to content of AL ADC CL,BL ;Add contents of BL

INC Instruction - Increments destination.

AF and CF are updated remaining flags are undefined

It works according to the following Algorithm:

;Clear AH for MSD

DAA Instruction - Decimal Adjust Accumulator

SUB destination, source

SBB destination, source

SUB and SBB update all the six flags.

SUB CL, BH ; CL = 0110 0101 = 101 decimal

DEC updates all the flags except CF.

Decrement Algorithm: Operand = operand - 1

NEG updates all the flags

CMP destination, source.

AAS Instruction - ASCII Adjust for Subtraction

;AL =0011 1001 =ASCII 9

All flags are updated except OF

if low nibble of AL > 9 or AF = 1 then:

if AL > 9Fh or CF = 1 then:

MUL updates OF and CF remaining flags are undefined

IMUL Instruction - Multiply signed numbers

IMUL Instruction performs a signed multiplication.

IMUL updates OF and CF remaining flags are undefined

AAM updates SF, ZF and PF

OF,AF and CF are undefined

When dividing a word by a byte , the word must be in the AX register.

All the flags are undefined

The SUB AH,AH instruction is a quick way to do.

The SUB DX,DX instruction does this quickly.

; AX = 37D7H = 14, 295 decimal

IDIV Instruction - Divide by signed byte or word IDIV source

All the flags are undefined

A signed word divided by a signed byte

AAD Instruction - ASCII adjust before Division

AAD updates SF, ZF and PF

OF,AF and CF are undefined

None of the flags are updated

None of the flags are updated

;Convert signed word in AX to signed double ;word in DX:AX

None of the flags are updated

;Complement contents of BX register.