module decode2_4(y,w,en

);
output[3:0] y;
input [1:0] w;
input en;
reg [3:0] y;
always @(w or en)
case({w,en})
3'b001: y=4'b0001;
3'b011: y=4'b0010;
3'b101: y=4'b0100;
3'b111: y=4'b1000;
default : y=4'b0000;
endcase
endmodule
__________________________
module compar4_bit(q,a,b
);
output [2:0] q;
input [3:0] a,b;
reg [2:0] q;
wire [3:0] x;
assign x=4'b1111;
assign A=(a[3:3]&~b[3:3])|(x[3:3]&a[2:2]&~b[2:2])|(x[3:3]&x[2:2]&a[1:1]
&~b[1:1])|(x[3:3]&x[2:2]&x[1:1]&a[0:0]&~b[0:0]);
assign B=(b[3:3]&~a[3:3])|(x[3:3]&b[2:2]&~a[2:2])|(x[3:3]&x[2:2]&b[1:1]
&~a[1:1])|(x[3:3]&x[2:2]&x[1:1]&b[0:0]&~a[0:0]);
always @( a or b)
begin
if(A) q<=3'b001;
else if(B) q<=3'b100;
else q<=2'b010;
end
endmodule
______________________________
module halfadder(s,c,x,y
);
output s,c;
input x,y;
xor (s,x,y);
and (c,x,y);

endmodule
module fulladder(s,c,x,y,z
);
output s,c;
input x,y,z;
wire s1,c1,c2;
halfadder h1(s1,c1,x,y);
halfadder h2(s,c2,s1,z);
or (c,c1,c2);
endmodule

___________________________
module dff(q,d,clk,set,rst
);
output q;
input d,clk,rst,set;
reg q;
always @(posedge clk,negedge rst)
if(~rst||~set)q<=1'b1;
else
q<=d;
endmodule
module dual_dff(q2,q,d2,d,clk2,clk,set2,set,rst2,rst
);
output q,q2;
input d,d2,clk,clk2,rst,rst2,set,set2;
dff dd1(q2,d2,clk2,set2,rst2);
dff dd2(q,d,clk,set,rst);
endmodule
___________________-______________
module jkff(q,j,k,clk,set,rst
);
output q;
input j,k,clk,set,rst;
wire jk;
assign jk=(j&~q)|(~k&q);
dff jk1(q,jk,clk,set,rst);
endmodule
module dff(q,d,clk,set,rst
);
output q;
input d,clk,set,rst;
reg q;
always @(posedge clk,negedge rst)
if(~rst||~set)q<=1'b1;
else
q<=d;
endmodule
________________________________________
module j_kff(q,j,k,clk,rst
);
output q;
input j,k,clk,rst;
wire jk;
assign jk=(j&~q)|(~k&q);
dff d2(q,jk,clk,rst);
endmodule
module dff(q,d,clk,rst
);

output q;
input d,clk,rst;
reg q;
always @(posedge clk,negedge rst)
if(~rst)q<=1'b0;
else
q<=d;
endmodule
module tff(q,t,clk,rst
);
output q;
input t,clk,rst;
wire d1;
assign d1=q^t;
dff t1(q,d1,clk,rst);
endmodule
module dff(q,d,clk,rst
);
output q;
input d,clk,rst;
reg q;
always @(posedge clk,negedge rst)
if(~rst)q<=1'b0;
else
q<=d;
endmodule
______________________________________
module mux2_1(m_out,a,b,select
);
output m_out;
input a,b,select;
reg m_out;
always @(a or b or select)
if(select==1'b0)m_out=a;
else m_out=b;
endmodule
module mux4_1(mout,a,b,c,d,s
);
output mout;
input a,b,c,d;
input[1:0] s;
reg mout;
always @(a or b or c or d or s)
if(s==2'b00)mout=d;
else if(s==2'b01)mout=c;
else if(s==2'b10)mout=b;
else mout=a;
endmodule
_______________________________________
module mux8_1(mout,a,b,c,d,e,f,g,h,str,s
);
output mout;

input a,b,c,d,e,f,g,h,str;
input[2:0] s;
reg mout;
always @(a or b or c or d or e or f or g or h or s or str)
if(str==1'b1)mout=1'b0;
else
case(s)
2'b000:mout<=h;
2'b001:mout<=g;
2'b010:mout<=f;
2'b011:mout<=e;
2'b100:mout<=d;
2'b101:mout<=c;
2'b110:mout<=b;
2'b111:mout<=a;
endcase
endmodule
_________________________________________
module halfadder(s,c,x,y
);
output s,c;
input x,y;
xor (s,x,y);
and (c,x,y);

endmodule
module fulladder(s,c,x,y,z
);
output s,c;
input x,y,z;
wire s1,c1,c2;
halfadder h1(s1,c1,x,y);
halfadder h2(s,c2,s1,z);
or (c,c1,c2);
endmodule
module rippleadder(sum,c4,a,b,c0
);
output [3:0] sum;
output c4;
input [3:0] a,b;
input c0;
wire c1,c2,c3;
fulladder fa0(sum[0],c1,a[0],b[0],c0),
fa1(sum[1],c2,a[1],b[1],c1),
fa2(sum[2],c3,a[2],b[2],c2),
fa3(sum[3],c4,a[3],b[3],c3);
endmodule
__________________________________________
module shift4bit(q,p,clk,rst,s1,s0,l,d
);
output [3:0] q;
input [3:0] p;
input s1,s0,l,d,clk,rst;

reg [3:0] q;
always @(posedge clk,negedge rst)
if (~rst)q<=4'b0000;
else
case({s1,s0})
2'b00:q<=q;
2'b01:q<={d,q[3:1]};
2'b10:q<={q[2:0],l};
2'b11:q<=p;
endcase
endmodule