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ELECTRNICA
CONTROL DIGITAL
DEBER
Tema: COMPENSADORES Y CONTROLADORES
Profesor: Ing. Edwin Aguilar
Estudiante:
Nivel: Sptimo
Fecha de realizacin: 15 de Enero del 2016
Mf= 59.3
B. - to reduce steady state errors, k is incremented to k=5, design a
unity DC gain phase lag controller that yields a system phase margin of
45.
C. - design a unity DC gain phase lead controller, with k=5, that yields a
system phase margin of 45
CONTROLADOR PD
PROGRAMA EN MATLAB
GRAFICAS