Ce06sl PDF

Sequential Circuits
Sequential Circuits
Tilman Schieber (TU Berlin)
Computer Engineering
2016
87
Sequential Circuits
Saving 1 Bit
Overview
Saving 1 Bit
2016
88
Sequential Circuits
Saving 1 Bit
The Need for Memory
A computer without memory is not possible. We need it to

store instructions to be executed
store the data our program needs
While a computer typically has gigabytes of memory, we start at the very

beginning:
How can we store one bit?
2016
89
Sequential Circuits
Saving 1 Bit
Storing One Bit

RS-Latch
Two inputs S (set) and R (reset)

Two outputs Q and Q
it can save one bit. . . but how?
2016
90
Sequential Circuits
Saving 1 Bit
Sequential Circuits
We have never seen a circuit like this before

It has a feedback circle
We cant express it with a boolean function
Q(R, S) = (S (R (S (R (S . . . ?
so how does it work?
2016
91
Sequential Circuits
Saving 1 Bit
Two States of a Latch
Storing 0
Q = (0 1) = 0
Q = (0 0) = 1
Storing 1
Q = (0 0) = 1
Q = (0 1) = 0
2016
92
Sequential Circuits
Saving 1 Bit
Setting and Resetting

Now we activate the set and reset inputs:
Set
Reset
We can explain the behaviour of this Circuit
Truth tables and Boolean expressions however dont help us

we need a new tool to describe a sequential circuit
2016
93
Sequential Circuits
Saving 1 Bit
State Table
State Table for a Latch
S
0
0
1
1
0
0
1
1
R
0
1
0
1
0
1
0
1
Q(t)
0
0
0
0
1
1
1
1
Q(t + 1)
0
0
1
1
0
1
This is a 1-dimensional state table
(characteristic table)
For each input combination and current
state (Q(t)) the new state (Q(t + 1)) is

given
Note that for S = R = 1 our circuit is
undefined.
2016
94
Sequential Circuits
Timing and Clocks
Overview
Timing and Clocks
2016
95
Sequential Circuits
Timing and Clocks
Timing
To further talk about memory we need a better understanding of
timing
As a sequential circuit changes over time, depending on inputs, we
need to analyze gates and circuits in regard to their timing properties
2016
96
Sequential Circuits
Timing and Clocks
Gate Delay
each gate needs a certain time to switch
we call this propagation delay tP

the time the output needs to switch from low (0) to high (1) is tPLH
from high to low: tPHL
these values differ depending on technology, temperature and many
other factors.
Generally the manufacturer guarantees a maximum delay.
2016
97
Sequential Circuits
Timing and Clocks
Gate Delay: Example

Timing Diagram for an AND-Gate
tPLH
tPHL
x y
2016
98
Sequential Circuits
Timing and Clocks
Logic Glitches
For a short moment, a circuit may have a wrong output because of
propagation delay
Circuit for x y
x
y
inputs change from both 0 to
both 1. The output should
always be 0.
inv
and
2016
99
Sequential Circuits
Timing and Clocks
Handling Glitches
To be sure that the output of the circuit is correct we have to wait
until all the gates have switched
How to realize this in a computer?
2016
100
Sequential Circuits
Timing and Clocks
Handling Glitches
To be sure that the output of the circuit is correct we have to wait
until all the gates have switched
How to realize this in a computer?

Solution: We need a clock
2016
100
Sequential Circuits
Timing and Clocks
Clocks
a clock is a special signal that toggles its value between 0 and 1 n
times every second
its frequency is n1 Hz (hertz), modern computers clocks have up to
5.2 GHz
we use a clock generator (based on an oscillator crystal)
Clock Signal
clk
2016
101
Sequential Circuits
Timing and Clocks
Clock Signal
Parts of a Clock Signal

rising
falling
clk
high
low
2016
102
Sequential Circuits
From Flip-Flops to Memory
Overview
2016
103
Sequential Circuits
Clocked SR-Latch
Now we use a clock to control writing to a latch
The latch can only be set or reset when the clock is 1

we call such a latch synchronous
Clocked SR-Latch
2016
104
Sequential Circuits
D-Latch
We can improve this design
The problematic case when both inputs are 1 should not occur
Solution: We use one input called D (data) to set or reset the latch.
Clocked D-Latch
2016
105
Sequential Circuits
Edge-Triggering a Latch
It needs only little time to store a bit with a latch
In practice most memory stores D on the rising edge of the clock

we call this edge-triggered
to achieve this we need a so-called pulse generator
2016
106
Sequential Circuits
Pulse Generator
Circuit and Timing Diagram
clock
output
the NOT-gate has a short delay tP
when the clock changes from 0 to 1 the output is 1 for tP

2016
107
Sequential Circuits
D-Flip-Flop
If we combine this pulse generator with a clocked D-latch, we get the
following circuit:
D-Flip-Flop
2016
108
Sequential Circuits
D-Flip-Flop Behaviour
The content of the D-input is saved when the clock goes from 0 to 1
this is called the rising edge of the clock signal
the flip-flop is set synchronously
Timing Diagram
clock
D
Q
2016
109
Sequential Circuits
Asynchronous Set/Reset
Some flip-flops also allow asynchronous (re-)set
In this case they have extra inputs that change without depending on
the clock
D-FlipFlop with Asynchronous (Re-)Set
2016
110
Sequential Circuits
Symbols
From now on we will use symbols for latches and flipflops. The clock input
is denoted by a triangle.
SR-Latch
clocked SR-Latch
D-FF async.SR
D-FF in Logisim
D-FlipFlop
2016
111
Sequential Circuits
Building a Register
To get bigger memory we can simply combine flipflops
The circuit we get this way is called a register
It uses one clock signal to save all inputs in parallel
4-Bit Register
2016
112
Sequential Circuits
Building RAM
A Register is practical for some bits... but not for RAM
our memory chip would need at least 2 pins for every bit.
So we need a clever way to put those flip-flops together
2016
113
Sequential Circuits
RAM Design Ideas
Data is read and written in words, not bits (e.g. 16 or 32 bits)
There is an address input that decides which word to read or write
We put the same input to all flip-flops, they are only written when
selected
we activate the output of a flip-flop only when selected, so we use

common output lines
2016
114
Sequential Circuits
RAM: Inputs and Outputs
Inputs needed:
1 data in
2 address bits (choose which flip-flop to read or write)
3 read bit (do we want to read or write?)
4 chip select (tell the chip if we want to use it)
Outputs needed:
data out
2016
115
Sequential Circuits
RAM: Data Input
We look at an example 44 RAM (4 words with 4 bits each):
Example RAM: Inputs
2016
116
Sequential Circuits
RAM: Addressing
We use a decoder to address a specific word in the RAM
Example RAM: Addressing
2016
117
Sequential Circuits
Combining In- and Outputs

in- and output pins are never used at the same time
therefore we can we can use the same pins for both
we need to disconnect the output lines when writing to the chip.

Otherwise the output would overwrite the incoming data.
we use a controlled buffer:
2016
118
Sequential Circuits
Controlled Buffer
a controlled buffer is a so-called tri-state device
it has three instead of two states: true, false, unknown

it has a data and a control input
if control is 1, it acts like a normal wire
if control is 0, its like a cut wire: the output is unknown
2016
119
Sequential Circuits
A Complete 44 RAM
Example RAM
2016
120
Sequential Circuits
44 RAM: Observations
When CS (chip select) is 0, the RAM cannot be read or written
When RD is 1, the RAM is read, when its 0 the data input is written
to activate the output lines, OE (output enable) has to be set to 1
only the row of flip-flops activated by the two address bits can be
accessed
2016
121

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Sequential Circuits

Tilman Schieber (TU Berlin)

Tilman Schieber (TU Berlin)

The Need for Memory

A computer without memory is not possible. We need it to

store the data our program needs

While a computer typically has gigabytes of memory, we start at the very

Tilman Schieber (TU Berlin)

Storing One Bit

Two inputs S (set) and R (reset)

it can save one bit. . . but how?

Tilman Schieber (TU Berlin)

We have never seen a circuit like this before

We cant express it with a boolean function

Tilman Schieber (TU Berlin)

Two States of a Latch

Tilman Schieber (TU Berlin)

Setting and Resetting

We can explain the behaviour of this Circuit

Truth tables and Boolean expressions however dont help us

Tilman Schieber (TU Berlin)

Tilman Schieber (TU Berlin)

This is a 1-dimensional state table

For each input combination and current

state (Q(t)) the new state (Q(t + 1)) is

Note that for S = R = 1 our circuit is

Timing and Clocks

Timing and Clocks

Tilman Schieber (TU Berlin)

Timing and Clocks

To further talk about memory we need a better understanding of

As a sequential circuit changes over time, depending on inputs, we

need to analyze gates and circuits in regard to their timing properties

Tilman Schieber (TU Berlin)

Timing and Clocks

each gate needs a certain time to switch

we call this propagation delay tP

Generally the manufacturer guarantees a maximum delay.

Tilman Schieber (TU Berlin)

Timing and Clocks

Gate Delay: Example

Tilman Schieber (TU Berlin)

Timing and Clocks

Tilman Schieber (TU Berlin)

Timing and Clocks

To be sure that the output of the circuit is correct we have to wait

until all the gates have switched

How to realize this in a computer?

Tilman Schieber (TU Berlin)

Timing and Clocks

To be sure that the output of the circuit is correct we have to wait

until all the gates have switched

How to realize this in a computer?

Tilman Schieber (TU Berlin)

Timing and Clocks

times every second

its frequency is n1 Hz (hertz), modern computers clocks have up to

we use a clock generator (based on an oscillator crystal)

Tilman Schieber (TU Berlin)

Timing and Clocks

Parts of a Clock Signal

Tilman Schieber (TU Berlin)

From Flip-Flops to Memory