IEEE 1149.

1
1149 1 (JTAG)
Boundary Scan Architecture

Introduction
y TestingastandalonechipisrelativelyeasybecauseallI/Opinsare

controllable and observable

controllableandobservable
y Onceachipismountedonaprintedcircuitboard(PCB),theproblem

b
becomesmuchmorecomplex.
h
l
y Conventionalbedofnailsboardleveltestmethodencountered

difficultiesindealingwithmultiplelayerboards.
y Withtheadventofsurfacemountpackagesandmultiplechipmodules
With the advent of surface mount packages and multiple chip modules

(MCMs),thismethodbecomesinfeasibleasnoorfewthroughhole
pinsareavailableforprobing

Board Level Testing Methodology

Device Packaging Styles

Issues with Inline Testing

JTAG Meeting
Meeting, 17 September,
September 1988
OriginallyknownasJointEuropeanTestActionGroup(JETAG)

Motivation for Boundary Scan

y Basicmotivationwasminiaturizationofdevicepackaging,leadingto
y Surfacemountpackagingstyles,leadingto
Surface mount packaging styles leading to
y Doublesidedboards,leadingto
y Multilayerboards,leadingto
y Reductionofphysicalaccesstestlandsfortraditionalbedofnailin
d
f h
l
l d f
d
lb d f
l

circuittesters

y Problem:Howtotestformanufacturingdefectsinthefuture?
y Solution:Addboundaryscanregisterstothedevices

IEEE1149.1standarddefinestestlogicthatcanbeincludedinanintegratedcircuitto
providestandardizedapproachesto
TestingtheinterconnectionsbetweenICsafterassembledontoaPCB
Testingtheintegratedcircuititself
Observingormodifyingcircuitactivityduringthecomponent'snormaloperation

Boundary Scan Architecture

Specifications
y Testlogicarchitecturecontains

ATAP
A
TAP
ATAPcontroller
Aninstructionregister
A group of test data registers
Agroupoftestdataregisters
y Instructionandtestdataregistersshallbeseparateshiftregister

basedpathsthatareconnectedinparallelandhaveacommonserial
data input and a common serial data output connected to the TAP TDI
datainputandacommonserialdataoutputconnectedtotheTAPTDI
andTDOsignals,respectively.
y Theselectionbetweenthealternativeinstructionandtestdata

register paths between TDI and TDO is controlled by TAP controller

registerpathsbetweenTDIandTDOiscontrolledbyTAPcontroller
The TAP controller, the instruction register, and the associated circuitry necessary for
control of the instruction and test data registers shall be dedicated test logic (i.e.,
(i e
these test logic blocks shall not perform any system function).

Top Level View

Boundary Scan Overview

TESTACCESS
PORT(TAP)

y Fourdedicatedtestpins:
p

SCANCELLS

y PlaceBoundaryscanregister(BSR) adjacenttoeachpin

TestDataIn(TDI)
TestModeSelect(TMS)
TestClock(TCK)
(
)
TestDataOut(TDO)
TestReset(TRST*){optional}

y Stitchesinput&outputportsofallchipsonthePCBinto

scanchain
h i
TAP
CONTROLLER

y Statemachinethatcontrolsboundaryscanoperation
y TCK,TMS,andTRST*
y Instructionsdecodelogic

REGISTERS

y Nbit(N>=2)Instructionregister,holdingthecurrent

instruction
y 1bitBypassregister
y 32bitIdentificationregister{optional}
y OnlyonedataregistercanbeconnectedbetweenTDI

and TDO
andTDO
y TheselectedDataregisterisidentifiedbythedecoded

paralleloutputsoftheInstructionregister
INSTRUCTONS

y Inadditiontothehardwarecomponents,definesasetof

testinstructions
Fourmandatoryones(BYPASS,SAMPLE,PRELOAD,and
EXTEST)
Severaloptionalones,includingINTEST,RUNBIST,CLAMP,
IDCODE,USERCODE,andHIGHZ
y Allowstheuserstodefinetheirowninstructions
ll
h
d f
h

Test Access Port (TAP)

Consistsofminimum4pinsforthefoursignalsthatmakeupthetestbus
Pin
TCK (TestClock)
TCK
(T t Cl k)
TMS(TestModeState)
TDI(TestDataIn)

TDO(TestDataout)
TRST(TestReset)*

Description
Synchronizestheinternalstatemachine
y
operations
Determinesthenextstate
Sa p ed at s g edge o C
SampledatrisingedgeofTCK
Representsthedatashiftedintothedevice'stest
orprogramminglogic
It is sampled at the rising edge of TCK
ItissampledattherisingedgeofTCK
Representsthedatashiftedoutofthedevice's
testorprogramminglogic
g g
ValidonthefallingedgeofTCK
Anoptionalpin
ResetstheTAPcontroller'sstatemachine

Basic idea of boundary scan

y Datashiftsalongscanpath{

TDI(testdatain)
TDI(test
data in)
dataout)}

TDO(test
TDO(test

y TDOofonechipfeedsthe
f
h f d h

TDIofthenext
y TheinputsTCK(testclock)

andTMS(testmodeselect)
connect,inparallel,toeach
boundaryscandeviceinthe
scanpath.

Cont..
Cont
y Toallowtheinterconnectionsbetweenthevariouscomponentstobe

tested
y testdatacanbeshiftedintoalltheboundaryscanregistercells

associatedwithcomponentoutputpinsandloadedinparallelthrough
the component interconnections into those cells associated with input
thecomponentinterconnectionsintothosecellsassociatedwithinput
pins
y Toallowthecomponentsontheboardtobetested,theboundary

scanregistercanbeusedasameansofisolatingonchipsystemlogic
scan
register can be used as a means of isolating on chip system logic
fromstimulireceivedfromsurroundingcomponentswhileaninternal
selftestisperformed.
y Alternatively,iftheboundaryscanregisterissuitablydesigned,itcan
Alternatively if the boundary scan register is suitably designed it can

permitalimitedslowspeedstatictestoftheonchipsystemlogic
sinceitallowsdeliveryoftestdatatothecomponentandexamination
of the test results
ofthetestresults.

Boundary scan register (BSR)

Boundary-scan

Boundary Scan Cell (BSC)

y BSCsareplacedbetweentheinternallogicandeachIOpin.
y BSCscollectivelycompriseaparallelin,paralleloutshiftregisterthat

runsalongtheperipheryofthedesign.
y Boundaryscancellscontainmemoryelementsfor(Dependentonthe

controlsignalsappliedtothemultiplexers)
Capturingdatafromthecircuit
Capturing
data from the circuit
Loadingdataintothecircuit
Seriallyshiftingdatatothenextscancell
y Secondflipflopisprovidedtoensurethatthesignalsdrivenoutof

thecellareheldwhilenewdataisshiftedintocell(notrequiredinall
cases)

Modes in Boundary Scan

Normal Mode
Update Mode

Mode

Shift/Load

Capture Mode
Scan Mode

Normalmode

Capturemode

y SignalMode=0

y Shift/Load=0

y Cellistransparent

y Inputvalueisstoredwithinthescan

y Outputcorrespondstoinputvalue

chain
y TheoutputvalueinDataOut depends

ontheModesignal.

UpdateMode
y Mode=1

Scanmode
y Shift/Load=1

y QA value,previouslyloadedbyaScanor y Cellsareconnectedinseriestoforma

aCaptureoperation,islatchedintothe
UpdateFlipFlip

chainthroughthesignalsSerialIn and
SerialOut

Instruction Register
y Storestheinstructiontobeexecuted
y Controlstheoperationaffectingthedatainthatregister,usinga
Controls the operation affecting the data in that register using a

predefinedsetofinstructions.
y ReceivesinstructionthroughTDI,decodesit,andselectsthe
appropriatedataregister
y Theshiftregisterholdstheinstructionbitsmovingthroughthe
InstructionRegisterandthelatchesholdthecurrentinstruction.
y ThesizeoftheInstructionRegisterdependsonthenumberof
implementedinstructions.

Data Registers
y BSR:
BSR : Movesdatatoandfromthe
Moves data to and from the pins
pins onadevice.
on a device
y BYPASS :singlebitregisterthatpassesinformationfromTDItoTDO.Itallows

otherdevicesinacircuittobetestedwithminimaloverhead.

y Otherdataregistersmaybepresent,butarenotmandatory
g
y p
,
y
y EX:Deviceidentification Containsadeviceidentificationcode

Instruction Set
y Fourmandatoryboundaryscantestinstructions(BYPASS,SAMPLE,

PRELOAD and EXTEST)

PRELOAD,andEXTEST)
y Otherusefulinstructions,includeINTEST,RUNBIST,CLAMP,IDCODE,

USRCODE,andHIGHZ{optional}

Bypass
y Selectsbypassregister
y Providesshortscanpath:1bit

betweenTDIandTDO
y Usedwhennotestoperationof

thatcomponentisrequired;
bypassingofchip
y Usuallyloadedinchipsthatare
y
p

idlewhileotherchipsonthe
boardarebeingtested

BSR Instructions
y SAMPLE,PRELOAD,EXTEST,and

INTESTinstructionscomeunder
INTEST
instructions come under
thiscategory
y Basedontherequiredoperation,
d
h
d

itperformsClockDR,ShiftDR,
andUpdateDRoperations
y Dataflowsbetweenthe

componentssystempins,the
boundaryscanregistercells,and
theonchip systemlogic

Sample
y Boundaryscanregisterselected
y Obtainasnapshotofthenormalcomponentinputandoutputsignals
Ob i
h
f h
l
i
d
i l
y StoretheminthefirstofthetwomasterslaveflipflopsintheBSRs
y Deviceinfunctionalmode,nottestmode
y Noeffectontheinternallogicorontheflowofsignalsbetweenthe

internallogicandtheI/Opinsofthechip

Preload
y Boundaryscanregisterselected
y Allowstestdatatobeshiftedintooroutoftheselecteddataregister;
All
d
b hif d i
f h
l
dd
i

shifteddataarethenlatchedtotheparalleloutput(R2)
y Deviceinfunctionalmode,nottestmode
y Nointerferencetothenormaloperationoftheinternallogic

Extest
y Teststhecircuitryexternaltothechips,typicallytheinterconnects

between chips and between boards

betweenchipsandbetweenboards
y Usedtoapplypatternstotheinterconnectstructuresontheboard
y Boundaryscancellshavepermissiontowritetotheiroutputs(device

intestmode)
d )
y Maintestinstructionforboundaryscantesting

Test Interconnect line from Chip1 to Chip2

Intest
y Boundaryscanregisterselected
y Usedtoapplypatternstothedeviceitself
U d
l
h d i i lf
y Testsachipsinternalcircuitrybyapplyingatestvectorto,and

capturingtheoutputresponsefrom,theapplicationlogic
y Boundaryscancellshavepermissiontowritetotheiroutputs(device

intestmode)

Execution of INTEST instruction

RunBIST
y Purpose:Allowsyoutoissue

BISTcommandtocomponent
throughJTAGhardware
y Optionalinstruction
y Theselftestroutinemustbe

selfinitializing(i.e.,noexternal
seedvaluesareallowed)
y Essentiallytargetsaselftest

resultregisterbetweenTDIand
TDO.
y Attheendoftheselftestcycle,

thetargeteddataregisterholds
/
thePass/Failresult.

Idcode
y Purpose:Connectsthecomponent

deviceidentificationregister
device
identification register
seriallybetweenTDIandTDOIn
theShiftDRTAPcontrollerstate
y Capture
Capturess32bitidentificationcode
32 bit identification code
y Thedeviceidentificationregister

containsthedeviceIDnumber,
which is normally used to
whichisnormallyusedto
determineifthechipisreallyapart
oftheboard.

Other Instructions
y Usercode

Selectstheidentificationregister,
Selects
the identification register
buttheinformationplacedin
thatregisterisnowuserdefined
y HighZ

Putsallcomponentoutputpin
signals into highimpedance state
signalsintohighimpedancestate
y Clamp

Forcescomponentoutputsignals
Forces
component output signals
tobedrivenbyboundaryscan
register

TAP Controller
y 16statefinitestatemachineaddedontheICdieitself
y Recognizesthecommunicationprotocol;Generatesinternalcontrol
R
i
h
i i
l G
i
l
l

signalsusedbytheremainderoftheboundaryScanlogic
y DrivenbyTCKandTMS(andoptionalTRST*)
y 5cyclesofTCKwithTMSheldhighwillresetthemachine
y TwosteadystatesexistforTestLogicResetandRunTest/Idle
y Remainingstatesrepresenttwomajorbrachesaccessingthe
Remaining states represent two major braches accessing the

instructionanddataregisters
y Onlythreeeventscantriggerachangeofcontrollerstate:

Testclockrisingedge,
Testclock
rising edge
Assertionofalogic0ontoaTRST*(ifitexists)
Systempowerup.

Main functions of TAP controller

y Providingcontrolsignalsto

ResetBScircuitry
Reset
BS circuitry
Loadinstructionsintoinstructionregister
Performtestcaptureoperation
Perform test update operation
Performtestupdateoperation
Shifttestdatainandout

TAP controller state diagram

Transitions
are based on
the value of
the TMS

Note: Controls for IR are similar to those for DR

States of TAP Controller

TestLogicReset
Test
Logic Reset

Normal mode
Normalmode

RunTest/Idle

WaitforinternaltestsuchasBIST

S l t DR S
SelectDRScan

I iti t d t
Initiateadatascansequence

CaptureDR

Loadtestdatainparallelonto1st flop

ShiftDR

Loadtestdatainseries

Exit1DR
PauseDR

Finishphase1shiftingofdata
T
Temporarilyholdthescanoperation(e.g.,
il h ld th
ti (
allowthebusmastertoreloaddata)

Exit2DR

Finishphase2shiftingofdata
p
g

UpdateDR

Parallelloadfromassociatedshiftregisters

1: TESTLOGIC-RESET

Test not completed,

returns to step 5

22: Instruction
I
i
SAMPLE/PRELOAD
set-up

7: Update
next stimulus

3: Load Boundaryy
Scan Register

6: Shift out
response pattern

4: Load EXTEST

5: Capture
Response Pattern

Boundary Scan process on a Chip

TAP Controller State Diagram

Test-Logic-Reset

0
Run-Test/Idle
Run
Test/Idle

Select-DR-Scan
Select
DR Scan

Select-IR-Scan

0
1

Capture-DR

Capture-IR

Shift-DR

Shift-IR

Exit1-DR

Exit1-IR

Pause-DR

1
0

Exit2-DR

Exit2-IR

Update-DR

Pause-IR

1
0

Update-IR

SAMPLE/PRELOAD: UpdateIR
p
SAMPLE/
DATA
PRELOAD

TMS
TDI
TCK

TDO
TRST_N

TAP
Controller
SMP/PRLD
BYPASS

Chip
Core

TAP Controller State Diagram

Test-Logic-Reset

0
Run-Test/Idle
Run
Test/Idle

Select-DR-Scan
Select
DR Scan

Select-IR-Scan
Select
IR Scan

0
1

Capture-DR

Capture-IR

Shift-DR

Shift-IR

Exit1-DR

Exit1-IR

Pause-DR

1
0

Exit2-DR

Exit2-IR

Update-DR

Pause-IR

1
0

Update-IR

SAMPLE/PRELOAD: CaptureDR
p
Capture (sample)

DATA

Mode=0

TMS
TDI
TCK
TDO

0
TAP
Controller

Chip
Core

SMP/PRLD
0

TRST_N
0

TAP Controller State Diagram

Test-Logic-Reset

0
Run-Test/Idle
Run
Test/Idle

Select-DR-Scan
Select
DR Scan

Select-IR-Scan
Select
IR Scan

0
1

Capture-DR

Capture-IR

Shift-DR

Shift-IR

Exit1-DR

Exit1-IR

Pause-DR

1
0

Exit2-DR

Exit2-IR

Update-DR

Pause-IR

1
0

Update-IR

SAMPLE/PRELOAD: ShiftDR
01

01

DATA

10

10

TMS
TDI
TCK
TDO

01
TAP
Controller
SMP/PRLD

Chip
Core

10
01

TRST_N
1
0
1
0

10

01

01

01

TAP Controller State Diagram

Test-Logic-Reset

0
Run-Test/Idle
Run
Test/Idle

Select-DR-Scan
Select
DR Scan

Select-IR-Scan
Select
IR Scan

0
1

Capture-DR

Capture-IR

Shift-DR

Shift-IR

Exit1-DR

Exit1-IR

Pause-DR

1
0

Exit2-DR

Exit2-IR

Update-DR

Pause-IR

1
0

Update-IR

SAMPLE/PRELOAD: UpdateDR
p
1

Mode=0
TMS
TDI
TCK
TDO

1
TAP
Controller
SMP/PRLD

Chip
Core

0
1

TRST_N
1

TAP Controller State Diagram

Test-Logic-Reset

0
Run-Test/Idle
Run
Test/Idle

Select-DR-Scan
Select
DR Scan

Select-IR-Scan
Select
IR Scan

0
1

Capture-DR

Capture-IR

Shift-DR

Shift-IR

Exit1-DR

Exit1-IR

Pause-DR

1
0

Exit2-DR

Exit2-IR

Update-DR

Pause-IR

1
0

Update-IR

EXTEST: UpdateIR
p
EXTEST

Mode=1

TMS
TDI
TCK
TDO

1
TAP
Controller
EXTEST

Chip
Core

TRST_N
1

TAP Controller State Diagram

Test-Logic-Reset

0
Run-Test/Idle
Run
Test/Idle

Select-DR-Scan
Select
DR Scan

Select-IR-Scan
Select
IR Scan

0
1

Capture-DR

Capture-IR

Shift-DR

Shift-IR

Exit1-DR

Exit1-IR

Pause-DR

1
0

Exit2-DR

Exit2-IR

Update-DR

Pause-IR

1
0

Update-IR

EXTEST: CaptureDR
p
Capture (sample)

01

DATA

01

TMS
TDI
TCK
TDO

1
TAP
Controller
EXTEST

10

Chip
Core

TRST_N
1

10

10

TAP Controller State Diagram

Test-Logic-Reset

0
Run-Test/Idle
Run
Test/Idle

Select-DR-Scan
Select
DR Scan

Select-IR-Scan
Select
IR Scan

0
1

Capture-DR

Capture-IR

Shift-DR

Shift-IR

Exit1-DR

Exit1-IR

Pause-DR

1
0

Exit2-DR

Exit2-IR

Update-DR

Pause-IR

1
0

Update-IR

EXTEST: ShiftDR
DATA

01

01

01

01

TMS
TDI
TCK
TDO

01
TAP
Controller
EXTEST

Chip
Core

01
01

TRST_N
1
1
1
1

01

01

01

01

TAP Controller State Diagram

Test-Logic-Reset

0
Run-Test/Idle
Run
Test/Idle

Select-DR-Scan
Select
DR Scan

Select-IR-Scan
Select
IR Scan

0
1

Capture-DR

Capture-IR

Shift-DR

Shift-IR

Exit1-DR

Exit1-IR

Pause-DR

1
0

Exit2-DR

Exit2-IR

Update-DR

Pause-IR

1
0

Update-IR

EXTEST: UpdateDR
p
0
DATA

Mode=1

TMS
TDI
TCK
TDO

0
TAP
Controller

Chip
Core

EXTEST
0

TRST_N
0

Benefits of Boundary Scan

y Limitationsofincircuittestprovingtobeabottleneckfortesting,

boundaryscanprovidesthesamebenefits,withoutrequiringphysical
boundary
scan provides the same benefits without requiring physical
accesstoeachelectricalnetwork
y Primaryuseisinboardleveltesting,butitcanalsocontrolcircuitlevel

test structures such as BIST or internal scan

teststructures,suchasBISTorinternalscan
y Createsstandardinterfaceforaccessing&testingchipsatboardlevel
y Detectsvastmajorityofboardmanufacturingprocessfaultslikewrong

components,missingcomponents,incorrectlyorientedcomponents,
componentswithstuckpins,shorts,opens,andblownwirebonds
y Althoughyourengineeringcostsmayincreaseslightlybecauseofthe

additionalsiliconandportsusedfortheboundaryscancircuitry,
implementingtheIEEE1149.1standardcandramaticallyreduce
designsmanufacturingcosts