IJIRST International Journal for Innovative Research in Science & Technology| Volume 3 | Issue 02 | July 2016

ISSN (online): 2349-6010

Design of a Vedic Arithmetic and Logical Unit

using Lab View
Jyoti
M. Tech Student
Department of Electronics & Communication Engineering
Appa IET ,kalaburgi, VTU, Belagavi, India

Anuradha. S
Associate Professor
Department of Electronics & Communication Engineering
Appa IET ,kalaburgi, VTU, Belagavi, India

Abstract
In the todays technologies the computation unit is the important unit of all of the currently available technology. This paper
represents the design concept of Vedic Arithmetic and logical unit using labview. The LABVIEW is used here to perform all
design methodology. Every module of ALU is implemented in LABVIEW. Vedic mathematics is used in the multiplier unit.
The Vedic mathematics sutra Urdhvatriyakbhyam is used to design Vedic multiplier. The labview illustrates how the CPU
executes simple and a few complex operations using basic logic functions.
Keywords: Labview, vedic mathematics, ALU
_______________________________________________________________________________________________________
I.

INTRODUCTION

It is evident in the present day technologies that the computation unit is no doubt the important unit of all of the currently
available technologies that performs all the arithmetic operations, namely division, addition, subtraction and multiplication. Also
the logical operations specifically XOR, OR, AND etc. These logical operations are the most leading characteristics in any
digital area related applications. Along with performing arithmetic operations the ALU also performs logical operations. Also,
that is the reason ALU is known as the important of Microcontrollers, Microprocessors and CPUs. An ALU is a part of CPU that
performs arithmetic and logical operations on operands in the instruction word. In most processors, ALU incorporates two units,
arithmetic and logic unit. The processor's operations are carried over by ALU. The ALU loads the information values from
accessible info registers. The operation to be performed is controlled by external control unit. The result is stored in the output
register.
II. LITERATURE SURVEY
Nisha,C,K, Saranya.M.K, [1] In this paper fast multipliers using UrdhvaTriyagbhyam sutra are represented. The VHDL code is
used to design multiplier and simulated using AlteraQuartus II EP1C20F400C7 device. The worst case delay measured of the
proposed 4-bit Vedic multiplier was found to 23.165ns.
ManaswiniDehury, Anita Mohanty [2]In this paper the four bit ALU is designed. The ALU is designed using LABVIEW. The
LABVIEW illustrates how the simple and complex operations are executed by CPU using logic functions.
K.Vinay Kumar, B.Shiva Kumar, [3]In this paper DML mode of logic is used to design ALU. In an situation where the
systems need faster operations and power dissipations are considered up to some extents this proposed efficient ALU is used.
K.Madan Mohan,R,NareshNaik [4]In this paper they have used UrdhvaTriyakbhyam to design a method which is a faster
multiplication technique. They have used verilog for coding 16-bit and 32-bit fractional fixed point multiplications and Xlinx is
used for synthesization.
Honey DurgaTiwari, Chan Mo Kim, [5]In this paper they have proposed a multiplier architecture and a square architecture
using the ancient Indian Vedic Mathematics algorithm, for the applications which require high speed and low power. They have
implemented on ALTERA cyclone-II FPGA which shows that this multiplier is faster compared to other multipliers.
Jagadguru Swami Sri Bharati Krishna [6] All the computations based on Vedic, clarification of sutra and complete exchanges
were included in this. In this paper right from scratch all explanations it has. This contains the entire thing of Vedic systems, the
related sutraswith the clarifications.

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Design of a Vedic Arithmetic and Logical Unit using Lab View

(IJIRST/ Volume 3 / Issue 02/ 017)

III. SYSTEM ARCHITECTURE

Fig. 1: proposed ALU

Implementation of Four-Bit ALU:

Fig. 2: Implementation of Four- Bit ALU

The Vedic ALU is designed after designing all the individual units that are adder/subtractor, multiplier, divider, comparator. The
Adder circuit adds two 4-bit operands and produces result. A comparator takes two 4-bit numbers as input and produces output

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Design of a Vedic Arithmetic and Logical Unit using Lab View

(IJIRST/ Volume 3 / Issue 02/ 017)

as whether one input is greater than the other, less than the other, or equal to the other. The 4-bit Vedic multiplier multiplies two
4-bit inputs and produces the result and the parallel divider takes two 4-bit numbers as input and produces the output .Three logic
operations are performed that are AND,OR and XOR operations. The logic operations are performed bit by bit. In this 4-bit
Vedic ALU the 4-bit opcode is used to select the operation that is to be performed. The table shows the specifications of ALU.
Sl.No
1
2
3
4
5
6
7

S3
0
0
0
0
0
0
0

Table 1
Specifications of ALU.
S3 S1 S0
operation
0
0
1 Addition / subtraction
0
1
0
AND
0
1
1
Multiplication
1
0
0
Division
1
0
1
XOR
1
1
0
Comparison
1
1
1
OR

Fig. 3: Result of Vedic ALU

IV. METHODOLOGY
To design a Vedic ALU the major blocks of the complete application are to be designed. The major blocks required are Vedic
multiplier, Adder/Subtractor, Parallel divider, 4 I/P AND gate, 4 I/P OR gate and 4 I/P x-or gate and Comparator circuit. The
vedic mathematics is used to design multiplier. To plan a Vedic multiplier we utilize Vedic mathematics. Vedic is a word "Veda"
and its significance is "storage facility of all learning". It involves the 16 sutras. These sutras can be related to different branches
of mathematics like geometry, algebra, arithmetic etc
Basically, Vedic mathematics is component of four Vedas which are the books of wisdom. Being a part of Sthapatya Veda
which is a book on civil engineering and architecture, which in turn serves as a supplement to Athrva Veda. It provides full
explanation of various mathematical terms incorporating arithmetic, geometric, trigonometric, quadratic equations, factorization
and also calculus. His Holiness Sri Jagadguru Shankaracharya Bharati Krishna Teerthaji Maharaj (1884- 1960) contained his
whole work at one place and gave them their mathematical explanation and also gave details about its various applications.
Swamiji constructed 16 sutras or formulae and 16 upasutras or sub formulae after a broad research he performed in Atharva
Veda.

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Design of a Vedic Arithmetic and Logical Unit using Lab View

(IJIRST/ Volume 3 / Issue 02/ 017)

V. CONCLUSION
In this paper 4-bit Vedic ALU is designed using LABVIEW. The 4-bit Vedic ALU designed here is faster. The precision can be
converted to 8-bit, 16-bit or more easily. From the implementation and outcome, it can be concluded that this ALU can work in
appropriate condition and executes different operations effectively.
REFERENCES
[1]
[2]
[3]
[4]
[5]

Nisha,C,K, Saranya.M.K, Design Of Fast Multipliers Usingvedic Mathematics , IJEECS ISSN:2347-2820,Volume-3, Issue-2 2015.
ManaswiniDehury, Anita Mohanty, SushreeSouraviKar ALU Design and Its Performance Analysis in Labview, ITSI-TEEE ISSN (PRINT): 2320-8945,
Volume-2, Issue-5, 6 2014.
K.Vinay Kumar, B.Shiva Kumar, N.V.Siva Rama Krishna.T Design of an Efficient ALU Using Low-Power Dual Mode Logic International Journal of
Engineering Research and Applications ISSN: 2248-9622, Vol.4, Issue 5(Version 4), May 2014.
K.Madan Mohan,R,NareshNaik Design of Vedic Multiplier for Digital Signal Processing Aplications IJETT-Volume 4 Issue 7- July 2013.
Honey DurgaTiwari, Chan Mo Kim, Yong Beom Cho Multiplier design based on ancient Indian Vedic Mathematics 978-1-4244-2599-0/08/$25.00 2008
IEEE 2008 International SoC Design Conference.

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