A Novel Digital Controller for Boost PFC Converter with

High Power Factor and Fast Dynamic Response

Daying Sun, Weifeng Sun, Qing Wang, Shen Xu, Shengli Lu
National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China
E-mail:hasdysun@seu.edu.cn
widely used due to its simplicity and small inductor size.

Abstract

In high power applications, continuous conduction mode

A novel digital controller for boost power factor

(CCM) is often used due to lower conduction losses and

correction converter is proposed to achieve high power

reduced EMI filtering requirements[3][4]. Digital PFC

factor and fast dynamic response. A method of direct

controller has received increased attention in PFC

duty cycle calculation is adopted to improve the power

applications recently [5][6], due to its improved

factor. The prediction module is adopted to estimate the

integration,

track of the output voltage and the inductor current of

realization of more advanced control technique.

next switching cycle in advance to improve the dynamic

Compared to peak current control or hysteresis current

response.

approximation

control, average current control is commonly used for

analog-to-digital converter (ADC) is designed to aim

boost PFC operating in CCM mode because of its higher

high resolution via little hardware resource. Meanwhile,

power factor and less sensitive to switching noise [7][8],

a novel digital pulse width modulator (DPWM) is

But the implementation of such control approach is

realized to improve the regulation linearity. The boost

complicated. Meanwhile, as is a tradeoff between the

PFC converter with proposed digital controller

based

dynamic response and the input current distortion caused

on the field programmable gate array (FPGA) has been

by output voltage ripple, the bandwidth of the voltage

implemented. Experimental results indicate that

control loop is typically 10-15 Hz.

multiplex

successive

the

programmability

and

opportunity

for

proposed digital controller can achieve high power factor

This paper presents a novel digital controller for boost

more than 0.98, the dynamic response under load

PFC converter operating in CCM to achieve high power

variation is about 80ms and the output voltage overshoot

factor and fast dynamic response. The organization of

is about 6%.

paper is as follows. The structure of digital PFC

controller system is described in Section 2, and the

Index Terms

design of digital controller is introduced in details in

Section 3. The experimental

PFC converter, digital controller, high power factor, fast

results are analyzed in

Section 4 and the conclusion is described in Section 5.

dynamic response
2.
1.

Architecture of the digital controller

Introduction
The architecture of the digital controller system for boost

Power factor correction (PFC) converters have been

PFC converter is shown in Figure l. The output voltage,

widely used in power conversions that are required to

input voltage and input current are respectively sampled

meet EN61000-3-2standard [1][2]. In low or medium

by

power applications, discontinuous conduction mode

approximation ADC, the prediction module is used to

(DCM) as well as critical conduction mode (CRM) is

estimate the track of the output voltage and the inductor

978-1-4673-6417-1/13/$31.00 2013 IEEE

the

three-time-sharing

multiplex

successive

current of next switching cycle, the direct duty cycle

system and um is equal to uoRs/Re. The formula (4) can be

calculation module is used to improve the power factor

modified through discrete operation. The digital

and simplify the control loop, the novel DPWM is

control law can been expressed as

utilized to realize the digital-to-analog conversion.

Boost PFC Converter

Vin

iL

AC

d * [ n] 1 

VO

Rs
ig [ n ]
um

(5)

L
Q

EMI
Filter

From the above formula, compared to the average

iR

iC

current control, such digital control approach omits the

Vin[t]
Vin[n]

input voltage sensing and has better immunity for the

Vo[t]

Iin[t]

variation of input voltage and electrical load.

Vo[n]

three-time-sharing multiplex successive

approximation ADC
Iin[n]

Novel
DPWM

d*[n]

direct
d[n]
duty cycle
calculation

3.2 Prediction module

PID
Compensation

e[n]
e[n]

FPAG

_
Vo[n+1]
+

Prediction
Moudle

According to the PFC circuit structure, whenever the

power system in steady-state or dynamic-state, the
relationship of voltage and current of inductance can
be described as

Vref[n]
Digital Controller

Figure l. The architecture of digital PFC controller

3.

Design of the digital controller

dI L
dt

3.1 Direct duty cycle calculation law

VL
L

The aim of power factor correction (PFC) boost

converter is to make the input average current follow the
input voltage perfectly. As shown in Figure 1, if the aim
is satisfied, the whole PFC converter system can be
equivalent to the resistance Re, and the system can be
described as

Vin  Vo
L , MOSFET is off

Vin ,
MOSFET is on
L

(6)

Where IL is the inductor current, Vin is the input

voltage, Vo is the output voltage, L is the inductance of
the boost inductor. According to (6), the output
voltage and the inductor current of the next cycle can
be derived as

component of the inductor current. For CCM boost

vin [k ]
vin [k ]  vo [k ]

(1  d )Ts
iL [k  1] iL [k ]  L dTs 
L

v [k ]
iav [k ]  o

vo [k ]
R (1  d )T




[
1]
[
]
v
k
v
k
dT
o
s
s
o
RC
C

converter, the relationship between the input voltage ug,

The average current Iav[k] can be calculated as

ug

Reig

(1)

Where ug is the input voltage and ig is the average

the output voltage uo and the duty ratio d is expressed

as

ug uo (1  d )

iav [k ]

(2)

Based on the formula above, the expression can be

derived as

Reig

uo (1  d )

Rs ig

Rs
1 (1d )T
uo (1  d ) um (1  d )
um dW ,0 d t d T (4)
Re
T 0

(3)

Where Rs is the equivalent current detection resistance of

3.3

iL [k ]  2

(7)

vin [k ]
dTs  iL [k  1]
L
4

(8)

Multiplex successive approximation ADC

A three-time-sharing

8-bits

multiplex

successive

approximation ADC is designed for digital PFC

controller. The proposed ADC has a 1.6MHz sampling

frequency and an input voltage range from 0 to 3.3V.
Charge redistribution method is employed to realize
an 8-bit DAC. To reduce the offset error of comparator,

a self-calibrating comparator is adopted. Digital

control logic circuits not only select the input channel
in turn and control the outputs of the ADC with three
shift registers, but also coordinate the work between
different modules. The architecture of analog-to-digital
converter is shown in Figure 2.

Experimental results

A boost PFC converter with the proposed digital

controller based on FPGA has been implemented. The
parameters of the boost PFC converter are listed as
follows: Vin =90-265 V, output voltage Vo=400V, output
power Po=300W, line frequency fline=50Hz, switching

Control
signal
generator

Clk

4.

frequency fs=100kHz. The proposed digital

EN_ADC

is coded

vin0

Input
selecting

vin1
vin2

S&H
And
DAC

Comp

in verilog hardware description language and

implemented on the FPGA control board.

SA
d[7:0]
Register
Control
r[7:0]
logic

vcm

controller

The input current and voltage waveforms for the full load
under the steady state are shown in Figure 4. The input
current can follow the input voltage under such condition,

Shift
register
1

Shift
register
2

Shift
register
3

Q1[7:0]

the power factor is 0.985.The proposed digital controller

Q3[7:0]

can achieve high power factor under the steady state.

Q2[7:0]

Figure 2. The architecture of proposed ADC

3.4

Vin
Iin

Novel digital pulse width modulator

The digital pulse-width modulator has the function of

converting digital signal to analog signal. A 10-bit digital

Time:10ms/div

pulse-width modulator is designed for digital PFC

controller. The architecture of digital pulse-width

Figure 4.

Measured input current and voltage waveforms for

modulator is shown in Figure 3. The delay line of the

the full load under the steady state

DPWM takes advantage of the programmable delay unit

The dynamic responses of the PFC converter with the

proposed digital controller under load variation from
50% load to full load and from full load to 50% load
are shown in Figure 5 and Figure 6 respectively. It can
be seen that the PFC converter has fast dynamic
response and small overshoot.

(PDU) .The delay-locked loop (DLL) technology is used

to eliminate the influence of process, temperature and
voltage that improve the linearity of PWM dramatically.

Digital PLL
Clk

Duty LSB [5:0]

Ring oscillator

2
26 : 1 Mux

Duty MSB[9:6]
Duty[9:0]
Comparator
4_bit
out

70ms
Vo:400V/div

26-1

Counter
4_bit
out

Comparator
4_bit
out

Time:100ms/div
Iin:5A/div

R
Q
S
dpwm_out

Figure 5. Measured output voltage and input current

Figure 3.The architecture of digital pulse-width modulator

dynamic response for load variation from 50% load to full load

Acknowledgments

80ms

Vin:400V/div

The authors

would

like

to

thank the scientific

research guidance foundation of southeast university

wuxi branch campus.
Time:100ms/div

Iin:5A/div

References
Figure 6. Measured output voltage and input current
dynamic response for load variation from full load to 50% load

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[8]

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