Chapter 2

Reliability of 3D NAND Flash Memories

A. Grossi, C. Zambelli and P. Olivo

2.1

Introduction

Reliability represents one of the major antagonist towards the unstoppable technological evolution of hyperscaled NAND memories, since the correct operations
must be assured throughout the entire lifetime. In particular, the ability of keeping
unaltered the stored information even after a consistent number of write operations
and for long times must be guaranteed.
A growth of the memory devices storage capacity without increasing the area
occupation is constantly requested by the market: in order to satisfy such requirements, an increase of the memory density and of cell shrinking is mandatory.
Nowadays, the transition from planar to three-dimensional architectures appears as
the most viable solution for the integration of non-volatile memory cells in Tera-bit
arrays. Charge Trap (CT) NAND memory cells are considered as one of the most
promising technology for 3D integration because of a better scalability than
Floating Gate (FG) NAND. Despite the high theoretical potentialities demonstrated
by CT memories, several reliability issues affect such technology. Moreover, the
transition from 2D to 3D changed the impact of the previously known reliability
issues and generated new problems. Recently, in order to overcome such problems,
new 3D vertical FG type NAND cell arrays have been proposed with promising
performances.

A. Grossi (&)
C. Zambelli
P. Olivo

Dipartimento di Ingegneria, Universit degli Studi di Ferrara, Ferrara, Italy
e-mail: alessandro.grossi@unife.it
C. Zambelli
e-mail: cristian.zambelli@unife.it
P. Olivo
e-mail: piero.olivo@unife.it
Springer Science+Business Media Dordrecht 2016
R. Micheloni (ed.), 3D Flash Memories, DOI 10.1007/978-94-017-7512-0_2

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A. Grossi et al.

In this chapter the main reliability mechanisms affecting 3D NAND memories

will be addressed, providing a comparison between 3D FG and 3D CT devices in
terms of reliability and expected performances. Starting from an analysis of basic
reliability issues related to both physical and architectural aspects affecting NAND
memories, the specic physical mechanisms impacting the reliability of 2D
CT NAND will be addressed. Then, a review of the main problems experimentally
observed in different 3D CT cell concepts is reported. Finally, 3D FG memory
concept is briefly introduced in order to understand the related reliability implications, and a comparison between 3D CT and 3D FG arrays is provided in terms of
reliability and expected performances.

2.2

NAND Flash Reliability

During its lifetime a NAND Flash module undergoes a large number of

Program/Erase (P/E) cycles. Every cycle involves very high electric elds applied to
the tunnel oxide. The reliability of the entire memory requires that the tunnel oxide is
able to correctly operate under stress conditions. It is obvious that huge efforts are to
be spent to determine the right process for the tunnel oxide creation (in terms of
thickness, material, growth, defectivity, interface, ) and the most effective algorithms in order to achieve a successful and reliable NAND technology.
In this section we will analyze the basic physical mechanisms related to the
tunnel oxide, which affect both memory endurance and data retention. Endurance
of a memory module is dened as the minimum number of P/E cycles that the
module can withstand before leading to a failure. Retention is the ability of
storing the information over time even when the external power supply is not
applied. The tunnel oxide, which is a thin oxide, may be also responsible for other
effects, such as erratic bits and over-programming, which might induce read errors.

2.2.1

Endurance

In NAND flash cells, program and erase operations rely on charge transport through
thin oxides; this is accomplished via Fowler-Nordheim (FN) tunneling into/from a
storage layer, which can be either a polysilicon FG [1] or an interfacial trapping
layer in CT technology [2, 3]. Electron tunneling is responsible for a slow, but
continuous, oxide wear out because of traps creation and interfacial damages; as a
result, there might be charge trapping/detrapping into the tunneling oxide or
undesired charge flowing into/from the storage layer.
As the number of P/E cycles increases, the above mentioned effects strongly
impact writing operations. For instance, electron trapping reduces the tunneling
efciency so that, under constant voltage and time conditions, the charge injected
into/from the storage layer decreases cycle after cycle.

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To counteract endurance effects, all writing algorithms are based on a

sequence of program/erase pulses, each one followed by a verify operation. This
sequence proceeds until the expected amount of charge is correctly transferred
into/from the storage layer. As the number of P/E cycles increases, the programming time is expected to reduce, whereas the erase time is expected to grow.
Without these write and verify algorithms (Chap. 3) it would be impossible to
control the actual amount of charge transferred into/from the storage layer and
Multi Level Cell (MLC) architectures would not exist [4].
Even if endurance is controlled by sophisticated (but slow and power consuming) algorithms, traps creation, charge trapping/detrapping, and interface damages
still degrade the tunnel oxide. As a result, it gets really problematic to retain the
stored information for extremely long times, which, at the end of the day, is a basic
requirement of the non-volatile paradigm.

2.2.2

Data Retention

As mentioned in the previous section, the ability of keeping the stored information
unaltered for a long time, i.e. the charge trapped into the storage layer, is mandatory
for non-volatile memories. However, even with no bias applied, electron after
electron, charge loss can lead to a read failure: a programmed cell can be read as
erased if its threshold voltage (VT) shifts below 0 V in case of Single-Level-Cell
(SLC), or towards a lower threshold level with respect to the initial threshold
voltage in case of MLC programming [5].
The higher the number of P/E cycles the worse the retention is, as it can be
appreciated in Fig. 2.1, which shows how the cumulative VT distributions of MLC
programmed cells changes over time. Charge loss from the storage layer moves the
VT distributions towards lower values: the rigid shift of the cumulative VT distributions is related to the oxide degradation and traps generation at the interface
between storage layer and tunnel layer. These traps may be responsible for charge
loss from the storage layer towards the silicon substrate. In fact, an empty trap,
suitably positioned within the oxide, can activate Trap Assisted Tunneling
(TAT) mechanisms characterized by a signicantly higher tunnel probability with

Fig. 2.1 Threshold voltage shifts induced by retention

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respect to a triangular barrier unmodied by the trap presence. Moreover, an

electron trapped inside the oxide during writing operations may be detrapped later
on, when the cell is read or even when the cell is not addressed. As a result, the
empty trap may enhance the TAT phenomenon (assuming a positive charged trap)
and, in addition, it can increase the electron eld at the storage layer-tunnel oxide
interface, thus raising the probability of electron tunneling. It is clear that these
mechanisms are strongly related to the oxide degradation and, therefore, data
retention gets shorter with the number of applied writing pulses. In the MLC case,
the cells programmed at higher VT are more prone to data retention issues.

2.2.3

Erratic Bits and Over-Programming

The Fowler-Nordheim (FN) tunneling mechanism for writing and erasing data in
NAND Flash has been used for several decades, demonstrating a sufcient level of
reliability.
Nevertheless, it has been found that anomalous FN tunneling currents can occur
in random periods of time, thus leading to signicant variations of the threshold
voltage after the writing operation [6] (see Fig. 2.2). This phenomenon is known as
erratic bits.
In a NAND array, the presence of this phenomenon is detrimental for the performances of the memory as the unpredictable increase of the cells threshold
voltage may eventually induce the over-programming issue. As shown in Fig. 2.3,
conductive cells featuring relatively large threshold voltage are erroneously read as

Fig. 2.2 Example of erratic behaviors in four flash cells. Cells threshold voltage VT plotted versus
the number of cycles exhibits RTN [6]

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Fig. 2.3 Effect of an

over-programmed cell in a
NAND flash string. In normal
conditions the status of the
cell to be read (supposed to be
ON) is correctly detected,
since all other cells are driven
by a VPASS so that they
behave as ON pass transistors.
In the presence of an
over-programmed cell
(VT > VPASS), the current
flow through the string is
inhibited and the absence of
current is attributed to a
programmed status of the cell
to be read, thus producing a
read error [6]

OFF if over-programmed, and they can electrically isolate the NAND string. Such
behavior generates read errors and consequent read throughput loss due to the
additional work done by the Error Correcting Codes (ECC) trying to repair the
failed bits.
Since erratic behaviors are intimately related to the electron tunneling mechanism, they can potentially affect all the cells of an array [6].
Anomalous tunneling has been related to the presence/absence of a cluster of
positive charges in the tunnel oxide that strongly affects the FN tunneling operation.
As a rst approximation, erratic behaviors can, therefore, be described in terms of a
two level Random Telegraph Noise (RTN) affecting the threshold voltage during
cycling, in which the normal and the anomalous threshold voltage levels are the
result of the presence of a cluster of more than 2, or less than 3, positive charges in
the tunnel oxide, respectively [7, 8].

2.3

Architecture Dependent Reliability Issues

Architectural solutions for memory operations may also affect the overall reliability,
by inducing errors and even cell failures [1]. The most common effects are the so
called disturbs, that can be interpreted as the influence of an operation performed
on a cell (Read or Write) on the charge content of a different cell.
Read disturbs are the most frequent source of disturbs in NAND architectures.
This kind of disturb may occur when reading many times the same cell without any

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Fig. 2.4 Representation of

read disturb in a NAND flash
array. The cells potentially
affected by read disturb are
marked in gray

erase operation. All the cells belonging to the same string of the cell to be read must
be ON, independently of their stored charge. The relatively high VPASS applied to
the control gate may induce a charge increase, especially if the read operation is
repeated many times. These cells suffer a positive shift of their threshold voltage,
which may lead to read errors. Figure 2.4 shows the typical read disturb conguration. As a matter of example, a 64 cell string is considered in the following,
however the reported considerations can be extended to longer strings as well.
The probability of suffering from read disturb increases with the number of P/E
cycles (i.e. towards the end of the memory useful lifetime) and it is higher in
damaged cells. Read disturb does not cause permanent oxide damages: it can be
reset by a simple erase operation.
In case of MLC programming, cells with lower VT are slightly more vulnerable
to shift than cells with higher VT (see Fig. 2.5). In fact, the lower the threshold
voltage the higher the voltage difference (VPASS VT) across the tunnel oxide,
which translates in a higher tunneling current. For cells in the erased state (ER) we
observe a systematic shift of the cells VTH to the right (i.e. to higher values). The
shift for P1 and P2 is much lower, since the read disturb effect becomes less
prominent as VT increases. For cells in P3, on the contrary, the average VT shifts to
the left. This is mainly due to charge loss (retention), which outweighs read disturb.
Two other important types of disturbs arise during the write operation: Pass
disturb and Program disturb, which are shown in Fig. 2.6 (left and right),
respectively. The former is similar to the read disturb and affects cells belonging to
the same string of a cell to be programmed. With respect to the read disturb, the
Pass disturb is characterized by a higher VPASS voltage applied to cells that are not

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Fig. 2.5 Threshold voltage shift induced by read disturb

Fig. 2.6 Representation of pass disturb (left) and program disturb (right) in a NAND flash array.
The cells potentially affected by disturbs are marked in gray

to be programmed (thus enhancing the electric eld applied to the tunnel oxides and
the probability of undesired charge transfer). On the other hand, the pass disturb can
be repeated for a limited number of times (i.e. the number of cells in the string
minus 1). In fact, when a string (block) has been fully programmed, an erase
operation must be necessarily performed before any other reprogram.
The Program disturb, on the contrary, affects cells that are not to be programmed
and belong to the same wordline of those that are to be programmed. In this case,
again, no cumulative effects are present.
Edge Wordline disturbs affect the cells belonging to the rst and last wordline,
which connect the cell strings to the string selectors [9]. This disturb is due to a
difference between the VT of the cells belonging to WL0 and WL63 with respect to
the average VT of all other cells. Such difference can be ascribed to three effects:
different potentials at their terminals with respect to the other cells depending on
the specic WL selected for programming;
a different cell geometry due to the fact that these cells are located between a cell
and a transistor (differently from cells belonging to WL1WL62), therefore with a
different eld underneath their channels and a modied programming dynamics;

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a different cell lithography, especially when extremely scaled technology nodes

are considered;
the presence of a large Gate Induced Drain Leakage (GIDL) [10] current
generated at the drain edge of DSL/SSL transistors due to their drain potential
raised by channel boosting: such a eld can efciently trigger electron-hole pair
generations followed by an acceleration of the electrons toward the channel of
WL0 and WL63 cells. These electrons can be injected into the floating gate of
these cells, thus provoking an undesired increase of their threshold voltages.
In order to overcome such problem, the most common solution is to introduce
two or more dummy WL before WL0 and after WL63, shielding the Edge Wordline
Disturb: in such a way, the difference between the edge cells and all other cells in
terms of potential at their terminals and cell geometry is minimized.

2.4

2D Charge Trap: Basics

The basic concept of a CT NAND memory cell consists of a metal oxide semiconductor device where the FG is replaced by an insulating charge trapping layer. Such
storage layer, typically made of silicon nitride, is isolated by means of a tunnel oxide
and a blocking oxide as sketched in Fig. 2.7 where the FG cell structure is reported for
comparison. The tunnel oxide plays a basic role for the control of the device threshold
voltage, whose value represents, from a physical point of view, the stored information. The blocking oxide prevents electrons from passing to/from the control gate.
Electrons transferred into the storage layer give a threshold voltage variation. In
quiescent conditions, thanks to the two oxides, the stored charge is supposed not to
leak away, thus granting the nonvolatile paradigm fulllment. Oxides are available in
different materials depending on the Back-End-Of-Line (BEOL) process. The most
common materials are: pure silicon dioxide (SiO2) for blocking oxides, and either
SiO2 or a barrier engineered stack of Oxide-Nitride-Oxide (SiO2-Si3N4-SiO2) for
tunnel oxides. A 2D planar Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) cell is
used as an example in this section [3].

Fig. 2.7 Left Example of a charge trap device. Right Example of floating gate device

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Fig. 2.8 Band diagrams of tunneling mechanisms in planar SONOS CT cell during programming
(left) and erase (right). The two different conditions triggering FN or DT are sketched for
programming [3]

High electric elds applied to the tunnel oxide allow electron transfer across the
thin insulator to the storage layer. The physical mechanism used for injecting
electrons into the storage layer depends on the applied electric eld and oxide
barrier thickness. In case of high electric elds and large oxide barriers, injection
mainly occurs through FN tunneling, whereas in case of low electric eld and thin
oxide barrier, electrons mainly transfer through Direct Tunneling (DT): in this case
there is a higher read margin window but retention is worse [3]. In CT cells electron
tunneling involves the MOS channel/substrate and it requires appropriate biasing of
control gate and bulk terminals (see Fig. 2.8), while drain and source are left
floating. Erase operation occurs either through electron detrapping from the storage
layer or hole injection from the substrate into the storage layer; at the same time,
such operation causes an electron injection from the control gate to the storage layer
through FN tunneling, and this is the reason for the well-known erase saturation
problem [11]. The results of charge separation experiments [12] demonstrate that
both electron detrapping and holes injection mechanisms contribute to the erase of a
previously programmed CT device: electron detrapping dominates the rst part of
the transient, whereas hole injection prevails after the removal of the trapped
electron charge due to electron emission.

2.5

2D Charge Trap: Reliability Issues

Despite the huge potential, several reliability issues affect CT memories, especially
endurance and retention.

2.5.1

Endurance Degradation

The band diagram depicted in Fig. 2.9 describes oxide degradation mechanisms for
blocking and tunnel layers. During programming operations (left), electron

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A. Grossi et al.

Fig. 2.9 Band diagram sketch of charge transport and trapping/detrapping during program (left)
and erase (right) in planar SONOS CT cell [3]

injection occurs through either FN or DT, damaging the Tunnel Layer; damages to
the Blocking Layer are caused by Anode Hot Hole Injection (AHHI). Moreover,
electrons and holes going through blocking layer and tunnel layer from the storage
layer contribute in a marginal, but not negligible, way to oxide degradation. During
erasing (right), the hot hole injection from the substrate generates interface traps at
the oxide/nitride interface, causing several damages to both storage and tunnel
layers, as well as electrons transfer through the tunnel layer [11]. The generation of
such interface traps between oxide and nitride interface is the main cause of
endurance degradation: in programmed cells, electrons sitting in shallow traps can
easily escape via oxide damages induced by cycling, resulting in a charge reduction
that may cause read errors.

2.5.2

Data Retention

Data retention is one of the major issues of CT cells, especially at high temperature.
Charge loss mechanisms of CT cells has been deeply investigated [13], identifying
two main discharging paths: the rst is related to thermal excitation of trapped
carriers, the second one is due to direct tunneling through the thin tunnel oxide.
The charge loss processes are schematically depicted in Fig. 2.10. For each
electron trapped inside the silicon nitride, two discharge mechanisms have to be
considered. The rst one is the direct Trap-to-Band (TB) tunneling from the storage
layer traps to the conduction band of the substrate or of the gate; the second one is
the thermal emission from traps to the conduction band of the storage layer.

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39

Fig. 2.10 Mechanisms involved in the discharging of programmed planar SONOS CT cell:
trap-to-band tunneling through the tunnel layer, trap-to-band tunneling through the blocking layer,
thermal emission above the oxide barriers, thermal emission and subsequent retrapping [13]

When thermal emission is considered, the charge loss is the result of two subsequent steps: the emission process and the escape of the electrons towards the bulk
and gate electrodes. After emission, retrapping is also possible: the tunneling rate
through the oxide barrier of the electrons emitted in the storage layer conduction
band could be comparable with the emission and the recapture rates. Here we
consider a simplied model where electrons leave the ONO layer only if their
energy is higher than the lowest between the tunnel oxide and the top oxide barriers.
Consequently, the tunneling of thermally excited carriers towards the bulk and the
control gate at energies lower than the oxide conduction band are neglected,
assuming that carriers with such an energy are recaptured in the same traps.
In additions, a fast initial charge loss has been observed on a small percentage of
cells [14] (see Fig. 2.11). This VT transient phenomenon has been attributed to the
dielectric relaxation effect in the high-k layer, to charge trapping/detrapping, or to
mobile charges in the blocking layer [14]. Such mechanism, denoted as fast
detrapping, is mainly related to electrons trapped in shallow traps which have lower
stability than electrons in deep traps; they can easily escape via oxide damages
within 1 s after programming.

Fig. 2.11 Threshold voltage shift induced by fast detrapping (left). Band diagram sketch of fast
detrapping effect (right) [14]

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The same effect is observed after erase too: since the threshold voltage after
program/erase does not immediately settle to the nal value, there is a wrong
estimation of the error bits during the verication step; of course, there is a
dependency from the time interval between program/erase and read operations.
Waiting for the nal VTH would signicantly increase the total program/erase time
and, of course, this is not acceptable. The transient threshold voltage shift after
erase is due to hole re-distribution in the charge trap layer [15].

2.5.3

Threshold Voltage Shift During Sensing

Sensing the cells threshold voltage during retention has been identied as one of
the main reliability issues of CT cells [16]. This VT decrease can be understood
within the process of the temperature-activated charge transport through the
blocking layer. The charge loss can be minimized when VT sensing time is
decreased down to microseconds. Moreover, blocking oxides engineered by adding
a thin SiO2 layer at the trapping layer/blocking oxide interface exhibit signicant
suppression of charge loss. Experimental data show that, for identically programmed devices, charge loss rate signicantly increases when the VT sensing
operation is repeated more frequently. Furthermore, a similar amount of charge loss
is observed when the cumulative sensing time is the same (same numbers of sensing
measurementsdashed line in Fig. 2.12). These results indicate that charge loss
might be strongly affected by the VT sensing operation as well as retention time.
The charge loss dependency from the VT sensing time was evaluated by varying the
sensing time from microseconds to few seconds. Shorter VT sensing time is seen to
minimize the initial charge loss and signicantly reduce charge loss rate.

Fig. 2.12 Left Retention charge loss as measured by the VT shift from the programmed VT value
(read window MW = 6 V) for different DC VT sensing frequencies (VT sensing time = 3 s). Right
Programmed VT dependency on retention time (retention charge loss) for various VT sensing times
[16]

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2.6

41

From 2D to 3D Charge Trap NAND

Three-dimensional architectures appear today as the most viable solutions for the
integration of non-volatile memory cells in Tera-bit arrays [1719]. Two different
approaches are possible in order to obtain 3D NAND devices (see Fig. 2.13): the
rst and simplest is to build the cell on a thin polysilicon substrate as usually done
in 2D planar arrays, and stack more levels (Chap. 3) [20]. The second and most
interesting approach, dened as vertical channel, is to build a CT cell with a
cylindrical channel [17]. Both architectures have a physically large cell size
(indicated with the feature process size Fprocess), mainly due to a channel width
wider than planar devices, although offering a smaller equivalent area occupation
due to the stacking of multiple tiers [21, 22]. The former solution does not offer any
advantage over conventional planar CT cells in terms of P/E and retention, whereas
the latter allows improving the cells programming performance, compared to planar
devices, thanks to the shape of the CT cell, also known as Gate-All-Around (GAA)
[23, 24]. Nevertheless, 3D NAND memories face new reliability issues because of
the cylindrical shape and the multi-layer stacking. To understand these new reliability problems, basic concepts of 3D NAND cells are briefly introduced in this
section; for more details about each single 3D architecture please refer to Chaps. 4,
5, 6, and 7. In the following sections, the reliability issues affecting 3D devices will
be discussed by reviewing the main problems experimentally observed in different
3D NAND arrays [20, 21].
The cross section diagram along a single WL plane of the 3D vertical channel
NAND reported in Fig. 2.13 (left) is shown in Fig. 2.14. It is worth highlighting
that a String-Select-Line (SSL) group is equivalent to a 2D planar flash memory cell
array. The 3D vertical flash memory has a nitride layer inside an Oxide-NitrideOxide (ONO) stack, which acts as a CT layer along the circumference of the thin
poly-silicon vertical channel. Please note that each CT cell in this 3D vertical
NAND memory is surrounded by the metal gates [24].
The GAA-CT cell is considered one of the most promising solution for 3D
integration [25]. This is due to the curvature effect that relaxes the erase saturation
problem: the electric eld in the blocking oxide is lower than the one in the tunnel

Fig. 2.13 3D NAND vertical

(left) and horizontal channel
(right) architectures with the
corresponding feature process
size Fprocess [21]

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A. Grossi et al.

Fig. 2.14 Horizontal section of 3D vertical flash memory cell array [24]

oxide, allowing to increase the electrons detrapping from nitride traps towards the
substrate. Moreover, thanks to the reduction of corner and fringing eld effects
during program, erase and read, GAA-CT cells allow more uniform trapped charge
distributions in the storage layer and provide, in turn, steeper incremental step pulse
programming (ISPP) transients than planar cells [26].
Figure 2.15 (left) shows a comparison between the GAA-CT cell (solid) and the
planar CT cell (dashed), given the same thickness of gate dielectrics, in case of
programming operation at VG = 12 V with neutral nitride. The energy band prole

Fig. 2.15 Comparison between a GAA-CT cell and a planar CT cell having the same thickness of
the gate dielectrics in terms of energy-band prole (left) and electric eld (right) during program,
for VG = 12 V and neutral nitride [27]

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43

Fig. 2.16 Comparison between a GAA-CT cell and a planar CT cell having the same thickness of
the gate dielectrics in terms of energy-band prole (left) and electric eld (right) during erase, for
VG = 12 V and neutral nitride [27]

clearly shows a reduction of the thickness of the energy barrier which prevents
electron tunneling from the substrate to the nitride. Compared to the planar case, the
electric eld inside GAA-CT dielectrics is not constant, showing a maximum value
at the substrate/tunnel oxide interface. This maximum value is about three times
larger than the electric eld in the tunnel oxide of the planar device: of course, this
is a strong improvement for the programming dynamics [27]. In addition to that, the
electric eld in the GAA-CT blocking oxide is lower than in the planar case, thus
resulting in a reduced electron leakage from the nitride to the gate during programming (see Fig. 2.15 right).
A comparison between GAA-CT and planar cell during erase at VG = 12 V is
shown in Fig. 2.16. As for positive VG, in the case of GAA-CT the electric eld
reaches a maximum at the substrate/tunnel oxide interface, and it is quite larger than
the electric eld present in the planar device (right). This behavior enhances the
hole tunneling current from the substrate to the nitride during erase. In addition, the
lower electric eld at the gate/blocking oxide interface prevents electron injection
from the gate, thus relieving the erase saturation issues [27].

2.7

3D Charge Trap: Reliability Issues

Even if the transition from 2D to 3D devices can leverage the advantages of the ring
shape stack of the memory cell, all the reliability issues affecting planar devices (i.e.
endurance, retention and read disturbs) are still there. On top of that, there are new
reliability challenges due to vertical charge loss (i.e. through Top/Bottom oxides)
and lateral charge migration (i.e. towards spacers). In case of 3D CT arrays the
causes are ascribed to either uneven electrical eld distribution in Bottom Oxide
(BTO), equivalent to the blocking oxide in 2D CT, and Top Oxide (TPO), equivalent to the tunnel oxide in 2D CT, due to the cylindrical geometry (see Fig. 2.17).

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Fig. 2.17 Top birds eye

view of 3D CT memory.
Bottom 3D CT-NAND string
with one cell and two select
transistors and schematic
diagram of the charge loss
paths [28]

As a result, charge loss in 3D memories is worse than what we have seen with
planar devices, and this is considered the most critical reliability issue for high
density and high reliability 3D integration [28]. In this section, physical mechanisms related to the vertical structure of the memory devices, such as vertical charge
loss and lateral charge migration, will be described.

2.7.1

Vertical Charge Loss Through Top and Bottom

Oxides

A constraint for the 3D vertical arrays, not present in planar devices, is that the
charge-trap layer cannot be easily interrupted between layers. This fact creates
additional leakage paths for the charge, from each cells active area towards other
cells on the same string, as schematically illustrated in Fig. 2.18. In addition to
vertical charge loss through Top and Bottom oxides (along Y axis), lateral charge
leakage (along X axis) represents an extra source of retention loss for cells in 3D
vertical arrays, which should be carefully considered for the reliability assessment
of the technology [29].
The involved physical mechanisms accounting for charge distribution evolution
during time, along X and Y axes, are illustrated in Fig. 2.19. Charge transport in the
conduction band of the charge trapping layer is described based on the drift-diffusion
transport scheme. The interaction between free carriers and trapped carriers is governed by the carrier capture phenomenon calculated by Shockley-Read-Hall

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45

Fig. 2.18 3D CT-NAND structure and charge loss along X and Y axes [29]

Fig. 2.19 Dominant physical mechanisms along X (left) and Y (right) axes: 1-DT/FN Tunneling,
2 and 3-carrier capture and emission, 4-drift and diffusion transport, 5-TB tunneling [27]

(SRH) theory, and carrier emission contributed by thermal and Poole-Frenkel effects.
Besides, Band-to-Trap (BT) tunneling and Trap-to-Band emission should be taken
into account as additional charge capture and loss mechanisms.
Figure 2.20 shows the simulated Remaining Charge Percentage (RCP), dened
as the percentage of the initial charge which remains inside the storage layer, during
Fig. 2.20 Simulated vertical
loss transients. The inset
shows the schematic diagram
of device structure and the
cross-sectional schematic of
charge loss paths [28]

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Fig. 2.21 a RCP of cylindrical and planar devices, with insets showing the schematic band
diagram under positive and negative bias. b Conduction band diagram of cylindrical and planar
devices at VG = 0 V [28]

vertical charge loss transients [28]. The charge loss characteristics strongly depends
on the temperature, which can be explained by enhanced Poole Frenkel emission
from trap to conduction band at elevated temperature.
In order to distinguish the role of charge loss through BTO and charge loss
through TPO, the RCP under different gate bias is given in Fig. 2.21 (left); in
addition, the RCP under different stresses of planar device with identical structure
parameters is also plotted as reference. As shown in the energy band diagram, the
charge loss through BTO occurs under negative bias while charge loss through TPO
dominates with positive bias. Compared to the planar device, charge loss towards
TPO is higher and charge loss from BTO is lower in cylindrical devices. This can
be explained by the conduction band diagram of Fig. 2.21 (right). Due to the
uneven distribution of the electric eld in BTO and TPO, the conduction band
graphs of the cylindrical device are not straight any longer, but convex in BTO and
concave in TPO. As a result, charge loss through BTO is slightly reduced [28].

2.7.2

Lateral Migration Towards Spacers

Lateral charge migration towards the spacer (i.e. the region between each layer)
region (along X axis, referring to Fig. 2.18) is another key path for the charge loss
due to the difculty of cutting the CT layer between memory cells. Different shapes
of the CT layer exhibit different lateral migration performances. To analyze this
shape dependency, Bit Cost Scalable (BiCS)-type structures and Terabit Cell Array
Transistor (TCAT)-type structures have been studied [28]; more details about both
arrays can be found in Chap. 4. In order to focus on lateral migration performance,
the cells were programmed to the same threshold voltage (6 V). Lateral migration is
accelerated by temperature (Fig. 2.22). The considerable threshold voltage loss

2 Reliability of 3D NAND Flash Memories

47

Fig. 2.22 Comparison

between TCAT-type and
BiCS-type devices [28]

caused by the lateral migration indicates that carriers in the nitride signicantly
migrate laterally. Figure 2.23a shows the distribution of trapped carriers versus
elapsed time in TCAT-type and BiCS-type devices: lateral migration of trapped
charges can clearly be observed as time proceeds. TCAT-type devices show better
retention characteristics. Shape dependency of lateral migration can be explained by
the lateral charge prole evolution shown in Fig. 2.23b: the corner of TCAT-type
devices suppresses the migration of trapped charges, which can be described in
device-level simulations not only by the higher charge density along the channel
direction, but also by the sharp peak at the corner of the CT layer.

Fig. 2.23 a Simulated

trapped charge distribution at
different elapsed time and
T = 85 C. b Simulated
lateral charge prole
evolution (cutline at middle of
CT layer along the channel)
[28]

48

A. Grossi et al.

Fig. 2.24 Split of threshold voltage change by vertical loss and lateral migration versus time (left)
and versus channel length (right) for TCAT devices [28]

Based on the above discussion, the impact of vertical loss and lateral migration
in retention has been compared for TCAT and summarized in Fig. 2.24 (left). It can
be seen that lateral migration is the dominant charge loss mechanism. The charge
loss behavior with different channel length is shown in Fig. 2.24 (right). As the
channel length reduces, lateral migration accounts for a larger percentage of charge
loss, which indicates that lateral migration should be a more critical issue than
vertical loss in high-density and high-reliability design of 3D GAA-CT memories.

2.7.3

Transient VT Shift

Transient VT shift after erase, previously described for 2D cells (Sect. 2.5.2), is
observed on 3D devices too. In the GAA-CT cell, a smaller diameter of silicon
nanowire shows a better erase efciency due to the electric eld concentration effect
on the tunnel oxide (Fig. 2.25, left). However, the GAA-CT device also shows a
transient VT shift after erase: the amount of VT shift is related to the amount of read
window (dened as the voltage difference between the programmed and erased
states in case of SLC architectures, or between two adjacent levels in case of MLC
architectures) and the VT shift in GAA-CT is well correlated to that in planar CT
devices (Fig. 2.25, right), thus implying the same mechanism. It is worthwhile
noting that the transient VT shift can be reduced by scaling the channel length (LG)
and the diameter of the silicon nanowire (WNW) in GAA-CT, probably due to a
compensation effect by charge crowding and lateral charge spreading. As shown in
Fig. 2.26, when the diameter of nanowire goes below 6 nm, the tendency of the
drain current ID to increase with time disappears. Therefore, 3D GAA-CT device
with small nanowire diameter shows advantages in fast erase operation [15].

2 Reliability of 3D NAND Flash Memories

49

Fig. 2.25 Left Erased saturation voltage versus WNW in GAA-CT device. A smaller WNW shows
a better erase efciency due to the electric eld concentration effect on the tunnel oxide. Right
Correlation of VT window and VT shift after erase operation. The VT shift in GAA-CT is well
correlated to that in planar CT devices, implying the same mechanism for the transient VT shift
[15]

2.7.4

Program and Pass Disturbs

All kinds of 3D NAND suffer from two program disturbs. Besides the traditional
program and pass disturbs affecting 2D architectures (see Fig. 2.6), in 3D NAND
also the disturbs related to the vertical structure are to be taken into account.

2.7.5

Vertical Hole Design Limitations

Since scaling and design of 3D NAND are completely different from planar NAND,
and with different implications on the memory reliability, new methodologies are

Fig. 2.26 Transient ID of GAA-CT devices with different LG (a) and WNW (b). Transient VT shift
becomes smaller when LG and the WNW are scaled. ID fluctuations in GAA-CT may be due to
single electron effects or random telegraph noise [15]

50

A. Grossi et al.

Fig. 2.27 Cross sectional view of 3D NAND [30]

required. One of the problems of 3D NAND is the reduced cells density per single
memory layer. As a matter of example, Fig. 2.27 shows the simplied cross sectional view of the Bit-Cost Scalable (BiCS) type 3D NAND. The BiCS hole must
be lled with ONO lm (*20 nm) and silicon channel. Since it is not possible to
aggressively scale the ONO lm because of read window and reliability, the
diameter of the BiCS hole is not so scalable. Therefore, the number of stacked
layers (Nlayer) should be increased to compensate this drawback. Moreover, as
shown in Fig. 2.27, there is an additional limitation due to the nite taper angle in
the BiCS hole: the memory cell at the top of the stack is always larger than the cell
at the bottom. In other words, once the bottom of the stack reaches the minimum
cells size of a specic technology, then the area cant be shrunk anymore. On the
other hand, since the minimal line and space lithography pattern are not required for
the control gate (CG) formation in 3D NAND, CG length Lg and spacing Lspace can
be independently chosen. This design flexibility is allowed for 3D NAND.
Therefore, suitable device design for 3D NAND can be explored in terms of Lg and
Lspace. Programming and disturbance characteristics are evaluated for the memory
operation, as shown in next sections [30].

2.7.5.1

VT Shift Induced by Stored Electrons During Programming

Given a specic electron density in the nitride layer, 3D and 2D cells can be
compared in terms of the resulting VT shift of the programmed cell, as shown in
Fig. 2.28 [30]. Lg and Lspace should not be too small and too large, respectively.
The smallest shift is observed at Lg = 10 nm and Lspace = 50 nm. When Lspace is
large, the spacing region determines the VT of the cell. Therefore, the effect of the
stored electrons on VT relatively decreases for large Lspace and the corresponding
read window decreases. Large Lg shows high VT shift because the potential of the
center region of the channel in the target cell is mainly controlled by the stored
electrons.

2 Reliability of 3D NAND Flash Memories

51

Fig. 2.28 VT shift of the programmed cell (corresponding to read window) as a function of Lg and
Lspace when electrons (electron density: 1 1019 cm3) are stored in 3D NAND (a) and planar
NAND (b) [30]

2.7.5.2

VT Shift Induced by Neighboring Cells

VT shift induced by the electrons stored in the neighboring cell was investigated as
shown in Fig. 2.29 [30]. As Lg and Lspace decrease below 2030 nm, VT shift due
to the neighboring cell drastically increases in both 3D and planar NAND. When
Lspace is small, stored electrons couple with the channel of the target cell. This is
severe when Lg is small because stored electrons potential can affect the entire
channel region of the target cell. Moreover, at small Lg and Lspace, the VT shift
degradation in 3D NAND is higher than in planar NAND. The substrate-channel
coupling in planar NAND reduces the VT shift by because of the coupling between
the channel and stored electrons.

Fig. 2.29 Vth shift as a function of Lg and Lspace when electrons (electron density: 1 1019 cm3)
are stored in the neighboring cell in 3D NAND (a) and planar NAND (b) [30]

52

2.7.5.3

A. Grossi et al.

Electric Field in the Tunnel Oxide During Programming

Evaluations of the electric eld in the tunnel oxide during the programming has
been performed [30]: Fig. 2.30 plots the electric eld of the tunnel oxide in the
channel (NAND string) direction. The gure shows that the electric eld spreads
out in the lateral direction (fringing electric eld exists). If Lg is small, the tunnel
oxide electric eld cannot concentrate at the center of the CG of the programmed
cell. Therefore, the electric eld in the tunnel oxide of the programmed cell
(Eox_pgm) decreases at small Lg. If Lspace is small, then the electric eld penetrates
into the neighboring cells; however, if Lg is large, the penetration is only at the edge
of the cell. Therefore, the electric eld at the center of the CG remains low for the
neighboring cells (low Eox_ngb).

Fig. 2.30 Electric eld of the tunnel oxide in the channel direction. 3D NAND string with:
Lg = 10 nm and Lspace = 10 nm (a), Lg = 10 nm and Lspace = 50 nm (b), Lg = 50 nm and
Lspace = 10 nm (c) [30]

2 Reliability of 3D NAND Flash Memories

53

Fig. 2.31 Lg and Lspace design window for 3D NAND (a) and planar NAND (b) [30]

2.7.5.4

Design Window of LG and LSPACE

Figure 2.31 shows the design window of Lg and Lspace for 3D (a) and planar
(b) NAND [30]. The criteria for unacceptable regions (shaded regions in Fig. 2.31)
are assumed as follows; VT roll-off < 3 V, Subthreshold Slope (S.
S.) > 300 mV/dec, VT shift < 2 V in the programmed cell, VT shift > 0.6 V by the
neighboring cell and Eox_ngb/Eox_pgm > 0.6. Lg = Lspace = 20 nm (layer pitch of
40 nm) is achievable in 3D NAND in terms of the electrical characteristics. Same
Lg and Lspace are preferable to cope with the tradeoff between the large VT shift for
the programmed cell and the small VT shift induced by the neighboring cell. For
further improvements, the diameter of the BiCS hole should be decreased.
Table 2.1 summarizes the comparison between 3D and 2D: 3D NAND achieves
very good on-current (Ion), S.S. and low program voltage (Vpgm) compared to
planar NAND. Slight degradations in VT roll-off and VT shift caused by the stored
electrons in the neighboring cell are observed only at the small Lg and Lspace region.

2.8

3D CT Versus State-of-the-Art 2D FG

In this section, a comparison between a particular 3D CT NAND (denoted as

Stacked Memory Array TransistorSMArT [31], depicted if Fig. 2.32) and
state-of-the-art 2D FG is reported, in terms of both performances and reliability.
A detailed description of 2D FG reliability problems is provided in [1].
VT distribution widths of MLC 3D CT cells are *30 % smaller compared to the
2y-nm FG, because of their interference free nature (Fig. 2.33, left). The widening
of cells VT distributions during cycling is compared in Fig. 2.33 (right), where

54

A. Grossi et al.

Table 2.1 Summary of 3D NAND cells [30]

Planar
NAND
3D NAND

Preferable
scaling
parameter

Ion

Vth
roll-off

S.S.

Vth shift
(programmed
cell)

Vth shift
(neighboring
cell)

Tunnel
oxide
electric
eld
(Eox_ngb/
Eox_pgm)

Vpgm

Poor

Fair

Poor

Fair

Fair

Fair

20 V

Very
good

Poor at
small
Lg,
Lspace

Very
good

Fair

Good at large Lg and

Lspace, poor at small
Lg and Lspace

Fair

17 V

Lspace

Lg

Lspace

Lspace

Fig. 2.32 SMArT cell

schematic [31]

SMArT cells show no widening up to 5k cycles, whereas FG cells start broadening

from 3k [31].
On the other hand, 3D CT have worst retention performances as shown in
Fig. 2.34, where the post cycling VT shifts at high temperature are compared. In 3D
CT cells the VT shifts are so large that the distributions are no longer separated [31].

2 Reliability of 3D NAND Flash Memories

55

Fig. 2.33 Left Comparison of cells VT distributions of 2y node FG and SMArT cells. Right
Comparison of VT widening during program-erase cycling [31]

Fig. 2.34 Cells VT distributions of HT retention after cycling of 2y node FG (left) and SMArT
cells (right) [31]

2.9

3D-FG Nand

Recently, 3D vertical FG type NAND cell arrays have been proposed to overcome
the retention and overall reliability issues of 3D CT NAND cell arrays [3236]. In
this section, an overview of the proposed 3D FG cells and their main reliability
problems is reported. Figure 2.35 shows the birds-eye view of published 3D
vertical FG type NAND cells structures: Extended Sidewall Control Gate (ESCG)
[32], Dual Control-gate with Surrounding Floating-gate (DC-SF) [33, 34], and
Separated-Sidewall Control Gate (S-SCG) cells [35].
ESCG and DC-SF cells suffer from interference and disturbance problems when
integrated into an array due to the direct coupling effect of neighboring cells in the
same string. S-SCG overcomes such a problem, strongly reducing interference and
disturbance effects. In the S-SCG structure, the Source/Drain (S/D) region can be
implemented by electrically inverting the pillar surface, and high CG coupling
capacitance can be achieved. S-SCG structure allows obtaining highly reliable

56

A. Grossi et al.

Fig. 2.35 Birds eye views

of the most recent 3-D vertical
FG type NAND cell schemes:
ESCG (top), DC-SF (middle)
and S-SCG (bottom) [35]

MLC operation, high speed P/E operation and good read current margin. More
details about these architectures can be found in Chap. 5.

2.9.1

DC-SF Interference and Retention Results

The interference between a programmed cell and an adjacent cell in case of 3D-FG
NAND array with DC-SF cells was studied as shown in Fig. 2.36 (left) [33].

2 Reliability of 3D NAND Flash Memories

57

Fig. 2.36 Left FG-FG interference characteristics (VT variation in the adjacent cell as a function
of VT in the programmed cell). Very small FG-FG coupling value of 12 mV is obtained. Right
Data retention characteristics of the DC-SF NAND flash cells [33]

Negligible VT shift of adjacent cell (12 mV) was obtained as the VT of programmed
cell is increased by 3.6 V, suggesting that each CG acts as shielding layer in a
string. The data retention characteristics of DC-SF cells at two different temperatures (90 and 150 C) are reported in Fig. 2.36 (right), showing the increase of
charge loss with temperature. In case of high temperature condition, a program and
erase VT shift due to charge-loss of 0.9 and 0.2 V after a retention time of 126 h is
shown, respectively.

2.9.2

S-SCG Interference Results

In 3D FG NAND arrays with S-SCG cells two critical interference coupling paths
exist: the former is the indirect coupling path while the latter is direct. Figure 2.37
shows the interference effects as a function of the S-SCG initial VT. The S-SCG
structure can sufciently suppress the indirect interference effect; however, the
direct coupling from neighboring FG to the channel of S-SCG remains a very
serious problem. ESCG and DC-SF cells have remarkable interference problems by
this direct coupling effect as well, which directly influences the parasitic transistor
below the S-SCG. To suppress this direct coupling effect, S-SCG cell applies the
SCG voltage to control the parasitic transistor [35].

2.9.3

S-SCG Performance and Reliability Advantages

The S-SCG cell strongly reduces both the interference effect and the disturbance
problem with good performance, and it has good potentials of highly reliable MLC
operation. Moreover, lower operation voltages than conventional 3D CT is

58

A. Grossi et al.

Fig. 2.37 Interference effect in 3-D vertical FG NAND cells (left) and cross sectional view of
interference coupling paths of the conventional ESCG cell array (right) [35]
Fig. 2.38 The effective cell
size of S-SCG cell in
comparison with other 3-D
vertical NAND cells at 20 nm
technology [35]

required: this implies that cell operation is more effective because of higher coupling ratio. The vertical cell height is decreased compared to that of the conventional FG cell by using a predeposited SCG layer. Figure 2.38 shows the effective
cell size with 3D vertical NAND cell schemes at 20 nm technology. Although the
Table 2.2 3D NAND cells comparison summary [35]

2 Reliability of 3D NAND Flash Memories

59

cell size of the proposed S-SCG cell is larger than that of CT type NAND cell by
about 60 %, the possibility of implementing MLC operation allows obtaining lower
bit costs. Less than half of the bit cost can be achieved by implementing TLC
operation to the proposed S-SCG cell. Finally, we show the MLC feasibility and the
number of stacked cells in comparison with conventional 3D cells in Table 2.2 [35].

2.10

3D-CT Versus 3D-FG

In this section a nal comparison between 3D CT and 3D FG in terms of performance and reliability is reported. For the comparison of the structures, vertical
schematic of the conventional 3D CT structure and 3D FG cell are shown in
Fig. 2.39 [34]. Unlike planar CT device, the CT nitride layer in a string of the
conventional 3D CT is continuously connected from top to bottom CGs along the
channel side, and it acts as a charge spreading path, which is an unavoidable
problem of 3D CT cell. As a result, this causes degradation of data retention
characteristics and poor distribution of cell state. In 3D FG cells, on the contrary,
the FG is completely isolated by the tunnel oxide and the Inter Poly Dielectric
(IPD). This approach allows obtaining a signicantly reliable structure, able to
contain charges without any problem related to leakage paths [34].
In order to compare the cell size, DC-SF as 3D FG and BiCS/TCAT as 3D CT
are considered. The effective cell size is estimated and plotted in Fig. 2.40 as a
function of the number of stacked cells. Even if the physical size of DC-SF cell is
assumed to be 54 % larger than that of conventional BiCS/TCAT, DC-SF allows
fabricating 1 Tb arrays with 3 bit/cell and 64 stacked cells or 2 Tb arrays with 3
bit/cell and 128 stacked cells, thanks to the small FG-FG interference.
Moreover, 3D FG ensure reliable retention characteristics and lower operation
voltage than that of conventional 3D CT [34]. As a result, the 3D FG structure
allows highly enhanced device performance for 3D NAND flash memory compared
to 3D CT. In the following, a summary of 3D FG advantages and disadvantages
compared to 3D CT is reported [37]:
Fig. 2.39 Comparison of 3D
NAND flash cell structures
(a) CT cell (BiCS) (b) 3D-FG
cell [34]

60

A. Grossi et al.

Fig. 2.40 Effective cell sizes

for various DC-SF NAND
flash structures [34]

Advantages of 3D FG:
Lower charge spreading resulting in less read errors, and consequently less ECC
intervention, in particular in multilevel architectures;
better data retention because of a more stable charge into the storage layer;
direct connection between channel poly and p-well, allowing bulk erase (no
GIDL).
Disadvantages of 3D FG:
Larger cell size;
larger 3D pillar due to the presence of the floating gate, and hence lower
scalability;
floating gate coupling effect: even if the S-SCG structure can sufciently suppress the indirect interference effect, direct coupling remains a very serious
problem that strongly reduces the programming speed.
Even if 3D FG shows a relevant number of reliability advantages compared to
3D CT, the higher scalability still makes 3D CT the most attractive solution for the
integration in hyper-scaled arrays. Moreover, it must be pointed out that enhanced
programming algorithms and error correction techniques allows mitigating the
previously described reliability issues.

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