HINDUSTAN INSTITUTE OF TECHNOLOGY & SCIENCE

Department of Information Technology

Digital Principles System Design
Question Bank for Model Exam with answers
Part A:
1. Distinguish between Mealy and Moore model.
Mealy: Depends upon external input and present state.
Moore: Depends upon only present states.
Mealy Model

Input

Combin
ational
Logic

Sequential
Logic

Output
Logic

Present
States

Output

Moore Model

Input
(optional)

Combin
ational
Logic

Sequential
Logic

Output
Logic

Present
States

Output

2. Draw the internal circuit of a NOR gate latch and derive the truth table.
S
0
0
1
1

R
0
1
0
1

Q
Q
Hold Hold
0
1
1
0
X
X

3. Mention any two uses of HDL.

Used for writing the code, this can be embedded into the chip.
To convert logic into a coding level format.

4. Implement the logic function f = m(0,2,3,6) using a decoder.

0
1
X

2
3 x 8 Decoder

3
4

5
6
7

5. What is Modulo N counter?

A counter modulo N has pulses (the counting sequence is from 0 to -1). The fourbit binary counter has 16 pulses (the counting sequence is from 0 up to 15) and
therefore is called modulo 16 counter. The BCD counter has 10 pulses (the counting
sequence is from 0 to 9) and therefore called modulo 10 counter.
6. What is a state diagram?
The information available in a state table can be represented graphically in a state
diagram. In this type of diagram a state is represented by a circle, and the transition
between states is indicted by directed lines connecting the circles.
7. Write down the characteristic table of all flip-flops.
S
0
0
1
1

R
0
1
0
1

Q
Hold
0
1
X

J
0
0
1
1

K
0
1
0
1

Q
Hold
0
1
Comp

D
0
1

Q
0
1

T
0
1

Q
Hold
Comp

8. Write down the general equation for all shift registers.

SISO n + 3 clock pulse
SIPO Four clock pulse
PISO Four clock pulse
PIPO One clock pulse
9. What is the advantage of universal shift register?
The purpose of the parallel-in/ parallel-out shift register is to take in parallel data,
shift it, then output it as shown below. A universal shift register is a do-everything
device in addition to the parallel-in/ parallel-out function.

10. Differentiate sequential and ripple counter.

Sequential Counter
Ripple Counter
It is governed by a global clock signal It is not governed by a global clock
generated by an oscillator.
signal generated by an oscillator.
Initially only it needs a clock to start
the counting.
The counter changes only by an The counter changes as and when the
application of a distributed clock signal. output is obtained, as the output of each
flip flop is connected as clock input of
the next flip flop.
It is a fast counter.
It is a slow counter.
11. Draw the NAND and NOR latch diagram.

12. What are the differences between sequential and combinational circuits?
Combinational
Sequential
The output depends upon input and The output depends upon input,
functionality of the circuits.
functionality of the circuits and
previous output.
It is not governed by a global clock It is governed by a global clock signal
signal generated by an oscillator.
generated by an oscillator.
No feedback.
Feedback is present.
Eg. Gates.
Eg. Flip Flops.

13. Define synchronous and asynchronous sequential circuits.

Synchronous sequential circuit: In synchronous circuits the input are pulses (or
levels and pulses) with certain restrictions on pulse width and circuit propagation
delay. Therefore synchronous circuits can be divided into clocked sequential circuits
and uncklocked or pulsed sequential circuits. The present state is totally specified by
the flip-flop values and does not change if the input changes while the clock pulse is
inactive.
Asynchronous sequential circuit: The circuit is considered to be asynchronous if it
does not employ a periodic clock signal C to synchronize its internal changes of state.
Therefore the state changes occur in direct response to signal changes on primary
(data) input lines, and different memory elements can change state at different times.
The internal state can change immediately after a change in the input.
14. What are the guidelines to be followed while making state assignments for output?
Assign a 0 to an output variable associated with an unstable state that is a
transient state between two stable states that have a 0 in the corresponding output
variable.
Assign a 1 to an output variable associated with an unstable state that is a
transient state between two stable states that have a 1 in the corresponding output
variable.
Assign a dont care condition to an output variable associated with an unstable
state that is a transient state between two stable states that have different values (0
and 1 or 1 and 0) in the corresponding output variable.
15. With a help of a diagram explain about master slave flip-flop using JK flip flop.

A master slave flip flop is constructed from two separate flip flops. One circuit
serves as a master and the other as a slave. When CLK is 1 the first flip flop
works and when the CLK is 0 the second flip flop works.
16. What are the two types of asynchronous circuits? How do they differ?
Fundamental Mode: In fundamental mode circuit, all of the input signals are
considered to be levels. The fundamental mode operation assumes that the input
signals will be changed only when the circuit is in a stable state and that only one
variable can change at a given time.
Pulse Mode: In pulse mode circuits, the inputs are pulses rather than levels. In this
mode of operation the width of the input pulses is critical to the circuit operation. The
input pulse must be long enough for the circuit to respond to the input but it must not
be so long as to be present even new state is reached. In such a situation the state of
the circuit may make another transition.
17. Differentiate shifting and rotating.
Shifting: This shifts out the data to the right or left and stuffs 0s in the opposite
direction.
Eg. 2 bit right shifting of 11001 is 00110
Rotating: This rotates the data clockwise or anticlockwise.

Eg. 2 bit right rotating of 11001 is 01110

18. When is a counter said to suffer from lock out?

In a counter if the next state of some unused state is again an unused state and if by
chance the counter happens to find itself in the unused states and never arrived at a
used state then the counter is said to be in the lockout conditions.
19. Differentiate latch and flip flop.
Flip flop
Latch
Flip flops are edge triggered.
Latches are level triggered.
Glitches (spike / noise) are avoided Glitches (spike / noise) are not avoided.
mostly.
It needs a area of two latches.
It needs area/2.
20. Define set up time and hold time.
Setup Time: The amount of time, the data input is valid before the clock edge.
Hold Time: The amount of time, the data input is valid after the clock edge.

Part B:
21. Draw the logic diagram of a 4-bit shift register with 4 flip-flops and four-4x1 mux
with mode selection inputs s1 and s0. The register operates as follows
S1
S0
Register Operation
0
0
No change
0
1
Complement
1
0
Clear to 0
1
1
Load parallel data
22. Explain the differences among a truth table, a state table, a characteristic table, and an
excitation table. Explain the difference among a Boolean equation, a state equation, a
characteristic equation and a flip-flop input equation.
Truth Table
For each combination of values of inputs, there is a value for output specified by the
definition of logical operation, i.e., a truth table is a table of all possible combinations of
variables showing the relation between the values that the variables may take and the
result of the operation.
Ex: Z=AB+C
Inputs
Output
A
B
C
Z
0
0
0
0
0
0
1
1
0
1
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
1

State Table
The time sequence of inputs, outputs and Flip Flop states can be enumerated in a state
table. There are 4 sections in a state table. They are present state, input, next state and
output.
Ex:
Present State
Input
Next State
Output
A
B
x
A(t+1) B(t+1)
y
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
1
0
1
1
1
1
0
1
0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
0
1
1
1
1
1
0
0
Characteristic Tables
Characteristic Table defines the next state as a function of the inputs and present state. Q
(t) refers to the present state prior to the application of a pulse. Q (t+1) is the next state
one clock period later.
J
K
Q (t+1)
0
0
Q (t)
No Change
0
1
0
Reset
1
0
1
Set
1
1
Q' (t) Complement
Excitation Table
A table that lists the required inputs for a given change of state is called an excitation
table.
Q (t)
Q (t+1)
J
K
0
0
0
X
0
1
1
X
1
0
X
1
1
1
X
0
Flip-Flop Input Equations
The logic diagram of a sequential circuit consists of flip-flops and gates. The
interconnections amng the gates form a combinational circuit and maybe specified
algebraically with Boolean functions.
The part of the circuit that generates the inputs to flip-flops are described algebraically by
a set of Boolean functions called flip-flop input equations.
Ex: JA = BCx +BCx
KA =B + y
Boolean Equations
A Boolean equation is an expression formed with binary variables, the two binary
operators OR and AND, and unary operator NOT.
Ex: F = ab + c

Characteristic Equations
A characteristic equation is an algebraic equation which represents the logical properties
of a flip-flop, as described in the characteristic table.
Ex: Qt+1 = JQ + KQ
State Equations
A state equation specifies the next state as a function of the present state and inputs.
Ex: At+1 =Ax + Bx
23. With examples, explain the different types of races in Asynchronous sequential
circuits.
24. Explain the difference between asynchronous and synchronous sequential circuits.
Define fundamental mode operation. Explain the difference between stable and
unstable states. What is the difference between an internal state and the total state?

Refer Question No 13 and 16. Also refer notes of 5th Unit.

Stable State: For a given value of input variables, the system is in stable state if the
circuit reaches a steady-state condition.
Unstable State: For a given value of input variables, the system is in unstable state if
the circuit does not reach the steady-state condition. The circuit is in a continuous
transition.
Internal State: A sequential circuit is specified by a time sequence of inputs, outputs
and internal states. In synchronous sequential circuits, the change of internal state
occurs in response to the synchronous clock pulses. In an asynchronous circuit, the
change of internal state occurs when there is a change in the input.
Total State: In an asynchronous circuit, the internal state can change immediately
after a change in the input. Because of this, it is sometimes convenient to combine the
internal state with the input value together and call it the total state of the circuit.
25. Design a Decade (Mod 10) counter (or any other Mod counter).
26. Conversion of flip flops.
27. Explain the different types of shift registers with neat diagram
28. Learn all the problems discussed under Unit IV and Unit V.
29. Learn all the assignment problems.
30. With examples, explain different types of hazards in sequential circuits.