Chapter 2

Introduction of IC
Fabrication
Hong Xiao, Ph. D.
hxiao89@hotmail.com
Hong Xiao, Ph. D.

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Objectives

Define yield and explain its importance

Describe the basic structure of a cleanroom.
Explain the importance of cleanroom protocols
List four basic operations of IC processing
Name at least six process bays in an IC fab
Explain the purposes of chip packaging
Describe the standard wire bonding and flip-chip
bump bonding processes

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Wafer Process Flow

Materials

IC Fab
Metallization

CMP

Dielectric
deposition

Test

Wafers
Thermal
Processes

Implant
PR strip

Etch
PR strip

Packaging

Masks
Photolithography

Final Test

Design
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Fab Cost

Fab cost is very high, > $1B for 8 fab

Clean room
Equipment, >$1M per tool
Materials, high purity, ultra high purity
Facilities
People, training and pay

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Wafer Yield

YW =

Hong Xiao, Ph. D.

Wafers good
Waferstotal

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Die Yield

YD =

Hong Xiao, Ph. D.

Dies

good

Dies total

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Packaging Yield

YC =

Hong Xiao, Ph. D.

Chips good
Chipstotal

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Overall Yield
YT = YWYDYC
Overall Yield determines whether a fab is
making profit or losing money
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How Does Fab Make Money

Cost:
Wafer (8): ~$150/wafer*
Processing: ~$200 (1$/wafer, 200 process steps)
Packing: ~$1/chip

Sale:
~100 chips/wafer
~$50/chip (low-end microprocessor in 2000)
*Cost of wafer and price of chip are changing daily, numbers
are choosing randomly based on general information.
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How Does a Fab Make (Loss) Money

Cost:

100% yield: 150+200+100 = $450/wafer

50% yield: 150+200+50 = $400/wafer
0% yield: 150+200 = $350/wafer

Sale:

100% yield: 100

50 = $5,000/wafer
50% yield: 5050 = $2,500/wafer
0% yield: 050 = $0.00/wafer

100% yield: 5000 - 450 = $4550/wafer

Profit
50% yield : 2500 - 400 = $2100/wafer
Margin:
0% yield : 0 - 350 = $350/wafer
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10

Throughput
Number of wafers able to process
Fab: wafers/month (typically 10,000)
Tool: wafers/hour (typically 60)

At high yield, high throughput brought

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Defects and Yield

1
Y
n
(1 + DA)

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12

Yield and Die Size

Killer Defects

Y = 28/32 = 87.5%

Hong Xiao, Ph. D.

Y = 2/6 = 33.3%

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13

Illustration of a Production Wafer

Die

Test die

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14

Illustration of a Production Wafer

Test
Structures

Scribe Lines

Dies
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15

Clean Room
Particles kills yield
IC fabrication must in a clean room

Artificial environment with low particle counts

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16

Clean Room
First used for surgery room to avoid bacteria
contamination
Adopted in semiconductor industry in 1950
Smaller device needs higher grade clean room
Less particle, more expensive to build

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17

Clean Room Class

Class 10 is defined as less than 10 particles
with diameter larger than 0.5 m per cubic
foot.
Class 1 is defined as less than 1 such particles
per cubic foot.
0.18 mm device require higher than Class 1
grade clean room.
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18

Cleanroom Classes
100000
Cl

# of particles / ft3

10000

,0

as

100
10

0.1

s1

00

Cl

1000

Hong Xiao, Ph. D.

as

Cl
as
sM
-1
0.1

s1

00

0,
00
Cl
as
0
Cl
s1
as
Cl
s1
as
,0
00
s1
00
0
Cl
as
s1

1.0
10
Particle size in micron

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19

Definition of Airborne Particulate

Cleanliness Class per Fed. Std. 209E
Particles/ft3
Class

0.1 m

0.2 m

0.3 m

0.5 m

M-1

9.8

2.12

0.865

0.28

35

7.5

10

350

75

30

10

750

300

100

100

5 m

1000

1000

10000

10000

70

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20

Effect of Particles on Masks

Particles
on Mask
Stump
on +PR

Hong Xiao, Ph. D.

Hole on
PR

Film

Film

Substrate

Substrate

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Effect of Particle Contamination

Ion Beam
Dopant in PR
Particle
Photoresist
Screen Oxide

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Partially Implanted Junctions

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22

Cleanroom Structure
Makeup Air

Makeup Air
Fans

Equipment Area
Class 1000
Process
Tool

Return Air

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HEPA Filter
Process Area

Equipment Area
Class 1000
Process
Tool

Raised Floor
with Grid Panels
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Pump, RF
and etc.
23

Gowning Area
Shelf of Gloves, Hair
and Shoe Covers

Gown Racks

Entrance

Disposal Bins
Shelf of
Gloves
To
Cleanroom

Wash/Clean
Stations

Shelf of
Gloves

Storage
Benches
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24

IC Fabrication Process Module

Thin film growth,
dep. and/or CMP
Photolithography
Etching

Ion Implantation

PR Stripping

PR Stripping
RTA or Diffusion

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Illustration of Fab Floor

Equipment Areas

Process Bays

Corridor

Service Area
Sliding Doors
Hong Xiao, Ph. D.

Gowning Area

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26

Wet Processes

Etch, PR strip, or clean

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Rinse

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Dry
27

Horizontal Furnace
Heating Coils

Wafers

Quartz
Tube

Temperature

Gas flow
Center Zone
Flat Zone

Distance
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Vertical Furnace
Process
Chamber
Heaters

Wafers
Tower

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29

Schematic of a Track Stepper

Integrated System
Wafer

Prep
Chamber

Spin Coater

Chill Plates

Stepper

Chill Plates
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Developer

Hot Plates

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Wafer
Movement
30

Cluster Tool with Etch and Strip

Chambers
PR Strip
Chamber

PR Strip
Chamber

Etch
Chamber

Etch
Chamber
Transfer
Chamber

Robot

Loading Station
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Unloading Station

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31

Cluster Tool with Dielectric CVD

and Etchback Chambers
O3-TOES
Chamber

Ar Sputtering
Chamber

PECVD
Chamber
Transfer
Chamber

Robot

Loading Station
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Unloading Station

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32

Cluster Tool with PVD Chambers

AlCu
Chamber

AlCu
Chamber

Ti/TiN
Chamber

Ti/TiN
Chamber
Transfer
Chamber

Robot

Loading Station
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Unloading Station

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33

Dry-in Dry-out CMP System

Wafer Loading
and Standby

Polishing
Pad

Post-CMP Clean

Polishing
Heads

Rinse

Multi-head Polisher
Dryer and Wafer
Unloading
Clean Station
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34

Process Bay and Equipment Areas

Sliding Doors

Equipment Area

Equipment Area

Tables For PC and

Metrology Tools

Process Tools

Process Area
Service Area
Wafer Loading Doors
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Test Results
Failed die

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36

Chip-Bond Structure
Microelectronics Devices and Circuits
Chip Backside
Metallization

Chip (Silicon)
Solder

Substrate
Metallization

Substrate (Metal or Ceramic)

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Melt and
Condense

37

Wire Bonding
Metal Wire

Wire Clamp

Bonding Pad

Bonding Pad

Bonding Pad

Formation of
molten metal ball

Press to make
contact

Head retreat

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38

Wire Bonding

Bonding Pad

Lead

Lead contact with

pressure and heat
Hong Xiao, Ph. D.

Bonding Pad

Lead

Clamp closed with heat

on to break the wire

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IC Chip with Bonding Pads

Bonding Pads

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IC Chip Packaging
Chip
Bonding
Pad

Pins
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41

Chip with Bumps

Bumps

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Flip Chip Packaging

Bumps
Chip

Socket
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Pins
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43

Bump Contact

Bumps
Chip

Socket
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Pins
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Heating and Bumps Melt

Bumps
Chip

Socket
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Pins
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Flip Chip Packaging

Chip

Socket
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Pins
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46

Molding Cavity for Plastic Packaging

Top Chase

Bonding Wires

Molding Cavity

IC Chip

Lead Frame
Chip Bond Metallization
Pins
Bottom Chase
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Ceramic Seal
Bonding Wires
Cap Seal
Metallization

IC Chip

Ceramic Cap
Layer 2

Layer 2

Lead Frame, Layer 1

Pins
Chip Bond Metallization
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48

Summary
Overall yield
Yield determines losing money or making
profit
Cleanroom and cleanroom protocols
Process bays
Process, equipment, and facility areas
Die test, wafer thinning, die separation, chip
packaging, and final test
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