CA3140, CA3140A

Data Sheet

September 1998

File Number 957.4

lead pinout used for

the 741 and other

4.5MHz, BiMOS
Operational Amplifier
with MOSFET
Input/Bipolar Output
The CA3140A and CA3140 are

industry standard op
amps. The CA3140A
and CA3140 are

Features
MOSFET Input
Stage
- Very High Input

intended for operation

Impedance (ZIN)

at supply voltages up

-1.5T (Typ)

to 36V ( 18V).

1-

Very
Low
Input Current (Il)
-10pA (Typ) at
15V
2- Wide
Common
Mode
Input
Voltage

integrated circuit operational

amplifiers that combine the
advantages of high voltage PMOS
transistors with high voltage bipolar

Range (VlCR) Can be Swung

0.5V
Below
Negative Supply
Voltage Rail

transistors on a single monolithic

chip.

3-

The CA3140A and CA3140 BiMOS

Swing

operational amplifiers feature gate

Complemen

protected MOSFET (PMOS)

ts

transistors in the input circuit to

Mode

very low input current, and high speed

CA3140 operate at supply voltage
from 4V to 36V (either single or dual

Range

2
Directly
Repla

supply). These operational amplifiers

ces

are internally phase compensated to

Indust
ry

achieve stable operation in unity gain

Type

follower operation, and additionally,

741 in

have access terminal for a

Most

supplementary external capacitor if

Applic

additional frequency roll-off is desired.

ations

Terminals are also provided for use in

applications requiring input offset
voltage nulling. The use of PMOS field
effect transistors in the input stage

Applications
1

Supply Amplifiers in

capability down to 0.5V below the

Automo-bile

negative supply terminal, an important

protection against damage from load

terminal short circuiting to either
supply rail or to ground.

The CA3140 Series has the same 8-

and

Portable

attribute for single supply applications.

transistors and includes built-in

Ground-

Referenced Single

results in common mode input voltage

The output stage uses bipolar

Input

Common

provide very high input impedance,

performance. The CA3140A and

Output

Instrumentation

Sample and
Hold Amplifiers

3
Lo
n
g

Duration
Timers/Multivi

TTL

brators

ms

secondsMinutesHours)

and

Tone
Controls

12

Power
Supplies

Voltag
e

Active Filters

13

Portable
Instruments

Syste

Comparators

ms

Interface in 5V

(BRAND)

11

Suppl

Peak Detectors

PART NUMBER

Function
Generators

Low

Photocurrent
Instrumentation

Ordering
Information

10

Other

4
5
6
7
8

Operational
Amplifier
Applications

Syste

9
Pinouts

TEMP.
RANGE (

CA3140AE

-55 to 125

CA3140AM
(3140A)

-55 to 125

CA3140AS

-55 to 125

CA3140AT

-55 to 125

CA3140E

-55 to 125

CA3140M
(3140)

-55 to 125

CA3140M96
(3140)

-55 to 125

CA3140T

-55 to 125

All Standard

14

Intrusion
Alarm Systems

INV.
INPUT

NON-INV.
INPUT

6 OUTPUT

+
3

5 OFFSET
4
NULL
V- AND CASE

CA3140 (PDIP, SOIC)

TOP VIEW
OFFSET
NULL

INV. INPUT

NON-INV.
INPUT

V-

8 STROBE

7 V+
6 OUTPUT
5

OFFSET
NULL

CAUTION: These devices are sensitive to electrostatic discharge; follow p

1-888-INTERSIL or 321-724-7143 | Copyrig

CA3140, CA3140A
Absolute Maximum Ratings

Thermal Information

o
o
JA ( C/W) JC ( C/W)
Thermal Resistance (Typical, Note 1)
PDIP Package . . . . . . . . . . . . . . . . . . .
100
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
160
N/A
Metal Can Package . . . . . . . . . . . . . . .
170
85
o
Maximum Junction Temperature (Metal Can Package) . . . . . . . 175 C
o
Maximum Junction Temperature (Plastic Package)
. . . . . . . 150 C
o
o
Maximum Storage Temperature Range . . . . . . . . . . -65 C to 150 C
o
Maximum Lead Temperature (Soldering 10s) . . . . . .
. . . . . . 300 C

DC Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . 36V

Differential Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) To (V- -0.5V)
Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short Circuit Duration (Note 2). . . . . . . . . . . . . . . . Indefinite

Operating Conditions
o
o
. . . . -55 C to 125 C

Temperature Range

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. JA is measured with the component mounted on an evaluation PC board in free air.

2. Short circuit may be applied to ground or to either supply.
Electrical Specifications

SUPPLY

o
= 15V, T = 25 C
A

TYPICAL VALUES
PARAMETER

SYMBOL

Input Offset Voltage Adjustment Resistor

TEST CONDITIONS
Typical Value of Resistor
Between Terminals 4 and 5 or 4 and 1 to

CA3140

CA3140A

UNITS

4.7

18

Adjust Max VIO

Input Resistance

RI

1.5

1.5

Input Capacitance

CI

pF

Output Resistance

RO
eN

60

60

BW = 140kHz, RS = 1M

48

48

eN

RS = 100

Equivalent Wideband Input Noise Voltage

(See Figure 27)
Equivalent Input Noise Voltage (See Figure 35)

Short Circuit Current to Opposite Supply

Gain-Bandwidth Product, (See Figures 6, 30)

Slew Rate, (See Figure 31)

f = 1kHz

40

40

nV/Hz

f = 10kHz

12

12

nV/Hz

IOM+

Source

40

40

mA

IOM-

Sink

18

18

mA

4.5

4.5

MHz

V/ s

220

220

fT
SR

Sink Current From Terminal 8 To Terminal 4 to

Swing Output Low
Transient Response (See Figure 28)

tr
OS

Settling Time at 10VP-P, (See Figure 5)

Electrical Specifications

tS

RL = 2k

Rise Time

0.08

0.08

CL = 100pF

Overshoot

10

10

RL = 2k

To 1mV

4.5

4.5

Voltage Follower

To 10mV

1.4

1.4

CL = 100pF

o
For Equipment Design, at V SUPPLY = 15V, T = 25 C, Unless Otherwise Specified
A

CA3140
PARAMETER

SYMBOL

MIN

TYP

CA3140A
MAX

MIN

TYP

MAX

UNITS

Input Offset Voltage

|VIO|

15

mV

Input Offset Current

|IIO|

0.5

30

0.5

20

pA

Input Current

II
A

10

50

10

40

pA

20

100

20

100

kV/V

86

100

86

100

dB

Large Signal Voltage Gain (Note 3)

(See Figures 6, 29)

OL

CA3140, CA3140A
Electrical Specifications

For Equipment Design, at V

SUPPLY

o
= 15V, T = 25 C, Unless Otherwise Specified (Continued)
A

CA3140
PARAMETER

SYMBOL

Common Mode Rejection Ratio

(See Figure 34)

TYP

MAX

MIN

TYP

MAX

UNITS

32

320

32

320

V/V

70

90

70

90

dB

-15

-15.5 to +12.5

11

-15

-15.5 to +12.5

12

100

150

100

150

V/V

76

80

76

80

dB

VOM+

+12

13

+12

13

VOMI+

-14

-14.4

-14

-14.4

mA

PD

120

180

120

180

VIO/ T

mW
o
V/ C

CMRR

Common Mode Input Voltage Range (See Figure 8)

Power-Supply Rejection Ratio,

ICR

PSRR

VIO/ VS (See Figure 36)

Max Output Voltage (Note 4)
(See Figures 2, 8)
Supply Current (See Figure 32)
Device Dissipation
Input Offset Voltage Temperature Drift

MIN

CA3140A

NOTES:

3. At VO = 26VP-P, +12V, -14V and RL = 2k .

4. At RL = 2k .
Electrical Specifications

For Design Guidance At V+ = 5V, V- = 0V, T

o
= 25 C
TYPICAL VALUES

PARAMETER

SYMBOL

CA3140

CA3140A

UNITS

Input Offset Voltage

|VIO|

mV

Input Offset Current

|IIO|

0.1

0.1

pA

Input Current

II

pA

Input Resistance

RI

100

100

kV/V

100

100

dB

32

32

V/V

90

90

dB

-0.5

-0.5

2.6

2.6

Large Signal Voltage Gain (See Figures 6, 29)

OL

Common Mode Rejection Ratio

CMRR

Common Mode Input Voltage Range (See Figure 8)

ICR

Power Supply Rejection Ratio

Maximum Output Voltage (See Figures 2, 8)

Maximum Output Current:

Source
Sink

Slew Rate (See Figure 31)

PSRR

100

100

V/V

VIO/ VS

80

80

dB

VOM+

VOM-

0.13

0.13

IOM+

10

10

mA

OMSR

Supply Current (See Figure 32)

fT
I+

Device Dissipation

PD

Gain-Bandwidth Product (See Figure 30)

Sink Current from Terminal 8 to Terminal 4 to Swing Output Low

mA

V/ s

3.7

3.7

MHz

1.6

1.6

mA

mW

200

200

CA3140, CA3140A
Block Diagram

2mA

4mA

7 V+

BIAS CIRCUIT
CURRENT SOURCES
AND REGULATOR
200 A

1.6mA

200 A

2mA

A
INPUT

2 A

10

10,000

6 OUTPUT

C1
12pF

4 V-

5
1
OFFSET
NULL

STROBE

Schematic Diagram
BIAS CIRCUIT

INPUT STAGE

SECOND STAGE

OUTPUT STAGE DYNAMIC CURRENT SINK

7 V+

D1

D
7

Q1

Q3

Q2

R9

20

50

D8

10

Q6

Q4

Q5

1K
Q

19

Q7

14

R 11

12

12K

17

Q8

8K

R8
1K

D3

20K

20

R1

13

5K

21

18

6 OUTPUT

D4
D5

INVERTING
INPUT
NON-INVERTING
INPUT

Q Q

9 10

C1
R2

R3

500

11

R4
500

12pF

500

14

15

16

13

12

R5
500

50
1

R7
30
4

OFFSET NULL

NOTE: All resistance values are in ohms.

STROBE

V-

CA3140, CA3140A
ated

Ap dow
pli n to
0.5
ca
V
tio belo
n w
Inf the
or neg
m ativ
e
ati
sup
on ply
Cir rail.
cui Two
t clas
De s A
scr amp
ipti lifier
on stag
As es
sh prov
o

ide

the

volt

in

age

th

gain

bl

and

oc a
k

uniq

di

ue

ag clas
ra

m, AB
th

amp

lifier

in

stag

driv
e

lowimp
eda
nce
load
s.
A
biasin
g
circuit
provid
es
contro
l of
casco
ded
const
ant
curre
nt
flow
circuit
s in
the
first
and
secon
d
stage
s. The
CA31
40
includ
es an
on

pu e

chip

prov

phase

ter ides

comp

mi the

ensati

na curr

ng

ls

ent

capac

gain

itor

ay nec

that is

be ess

suffici

op ary

ent

er

for

to

the sistors
unit (Q11,
Q12)
y
functi
gain oning
volt as
load
age
resisto
follo rs
wer togeth
con er
with
figur
resisto
atio rs R
2
n. throug
h R5.
Inp The
ut mirror
Sta pair
transi
ge
stors
The also
sch functi
ema on as
tic a
diag differe
ram ntialcon tosists single
of a diffe ended
renti conve
al rter to
inpu provid
t
e
stag base
e
curren
usin t drive
g
to the
PM secon
OS d
field stage
bipola
effe r
ct transi
tran stor
sisto(Q ).
13
rs Offset
(Q9, nulling
Q10 ,
)
when
wor desire
king d, can
into be
a
effect
mirr ed
or with a
pair 10k
of potent
bipo iomet
lar er
tran conne

cted
acros
s
Termi
nals 1
and 5
and
with
its
slider
arm
conne
cted
to
Termi
nal 4.
Casco
deconne
cted
bipola
r
transi
stors
Q2,
Q5
are
the
const
ant
curren
t
sourc
e for
the
input
stage.
The
base
biasin
g
circuit
for the
const
ant
curren
t
sourc
e is
descri
bed
subse
quentl
y. The
small
diode
s D3,
D4,
D5
provid
e gate
oxide

prot ne
ecti cte
d
on
loa
agai d
nst res
high ist
an
volt
ce
age pr
tran ovi
sien de
d
ts, by
e.g., bip
stati ola
r
c
tra
elec nsi
tricit sto
y. rs
Q

Se , 3
co Q
4
nd .
Sta On
ge chi
p

Mos ph
t of as
the e
co
volt m
age pe
ns
gain ati
in on
the ,
suffici
CA3
ent
140
for a
is
major
prov
ity of
ided
the
by
applic
the
seco ation
nd
ampli s is
fier
stage provi
,
consi ded
sting
by
of
bipol
C.
ar
transi
1
stor
Q

a
n
d
it
s
c
a
s
c
o
d
e
c
o
n

Additi
onal
Miller
Effect
comp
ensat
ion
(roll
off)
can
be
acco

13

mplis
hed,
when
desir
ed,
by
simpl
y
conn
ectin
ga
small
capa
citor
betw
een
Termi
nals
1 and
8.
Termi
nal 8
is
also
used
to
strob
e the
outpu
t
stage
into
quies
cenc
e.
When
termi
nal 8
is tied
to the
negat
ive
suppl
y rail
(Term
inal
4) by
mech
anical
or
electr
ical
mean
s, the
outpu
t
Termi

nal compl
6 ement
swi the
ngs capab
low,
ility of
i.e.,
the
app
PMO
roxi
mat S
ely input
to stage
Ter when
min opera
al 4 ting
pot
near
enti
the
al.
negati

Ou ve
tpu rail.
t Quies
Sta cent
ge curre
The nt in
CA3 the

140 emitte
Seri res

follow

circ er
uits casca
em de
ploy circuit
a
bro

(Q17,

Q18)
ad is
establi
ban
shed
by
d
transi
out stors
put
(Q14,
stag
Q15)
e
whose
that base
curren
can ts are
sink mirro
red to
load curren
s to t
flowin
the g
neg throug
h
ativ diode
e

D2 in
the

sup bias
ply circuit
sectio
to

n.
When
the

CA31
40 is
opera
ting
such
that
outpu
t
Termi
nal 6
is
sourc
ing
curre
nt,
transi
stor
Q18
functi
ons
as an
emitt
erfollow
er to
sourc
e
curre
nt
from
the
V+
bus
(Term
inal
7),
via
D7 ,
R9 ,
and
R11.
Unde
r
these
condi
tions,
the
collec
tor
poten
tial of
Q13
is
suffici
ently
high
to
permi
t the
nece
ssary
flow
of
base
curre
nt to
emitt
er
follow
er
Q17
which
, in
turn,
drive
s
Q18.

Whe flow
n
throug
the
CA3 h R13,
140 zener
is D ,
8
oper
and
ating
such R14.
that The
outp dynam
ut ic
Ter curren
minat sink
l 6 is is
sinki control
ng led by
curr voltag
ent e level
to sensin
the g. For
V- purpos
bus, es of
tran explan
sisto ation,
r
it is
Q16 assum
ed that
is
output
the
Termin
curr
al 6 is
ent
quiesc
sinki
ently
ng
establi
elem
shed
ent.
at the
Tran
potenti
sisto
al
r
midpoi
Q16 nt
is betwe
mirr en the
or V+
connand Vecte supply
d to rails.
When
D6, output
curren
R7, t
with sinkin
curr g
ent mode
fed operati
by on is
way require
of d, the
Q21,collect
or
R12, potenti
and al of
transis
Q20.tor
Tran
sisto Q13 is
driven
r
below
Q20,its
in quiesc
turn, ent
is level,
bias thereb
ed y
by causin
curr
ent g Q17,

Q18 to
decrea
se the
output
voltag
e at
Termin
al 6.
Thus,
the
gate
termin
al of
PMOS
transis
tor
Q21 is
displa
ced
toward
the Vbus,
thereb
y
reduci
ng the
chann
el
resista
nce of
Q21.
As a
conse
quenc
e,
there
is an
increm
ental
increa
se in
curren
t flow
throu
gh
Q20,
R12,

Q21,
D6,

R7,
and
the
base
of
Q16.
As a
result
, Q16
sinks
curre
nt
from
Termi
nal 6
in
direct
respo
nse
to

the
incre
menta
l
chang
e in
output
voltag
e
cause

d by as to
reduc
Q18 e the
.
base
This curren
sink t drive
curr from
ent
flow Q17,
s
thereb
rega y
rdle limitin
ss g
of curren
load t flow
;
in
any
exc Q18
ess to the
curr short
ent circuit
is ed
inter load
nallytermin
sup al.
plie
d by Bias
the
emit Circ
terfollo uit
wer

Q18 Quies
cent
.
Sho curren
rt t in all
circ stages
uit (excep
prot t the
ecti dynam
on
of ic
the curren
outp t sink)
ut of the
circ CA314
uit is0 is
prov depen
ided dent
by
upon
Q19 bias
,
curren
whic t flow

h is
driv in R1.
en The
into functio
con n of
duct
ion the
by bias
the circuit
high is to
volt establi
age sh and
drop mainta
dev in
elop
ed consta
acro nt
ss curren
t flow
R11 throug
und

er h D1,
outp
ut Q6,
shor
t
Q8
circ and
uit
con D .
ditio 2
ns. D1 is
Und a
er
thes diode
conne
e
con cted
ditio transis
ns, tor
the mirror
colleconne
ctor cted in
of paralle

Q19 l with
dive the
rts base
curr emitter
ent junctio
from ns of
Q4
so Q1,

Q2,
and
Q3.
D1
may
be
consid
ered
as a
curren
t
sampli
ng
diode
that
sense
s the
emitter
curren
t of Q6
and
autom
atically
adjust
s the
base
curren
t of Q6
(via
Q1) to
mainta
in a
consta
nt
curren
t
throug
h Q6,
Q8,
D2.
The
base
curren
ts in
Q2,
Q3 are
also
determ
ined
by
consta
nt
curren
t flow
D1.
Furthe
rmore,
curren
t in
diode
conne
cted
transis
tor Q2
establi
shes
the
curren
ts in
transis
tors
Q14
and
Q15.

Typ
ical
Ap

pli uniqu
ca e
desig
tio
n
ns based

mean

Wid upon

suitab

le for

the

s that
this
devic
e is

dyn PMO

many

ami S

single

suppl

Bipola

rang r

e of proce

applic

inpu ss.

ations

, such

Input

and comm
outp on
ut

mode

char voltag
acte e
risticrange
s

and

with output
the swing
mos capab
t

ilities

desi are
rabl compl
e

ement

high ary,
inpu allowi
t

ng

imp operat
eda ion
nce with
char the
acte single
risticsupply
s is down
achi to 4V.
eve
d in
the
CA3
140
by
the
use
of
an

as,
for
exam
ple,
where
one
input
is
driven
below
the
poten
tial of
Termi
nal 4
and
the
phase
sense
of the
outpu
t
signal
must
be
maint

The

ained

wide

dyna

most

mic

impor

range

tant

of

consi

these

derati

para

on in

meter

comp

s also

arator

applicatio
5

ns.

CA3140, CA3140A
in

nt of

Ou Figur
tpu e 1.
t This
Cir conn
cui ectio
t n
Co assur
nsi es
der that
ati the
on maxi
s mum

the
oper
ating
suppl
y
volta
ge.
V+
5V TO 36V
7
2

CA3140

Exc outpu

elle t
nt

signa

inte l
rfac swin
ing g will FIGURE 1.
with not
TTL go
circ more
uitr positi
y is ve
easi than
ly

the

achi zener
eve volta
d

ge

with minu
a

s two

sing basele

to-

6.2 emitt
V

er

zen volta
er

ge

dio drops
de withi
con n the
nec CA31
ted 40.
to

Thes

Ter e
min volta
al 8 ges
as are
sho indep
wn ende

ZE
NE
R
CL
AM
PI
NG
DI
OD
E
CO
NN
EC
TE
D
TO
TE
RM
IN
AL
S8
AN
D4
TO
LI
MI
T
CA
31
40
OU
TP
UT
S
WI

6.2V

LOGIC
SUPPLY
5V

TYPICAL
TTL GATE

5V

Q16

) vs
LOA
D
CU
RR
ENT

O
T
T
L
L
E

V Figur
E e2
L

51 , Q 16 )

show
s
output
curre
nt
sinkin
g
capab
SATURATIONVOLTAGE(mV)

OUTPUTSTAGETRANSISTOR(Q

ilities
of the
CA31
40 at
variou
s
LOAD
(SINKING)
CURRENT
(mA)
suppl
FIGURE 2.

V
voltag
OL
TA es.
G Outpu
E t
A
voltag
C
R e
O swing
S to the
S
negati
O
U ve
TP suppl
U y rail
T
permit
T
R s this
A devic
N e to
SI
opera
ST
O te
R both
S
power
(Q

transi

15 stors
A
and
N

thyrist
ors
directl
y
witho
ut the
need
for

lev is
el used
shif in
both
ting
case
circ
s to
uitr
limit
y the
usu drive
ally avail
ass able
oci to
the
ate
drive
d
n
wit
devic
h e.
the More
741 over,
seri it is
es reco
mme
of
nded
ope
that
rati
a
ona serie
l
s
am diod
plifi e
ers. and
shun
Fig t
ure diod
4 e be
sho used
ws at
so the
me thyris
typi tor
cal input
con to
figu prev
rati ent
ons large
.
nega
Not tive
e trans
that ient
a surg
seri es
es that
resi can
stor appe
,
ar at
the
RL ,
gate

of
thyris
tors,
from
dam
agin
g the
integ
rated
circui
t.

Offs
et
Volt
age
Nulli
ng
The
input
offset
voltag
e can
be
nulled
by
conn
ecting
a
10k
poten
tiome
ter
betwe
en
Termi
nals 1
and 5
and
return
ing its
wiper
arm
to
termi
nal 4,
see
Figur
e 3A.
This
techni
que,
howe
ver,
gives
more
adjust
ment
range
than

req e
uire pot
d
enti
and
ther om
efor eter
e, a ,
con
see
side
rabl Fig
e
ure
port 3B,
ion
to
of
the opti
pote miz
ntio e
met
its
er
rota utili
tion zati
is on
not
ran
fully
utili ge
zed. are
Typi giv
cal
en
valu
es in
of the
seri Ele
es
ctri
resi
stor cal
s
Sp

(R eci
)

fica

th

tion

at

tabl

ay e.
b

An
altern
pl ate
ac syste
m is
e
show
d n in
at Figur
eit e 3C.
This
h
circuit
er uses
e only
one
n
additi
d onal
of resist
th or of
e

appro
ximat
ely
the
value
show
n in
the
table.
For
poten
tiome
ters,
in
which
the
resist
ance
does
not
drop
to 0
at
either
end
of
rotati
on, a
value
of
resist
ance
10%
lower
than
the
value
s
show
n in
the
table
shoul
d be
used.

Low
Volt
age
Ope
ratio
n
Oper
ation
at
total
suppl
y
volta
ges

as perfor

The

low manc

output

as e

voltag

4V down

is

range

to

pos these

also

sibl lower

begin

s to

volta

with ges.

exten

the

CA3

The
low

down

140.

to the

negati

curr
ent
reg
ulat
or
bas
ed
upo
n
the
PM
OS
thre
shol
d
volt
age
mai
ntai
ns
reas

voltag
e
limitat
ion
occur
s
when
the
upper
extre
me of
the
input
comm
on
mode
voltag
e
range
exten
ds
down

ona to the

ble voltag
con e at

stan Termi
t

nal 4.

ope This

ratinlimit is
g

reach

curr ed at

ent a total
and suppl
hen y
ce voltag
con e just
sist below
ent 4V.

ve
suppl
y rail,
but is
slightl
y
higher
than
that of
the
input.
Figur
e8
show
s
these
chara
cterist
ics
and
show
s that
with
2V
dual
suppli
es,
the
lower
extre
me of
the
input
comm
on
mode

volt e is

age below

potent

rang groun

ial.

5
1

V
+

10k

V-

F
I
G
U
2
R
E
3
7
A
.
B
A
CA3
S
140
I
6
C
FI
G
U
R
E
3.
T
H
R
E
E
O
F
F
S
E
T
V
O
LT
A
G
E
N
U
L
LI
N
G
M
E
T
H
O
D
S

I
M

F
I
G
U
R
E
3
B
.

O
V
E
D
R
E
S
O
L
U
T
I
O
N

CA3140, CA3140A

120VAC

V+

+HV

LOAD

CA3140

-6

1mV

-8

10mV

-10
0.1

1.0
SETTLING TIME ( s)

FIGURE 5A. WAVEFORM

LOAD RESISTANCE (R

FIGURE 5. SETTLING TIME vs

INPUT VOLTAGE

LOAD CAPACITANCE (C

bet

is the f

B
a
n
d
w
i
d
t
h

we
en

typica
F
l

Ter

settlin

min

als

time

requir

a
n
d
S
l
e
w
R
a
t
e
F
o
r
t
h
o
s
e
c
a

and ed to
8

reach

can

1mV

red

or

uce

10mV

the

of the

ope final
n

value

loo

for

vario

-3d

us

levels

ban of
dwi

large

dth. signal
The input
sle

s for

the

rate volta
will, ge
ho

follow

wev er
er,

and

als

invert

ing

be

unity

pro

gain

port ampli

1mV

10mV
10

dt

fier

input

s can

tA
o

be

belo

w the

Term

inal 4

pote

ntial,

but a

serie

curre

nt

limiti

ng

ti

resist

or is

reco

mme

nded

to

limit

the

maxi

mum

input

termi

nal

curre

nt to

less

than

1mA

to

prev

ent

dam

age

to

the

input

prote

ction

circui

try.

drive

CA3140, CA3140A
is
sign suffici
al ent.

tran The
sien
typical
ts
fro input
m curren
forci t is on
ng a
sign the
al order
thro of
ugh
10pA
the
inpu when
t
the
prot inputs
ecti
on are
net center
wor ed at
k
nomin
and
dire al
ctly devic
drivi e
ng
the dissip
interation.
nal As the
con
output
stan
suppli
t
curr es
ent load
sour
curren
ce
whi t,
ch devic
coul
e
d
resudissip
lt in ation
posi will
tive
increa
feed
bac se,
k raisin
via
g the
the
outpchip
ut tempe
ter rature
min
and
al.
A resulti
3.9k ng in
increa
resi
stor sed

input

curren
t.
Figure
7
shows
typical
input
termin
al
curren
t
versu
s
ambie
nt
tempe
rature
for the
CA31
40.

It
is
we
ll
kn
ow
n
tha
t
M
OS
FE
T
de
vic
es
ca
n
ex
hib
it
sli
ght
ch
an
ge
s

olt

ag

e)

du

to

the

ap

pli

cat

ri

ion

of

ti

lar

ge

D
P
H
A
S
E
v
s
F
R
E

SUPPLY VOLTAGE: V

TA = 25

r
e
x
a
m
p
l

OPEN LOOP VOLTAGE GAIN (dB)

(f

ll

g
e
s
i
n
i
n

N
L
O
O
P
V
O
L
T
A

t
o
ff
s

G
A
I
N

e
t
v

40
20

FREQUENCY (Hz)

m 6.
FIGURE

60

10

80

100

A
N

es.

proce

d
i

ss is
revers
ible
and
offset

o
d

The

voltag
e
shifts
of the
oppos
ite
polarit
y
revers

n
p

t
e

e the
offset.
Figure
9
shows

typical

offset

the

voltag
e
chang
e as a
functi
on of

variou

e
r

u
r

t
a
i

Both
applie
d

voltag

e and

d
o
v
e

tempe
rature
accel
erate
these
chang

stress
voltag
es at
the
maxi
mum
rating
of

o
125
C (for
metal
can);
at
lower
tempe
rature
s
(metal
can
and
plastic
), for
exam

ple, de as
at

those

o encou
ntered
C, in an
this operat
cha ional
nge ampli
in fier
volt emplo
age ying a
is bipola
con r
side transi
rabl stor
y
input
less.stage.
In
typic
10K
al
line
1K
ar
appl
icati
100
ons,
whe
re
10
the
diffe
1
renti
al
-60 -40 -20
0 20 40 60 80
volt
10
age
0
is
12
0
sma
14
ll
0
and
T
sym
E
M
metr
P
ical,
E
thes
R
A
e
T
incr
U
eme
R
ntal
E
o
cha
(
nge
C)
s
are
F
I
of
G
abo
U
ut
R
the
E
sam
7.
e
I
mag
N
nitu
P
INPUTCURRENT (pA)

85

U
T
C
U
R
R
E
N
T
v
s
T
E
M
P
E
R
A
T
U
R
E

SUPPLY VOLTAGE: V

INPUT AND OUTPUT VOLTAGE EXCURSIONS

FROM TERMINAL 7 (V+)
-0.5

-1.5

-2.0

-2.5

-3.0

EXCURSIONS

INPUT
AND OUTPUT VOLTAGE

-1.0

1.5
-V

1.0

o
AT T = 125 C

ICR
o
A
-V ICR AT T = 25 C

o
-VICR AT TA = -55 C
A

0.5

-VOUT FOR
o
o
TA = -55 C to 125 C

0
-0.5
-1.0
-1.5
0

ed,
ass
em
FIGU
RE
ble8.
OUTP
d
UT
an
VOLT
d
AGE
test
SWIN
ed
G
un
CAPA
der
BILIT
Y
IS
AND
O9
COM
00
MON
0
MODE
qu
INPUT
alit
VOLT
y
AGE
RANG
sys
E
tevs
SUPP
ms
LY
cer
VOLT
tific
AGE
ati
on.
All
I
Int
n
ers
il
se
mi
co
nd
uct
or
pr
od
uct
s
ar
e
ma
nuf
act
ur

10
15
SUPPLY VOLTAGE (V+, V-)

o
r
For information regarding Intersil
Corporation and its products, see
web site

20

25

CA3140, CA3140A
N
C

OFFSET VOLTAGE SHIFT (mV)

R
E
M

functi

on

T
A
L
O

in
10.
The
1,000,
000/1
adjust

ment

range

I
F
T
v
s
O
P
E
R
A

is
acco
mplis
hed
by a
single
variab
le
potent
iomet

er or

by an

N
G
L (HOURS)
TIME
I

shown
Figure

is

range

ga
tuning

havin
wide

ator

gener

0 S

FIGURE 9.

Gen
erato
r

auxilia
ry
sweep
ing

signal

. The

Supe
r
Swe
ep
Func
tion

CA31
40
functi
ons
as a
noninverti

ng r

feed

rea outpu

back

doutt

loop

am signa
plifi ls are
er

then

of

appli

the ed to
triana
gula seco
r

nd

sign CA30
al

80

dev functi
elop oning
ed as a
acrohigh
ss spee
the d
inte hyste
gratiresis
ng switc
cap h.
acit Outp
or

ut

net from
wor the
k

switc

con h is
nect retur
ed ned
to

direct

the ly
outpback
ut ofto the
the input
CA3 of the
080 CA30
A

80A

curr curre
ent nt
soursourc
ce. e,
Bu
ffer
ed
tria
ng
ula

there
by,
comp
leting
the
positi
ve

The
trian
gula
r
outp
ut
leve
l is
dete
rmin
ed
by
the
four
1N9
14
leve
l
limit
ing
diod
es
of
the
sec
ond
CA3
080
and
the
resi
stor
divi
der
net
wor
k
con
nect
ed
to
Ter
min
al
No.
2

(i

nd,

provi

ther

des

efor

for a

ut

e,

const

indir

ant

of

ectly

gener

th

dete

ator

rmin

ampli

tude

the

outpu

amp

t, is

litud

most

e of

easily

0.

the

made

outp

ut

while

es trian
e
di
o
d
es
es
ta
bli
sh
th
e
in
p
ut
tri
p
le
ve
l
to
thi
s
s
wi
tc
hi
n
g
st
a
g
e
a

gle.

the
gener
ator

Com

is

pens

swee

ation

ping.

for

High

propa

frequ

gatio

ency

ramp

delay

linear

ity is

aroun

adjus

d the

ted

entire

by

loop

the

is

singl

provi

e 7pF

ded

to

by

60pF

one

capa

adjus

citor

tment

in the

on

outpu

the

t of

input

the

of the

CA30

CA30

80A.

80.

It

This
adjus
tment
,
which

m
u
st
b
e

fo

CA3

140

conn

ecte

xi

d as

mete

drive

ut

and

ut

buffe

li

ampl

ifier.

ar
o

it

in

th
e

ur

re
nt

er

at

or

fu
n

ct

io
n.

c
h
a
r
a
c
t
e
r
i
z
e
d

Low
drivi
ng
impe
danc
e is
requi
red
of
the
CA3
080
A
curr
ent
sour
ce to
assu
re
smo
oth

Mete
r
Drive
r and
Buffe
r
Ampl
ifier

oper

Figur

stme

e 11
sho
ws
the

ation
of
the
Freq
uenc
y
Adju
nt
Cont
rol.
This

lo

r, a

placed

w-

mete

across

dri r

the

vi

input

may

ng be

to the

im

CA308

pe
da
nc
e
re
qu
ire
m
en
t
is
ea
sil
y

0A to
give a
logarit
hmic
analog
indicat
ion of
the
functio
n
gener
ators
freque

ncy.

et

Analo
g
freque
ncy
reado
ut is
readily
acco
mplish
ed by
the
mean
s
descri
bed
above
becau
se the
output
curren
t of
the
CA30
80A
varies
appro
ximate
ly one
decad
e for
each
60mV
chang
e in
the
applie

by
us
in
g
a
C
A3
14
0
co
nn
ec
te
d
as
a
vo
lta
ge
fol
lo
w
er.
M
or
eo
ve

d
ablish
volt ed to
age
set
,

comp

VA lower

effect

the

limit

BC
on the
(volt
age meter.
bet The
wee three
n
remai
Ter
ning
min
transi
als
stors
5
and from

ensat
es for
the
s of
the
norm
al
negati
ve
tempe
rature
coeffi
cient

4 of the
the CA30
CA3
86
080
Array
A of
the used
func in the
tion swee
gen p
erat
gener
or).
ator
The
refo are
re, used
six for
dec this
ade
refere
s
nce
repr
ese voltag
nt e. In
360 additi
mV on,
cha
this
nge
refere
in

of the

VA gener

to

BC.

CA30
80A
VAB

C
termin
al
voltag
e.
Anoth
er
output
voltag
e from
the
refere
nce
gener
ator is

nce

used

ator

insure

arran
No geme
w, nt
only tends
the to
refe track

ren ambie
ce nt

volt tempe
age rature
mu variati
st ons,
be and
est thus

tempe
rature
tracki
ng of
the
lower
end of
the
Frequ
ency
Adjust
ment
Potent

iom set

Maxi

eter. the
A Frequ

mum

larg ency
e Adjus

ency

seri tment
es Poten

resi tiomet
er at
stan
its
ce
low
sim
end.
ulat
Then
es a
adjust
curr
the
ent
Minim
sourum
ce, Frequ
ass ency

urin Calibr
g

Frequ
Calibr
ation
Contr
ol for
the
maxi
mum
frequ
ency.
Beca
use
there
is
intera
ction
amon

ation
simi Contr

lar ol for

contr

tem the

ols,

per lowes
atur t

repeti

these

tion

frequ

of the

coe ency.
ffici To

adjust

ents establ
ish
at
the
both
upper
end
frequ
s of
ency
the
limit,
Fre
set
que
the
ncy
Frequ
Adj ency
ust Adjus
mentment
t

ment
proce
dure
may
be
nece
ssary.
Two
adjust
ment
s are
used
for
the

Poten
Con tiomet

meter

trol. er to

meter

To
cali
brat
e
this
circ
uit,

. The

its

sensit

upper

ivity

end

contr

and

ol

then

sets

adjust

the

the

meter

sca sitivity
le

adjust

wid ment
th

contr

of

ol

eac calibr
h

ates

dec the
ade meter
,

so

whil that it
e

deflec

the

1
ts /6

met
er

of full

each

pos scale
itio for
con decad
trol e
adj chang
ust e in
s

frequ

the ency.
poi Sine
nter Wave
on Shap
the er
sca

The
circuit
wit shown
h in
neg Figure
12
ligi
uses a
ble
CA31
effe 40 as
ct a
on voltag
e
the
follow
sen
er in
sitiv combi
ity nation
adj with
ust diodes
from
me
the
nt. CA30
Thu 19
s, Array
the to
conve
met
rt the
er triang
sen ular
le

signal
from
the
functi
on
gener
ator to
a
sinewave
output
signal
havin
g
typical
ly less
than
2%
THD.
The
basic
zero
crossi
ng
slope
is
establi
shed
by the
10k
potent
iomet
er
conne
cted
betwe
en
Termi
nals 2
and 6
of the
CA31
40
and
the
9.1k
resist
or and
10k
potent
iomet
er
from
Termi
nal 2
to
groun
d.
Two
break
points
are

esta zero
blis slope
hed at the
by maxim
diod um
es and
D1 minim
thro um
ugh levels
D4. of the
Posisine
tive wave.
feedThis
bac techni
k que is
via neces
D5 sary
and becau
D6 se the
esta voltag
blis e
hes follow
the er

config
uratio
n
appro
aches
unity
gain
rather
than
the
zero
gain
requir
ed to
shape
the
sine
wave
at the
two
extre
mes.
9

CA3140, CA3140A

CENTERIN
-15V

+15V

7.5k

+15V

360
3
360

SYMMETRY

CA3080A

4
5

2M

-15V

-15V

+15V

6
7-60
pF

15k

51
pF 2

+
CA3140

HIGH
FREQ.

4
0.1

SHAPE

-15V

2k

100k
FROM BUFFER METER
DRIVER (OPTIONAL)

FREQUENCY
ADJUSTMENT

39k

120

10k

5.1k

11k
10k
11k
EXTERNAL
OUTPUT

TO
SINE WAVE
SHAPER

-15V
+15V
OUTPUT

THIS NETWORK IS USED WHEN THE

OPTIONAL BUFFER CIRCUIT IS NOT USED

0
m
s/
Di
v.
E
x
t
e
r
n
a
O
ut
pu
t
at
ju
nc
tio
n
of
2.
7

an
d
51

re
si
st
or
s;
5
V/
Di
v.,
50

f
u
n
c

Center Trace:

Top Trace:

FIGURE 10A. CIRCUIT

t
i
o
n
g
e

u
t
p
u

e
a
t
o
r

r
i
a
n
g
u
l
a
r

/
i
v
.
,
5
0
0
m

10k

HIGH
FREQUENCY
LEVEL
0.1
910k
7-60pF
F

AMPLIFIER

62

2
3

s/Div.
Bottom
Trace:
Output of
Log
generator;
10V/Div.,
500ms/Div.
FIGURE
10B.
FIGURE
FUNCTION
GENERAT
OR
SWEEPIN
G

F
R
E
Q
U
E
N
C
Y
A
D
J
U
S
T
M
E
N
T

1V/Div.,
1s/Div.
Three tone test
signals,
highest
frequency

0.5MHz. Note
the
slight
asymmetry at
the
three
second/cycle
signal.
This
asymmetry is
due to slightly
different
positive
and
negative
integration
from
the
CA3080A and
from the PC
board
and
component
leakages
at
the
100pA
level.

FINE
RATE

SWEEP
GENERATOR

GATE
DC LEVEL
SWEEP ADJUST
OFF INT.

COARSE
RATE

V-

EXT.

SWEEP
LENGTH
V-

FIGURE 10C.
FUNCTIO
N
GENERA
TOR
WITH
FIXED
FIGURE
10D.
INTERC
ONNECT
IONS
FREQUE
NCIES
FIGURE 10. FUNCTION
GENERATOR

10

EXTERNAL
INPUT

CA3140, CA3140A
FREQUENCY
CALIBRATION
MAXIMUM
FREQUENCY 620k
7
ADJUSTMENT 51k
+
3
10k
CA3140
SWEEP IN
3M
2
500k

TO CA3080A
6

GENERATOR

(FIGURE 10)

4.7k

2k

OF FUNCTION CA3080A

+15V

0.1 F

5
METER
SENSITIVITY
ADJUSTMENT

12k
FREQUENCY 2.4k
CALIBRATION
MINIMUM
2.5

5.1k

620
1k
200 A
M METER

+1
100

11

510

510

8
6

2k

10

-15

14

12
METER
7
POSITION 3.6k
ADJUSTMENT

13

3/ 5 OF CA3086

-15V

FIGURE 11. METER DRIVER AND BUFFER AMPLIFIER

750k
LOG
SAWTOOTH
1N914

1M

22M
1N914

100k

SAWTOOTH
SYMMETRY

0.47 F

0.047
F

100k

18M

COARSE

4700p
F

FINE
RATE

8.2k

50k

RATE

470p
F

75
k
+15V0.1
LOG

CA31
40
3

+15V

SAW
F
TOO
TH

TRIANGL
E

30k

64

0.1

-15V

50k
LOG

100k
36k 3
TO
OUTPU
T
AMPLI
FIER

10k

EXTERN
AL
OUTPUT

RATE

ADJUST
1 TO
0 FUNCTI
k ON
GENERA

43k

TOR
SWEEP
IN

3
+
CA3140
2

-15V

7
6

LOGVIO

51k

SWE
EP
WIDT
H

6.8k

91k

5
1
25k

-15V

3.9 4
390

100

FIGURE 13.
SWEEPING
GENERATOR

11

FROM
CA3086
ARRAY
3

TRANSISTO
RS

CA3140, CA3140A
of

This R2.
circ The
uit final
can slop
be e is
adju esta
sted blish
mos ed
t
by
easi adju
ly sting
with
a R3,
dist ther
ortio eby
n addi
anal ng
yzer
, but
a
goo
d
first
appr
oxi
mati
on
can
be
mad
e by
com
pari
ng
the
outp
ut
sign
al
with
that
of a
sine
wav
e
gen
erat
or.
The
initi
al
slop
e is
adju
sted
with
the
pote
ntio
met
er
R1 ,
follo
wed
by
an
adju
stm
ent

VOLTAGE
ADJUSTMENT

REFERENCE
VOLTAGE

INPUT
2

dit r
io e
na
c

se o
g n
m t
en r
ts i
th b
at u
t
FIGURE
T 15.

i W
g
u

r
e
1
3
s
h
o
w
s

DC LEVEL
ADJUSTMENT

a
s
w
e

e FIGUR
E 14.

p WIDE

i BAND
n OUTP

UT
AMPLI
g FIER

g
e

nP
e
r
a
t
o
r.

CA3140

ad a

OUTPUT

REGULATED

CA3140, CA3140A
curre
nt
A
sampl
sma
ing.
ll
Foldb
hea
ack is
t
provid
sink
ed by
VE
the
RS
3k
AW
and
ATT
100k
tran

sist
divide
or is
r
use
netwo
d as
rk
the
conne
seri
cted
es
to the
pas
base
s
of the
ele
curre
me
nt
nt in
sensi
the
ng
fold
transi
bac
stor.
k
curr Both
ent
syst regula
em, tors
Fig provid
ure
17, e
sinc better
e
than
diss
ipati 0.02%
on load
leve regula
ls
will tion.
only Becau
app se
roac
there
h
10 is
W. const
In
this ant
syst loop
em, gain
the
D22 at all
01 voltag
diod e
e is
use settin
gs,
d
for the

2N6385

+30V

CURRENT

75

1k

100
7

2.7k 10 F

INPUT

9
8

3
5

100k

2
2N2102
3

56pF
1k

180k
82k

4
VOLTAGE
ADJUST

50k
14

12
13

1k

CA3140

+
2.2k
10 11

0.1 24V
AT 1A

1k
1k

3k

OUTPUT

POWER DARLINGTON LIMITING

ADJUST
D2201
2

100k

250 F

0.01 F

CA3086
1k
62k

HUM AND NOISE OUTPUT <200 VRMS

(MEASUREMENT BANDWIDTH ~10MHz)

LINE REGULATION 0.1%/V

FIG
URE
16.
RE
GUL
ATE
D
PO
WE
R
SUP
PLY

LOAD REGULATION
(NO LOAD TO FULL LOAD)
<0.02%

dwidt
reg h.
ulati Figur

on e
also 18A
rem show
s the
ains
turn
con ON
stan and
t. turn
OFF
Line
chara
reg cteris
ulati tics
on of
both
is
regul
0.1 ators.
% The
per slow
volt. turn
on
Hu
rise
m is
and due
nois to the
slow
e
rate
volt of
age rise
is of the
less refere
nce
than
volta
200 ge. FIGURE 17.
VFigur
as e
18B
rea
show
d s the
with transi
a ent
met respo
nse
er
of the
havi regul
ng aator
10Mwith
the
Hz
switc
ban hing
UP
RP
ECHA

RAC
1 TERI
8 STIC
5V/Div., 1s/Div.
AS
.
F
S
I
U
G

of a
20
load
at
20V
outpu
t.
OUTPUT 0V TO 25V
25V AT 1A
FOLDS BACK

FOLDBACK CURRENT
LIMITER
+30V

2N5294

D2201

TO 40mA

1k 200

100k

3k
2N2102

100k
7

CA3140
5

2.7k 10 F

100k

INPUT

8 1k

1 2

9
8

3
5

1k

180k
82k

4
VOLTAGE
ADJUST

5 F 50k
14

12
13

56pF

+
2.2k
10 11

100k

250 F

0.01 F

CA3086
1k
62k

HUM AND NOISE OUTPUT <200 VRMS

(MEASUREMENT BANDWIDTH

~10MHz)

LINE REGULATION 0.1%/V

REG
ULAT
ED
POW
ER
SUPP
LY
WITH
FOL
DBAC
K
CUR
RENT
LIMIT
ING

LOAD REGULATION
(NO LOAD TO FULL LOAD)
<0.02%

To
p
Tr
ac
e:
O
ut
pu
t
Vo
lta
ge
;
200mV/
Div., 5
s/Div.
Bottom Trace:
Colle
ctor
of
load
switc
hing
transi
stor,
load
= 1A;
5V/Di
v., 5
s/Div.
FIGU
RE
18B.
TRA
NSIE
NT
RES
PON
SE

FI

G
U

13

CA3140, CA3140A
plifier

unity

To s.
ne Two
Co tone
ntr contro
ol l
Cir circuit
cui s that
ts exploi

gain

Hig t

linea

these

sle chara
w

cterist

rate ics of
,

the

at
midb
and
and
uses
stan
dard
r
pote
ntio
mete
rs.

wid CA31

The

40

high

ban are

input

dwi show

impe

dth, n in

danc

high Figur

e of

out es 19

the

put and

CA3

volt 20.

140

age

mak

cap
abili
ty
and
high
inpu
t
imp
eda
nce
are
all
cha
ract
erist
ics
req
uire
d of
ton
e
cont
rol
am

The
first
circu
it,
sho
wn
in
Figu
re
20,
is
the
Bax
anda
ll
tone
contr
ol
circu
it
whic
h
provi
des

es
possi
ble
the
use
of
lowcost,
lowvalue
,
small
size
capa
citors
, as
well
as
redu
ced
load
of
the
drivin

Bass

e 19

sta treble

show

ge

boost

and

anoth

cut

er

are

tone

FOR
SINGLE SUPPLY
15dB
contr

at

ol

100H

circuit

z and

with

10kH

simila

z,

respe

boost

ctivel

and

y. Full

cut

peak-

speci

topeak
outpu
t is
availa
ble
up to
at
least
20kH
z due
to the
high
slew
rate
of the
CA31
40.
The
ampli
fier
gain
is
3dB
down
from
its
flat
positi
on at
70kH
z.
Figur

ficatio
ns.
The
wideb
and
gain
of
this
circuit
is
equal
to the
ultim
ate
boost
or cut
plus
one,
which
in this
case
is a
gain
of
eleve
n. For
20dB
boost
and
cut,
the
input
loadi

ng IC
of

Fla
t
Po
siti
on
Ga
in.

Oper

this ation
circ al
uit Trans
is

cond

ess uctan
ent ce
iall Ampl
y

ifier

eq (OTA

6.
1
5
d
B

ual )

to

With

the Powe
val r

s
s

ue Capa

of

bility

the by L.
res Kapl
ista an
H.

fro Wittli
m

e
b
l
e

nger,

Ter IEEE
mi Trans
nal actio
No. ns on
3

Broa

to

dcast

gro and
un Telev
d.

ision

Rece

det ivers,
aile Vol.
d

T
r

nc and
e

BTR-

B
o
o
s
t
a
n
d
C
u
t
a
t

an 18,

aly No.

sis 3,
of

Augu

this st,
circ 1972
uit .

H
z
a
n
d

is
giv NOTE
en S:
in
An

5. 20
dB

1
0
k
H
z

P-

P
ou
tp
ut
at
20
kH
z.

e
s
p
e
c
t

Hz
ref
ere
nc
e.
FOR DUAL
SUPPLIES
+15V

8. -

i
v
e
l
y
.

7. 2

5
V

3d
B
at
24
kH
z
fro
m
1k

0.005 F
5.1M

3 +
CA3140
2

4
-15V

TONE CONTROL
NETWORK

CIRCUIT
USING CA3140
SERIES

0.047

FIGURE 20. 14
BAXANDALL
TONE CONTROL

0.1 F
6

0.1 F

CA3140, CA3140A
alitie
facto
s is
r of
Wi
the
four
en Wien
and
Bri Bridg
R2 is
redu
dg e
sine
ced
e
wave
by a
Os
oscill
facto
cill ator.
r of
ato A
four,
the
r basic
Wien
gain
An
Bridg
requi
oth
e
red
er
oscill
for
ap
ator
oscill
pli
is
ation
cat
show
beco
ion
n in
mes
of
Figur
1.5,
the
e 21.
thus
CA
Whe
perm
31
n R1
itting
40
= R2
a
tha
=R
pote
t
and
ntiall
ma
C1 =
y
ke
C2 =
highe
s
C,
r
ex
the
oper
cel
frequ
ating
len
ency
frequ
t
equa
ency
us
tion
close
e
redu
r to
of
ces
the
its
to
gain
hig
the
band
h
famili
width
inp
ar f =
prod
ut
1/(2
uct of
im
RC)
the
pe
and
CA31
da
the
40.
nc
gain
e,
requi
hig
red
h
for
sle
oscill
w
ation,
rat
AOS
e,
C is
C1
an
equal
d
to 3.
hig
Note
h
that if
vol
C2 is
tag
incre
FIGURE 21.
e
ased
B
qu
by a
A

C2

R2

NOTES:

f =

+
OUTPUT

RS

1 1 2 2

2
OSC = 1 ++
C2

RF
R1

R C R C

ACL =

RF
1 +
RS

R1

I
F

N
B
R
I
D
G
E
O
S
C
I
L
L
A
T
O
R
C
I
R
C
U
I
T
U
S
I
N
G
A
N
O
P
E
R
A
T
I
O
N
A
L
A
M

Oscill
ator
stabil
izatio
n
takes
on
many
form
s. It
must
be
preci
sely
set,
other
wise
the
ampli
tude
will
eithe
r
dimin
ish or
reac
h
some
form
of
limiti
ng
with
high
level
s of
distor
tion.
The
elem
ent,
RS,

is
com
monl
y
repla
ced
with
some
varia

ble
resist
ance
elem
ent.
Thus
,
throu
gh
some
contr
ol
mea
ns,
the
value
of
RS is

adjus
ted
to
maint
ain
const
ant
oscill
ator
outp
ut. A
FET
chan
nel
resist
ance,
a
ther
misto
r, a
lamp
bulb,
or
other
devic
e
whos
e
resist
ance
incre
ases
as
the
outp
ut
ampli
tude
is
incre
ased

eases
, the
zener
diode
imped
ance
decre
ases
resulti
ng in
more
feedb
ack
with
conse
Fig quent
ure reduct
22 ion in
sho gain;
ws thus
anotstabili
her zing
me the
ans amplit
of ude of
stab the
ilizi output
ng signal.
the Furthe
osci rmore,
llato this
combi
r
with nation
a of a
zen monol
er ithic
diod zener
e diode
shu and
ntin bridge
g rectifi
the er
feedcircuit
bac tends
k to
resi provid
stor e a
(RF zero
of tempe
Fig rature
ure coeffic
21). ient
As for
the this
out regula
put ting
sign syste
al m.
am Becau
plitu se this
de bridge
incr rectifi
are
a
fe
w
of
the
ele
me
nts
oft
en
util
ize
d.

er
syste
m has
no
time
const
ant,
i.e.,
therm
al
time
const
ant for
the
lamp
bulb,
and
RC
time
const
ant for
filters
often
used
in
detect
or
netwo
rks,
there
is no
lower
freque
ncy
limit.
For
exam
ple,
with
1 F
polyca
rbonat
e
capaci
tors
and
22M
for the
freque
ncy
deter
minin
g
netwo
rk, the
operat
ing
freque
ncy is
0.007
Hz.
As

the ch a

OUTPUT

fre slew
qu rate

C2

en of
cy

appro

is

ximat

inc ely

R1

rea 9V/

1000pF

1000
pF

se s
d, when

ud
e
mu
st
be
red
uc
ed
to
pre
ve
nt
the
out
put
sig
nal
fro
m
be
co
mi
ng
sle
wrat
e
limi
ted
.
An
out
put
fre
qu
en
cy
of
18
0k
Hz
will
rea

0.1 F
6
SUBSTRATE

CA3109
DIODE
ARRAY

OF CA3019

7.5k

W
I
E
N
B
R
I
D
G
E
O
S
C
I
L
L
A
T
O
R
C
I
R
C
U
I
T
U
S
I
N
G
C
A
3

3.6k
500

7
0.1 F

50Hz, R = 3.3M

FIGURE 22.

0.1 F

100Hz, R = 1.6M
1kHz, R = 160M
10kHz, R = 16M
30kHz, R = 5.1M

16VP

-P.

THD <0.3%

R1 = R2 = R

put tude
am is
plit

7
3 +
CA3140

-15V

the its
out ampli

19VP-P TO 22VP-P

+15V

R2

1
3

s
the
0 read
out
Sim amp
ple lifier
Sa for
mpl the
e- stor
and age
cap
Hol acit
or.
d
The
Sys
CA3
tem
080
Fi A
g serv
ur es
e as
2 both
3 inpu
s t
h buff
o er
w amp
s lifier
a and
ve low
ry feed
si m thro
pl ugh
e tran
s smi
a ssio
m n
pl swit
e- ch
a (see
n Not
d- e
h 13).
ol Syst
d em
sy offs
st et
e nulli
m ng
u is
si acc
n omp
g lish
th ed
e with
C the
A CA3
3 140
1 via
4 its
0 offs
a et
1
4

nulli
ng
term
inal
s. A
typi
cal
sim
ulat
ed
load
of
2k
and
30p
F is
sho
wn
in
the
sch
ema
tic.
0

30k

SAMPLE

STROBE

-15

1N914
+15V
1N914
INPUT

2k

3
2

+15V

+
CA3080A

0.1 F
2k

200pF

0.1 F
7

+
CA3140

5
-15V
200pF
400

3.5k

0.1
F

100k
-15V

C1
2k

0.1 F
30pF
SIMULATED LOAD
NOT REQUIRED

FIG
UR
E
23.
SA
MP
LE
AN
D
HO
LD
CIR
CUI
T

In
this

2k

HO

circ
uit,
the
sto
rag
e
co
mp
en
sati
on
ca
pa
cita
nc
e
(C

vide
longe
r
hold
perio
ds
but
with
slowe
r
slew
rates.
The
slew
rate
is:
dv

dt

1) NOTE:
is
13. A
onl
N6
y
66
20
8
0p
A
F.
pp
Lar
lic
ati
ger
on
val
s
ue
of
ca
th
pa
e
cito
C
rs
A3
pro
08

15

0
an
d
C
A
30
80
A
Hi
gh
Pe
rfor
m
an
ce
O
I

pe
rat
io
na
l
Tr
an
sc
on
du
ct
an
ce
A
m
pli
fie
rs
.

CA3140, CA3140A
Puls
e
dro
op
duri
ng
the
hold
inter
val
is
170
pA/
200
pF
whic
h is
0.85

V/
s;
(i.e.,
170
pA/
200
pF).
In
this
cas
e,
170
pA
repr
ese
nts
the
typi
cal
leak
age
curr
ent
of
the
CA3
080
A
whe
n
stro
bed
off.

If C1
were
increa
sed to
2000p
F, the
holddroop
rate
will
decrea
se to
0.085
V/
s, but
the
slew
rate
would
decrea
se to
0.25V/
s.
The
paralle
l diode
networ
k
conne
cted
betwe
en
Termin

input

termin
als of
the
CA308
0A to
the
200pF
storag
e
capaci
tor
when
the
CA308
0A is
strobe
d off.
Figure
24
shows
dynam
ic
charac
teristic
wavefo
rms of
this
sampl
e-andhold
system
.

al 3 of
the
CA308
0A
and
Termin
al 6 of
the
CA314
0
preven
ts
large
input
signal
feedth
rough
across
the

Top
Trac
e:
Out
put;
50m
V/Di
v.,
200
ns/D
iv.

Bot /Di
tom v.
Center Trace: Tra
ce:
D
Inp
i
ut;f
50f
mV
e
/Div
r
.,
e
200
n
ns/
c
Div.
e

A
m
p
l
i
f
i
e
r
7
A
1
3

f
5
I

i
v

T
d
o
p
Tu
rt
ap
cu
et
:

Oi
u
g
t
n
p
a
u
l
t
s

S
i t
gh
nr
ao
l u
; g
h

5
VT
/
e
D
k
i
t
v
r
,
o

2n
i
x

s
/
D
i
v
.

Botto
m
Trac
e:
Input
Sign
al;
5V/D
iv.,
2
s/Div
.
L
A
R
G
E
S
I
G
N
A
L
R
E
S

PD
O
NH
S
O
E
L
A
ND
D
SS
EY
TT
S
LI
NT
GE
M
TI
M
ED
Y
N
A
M
I
C
C
H
A
R

SAMPLING
A
RESPONSE
C
T
Top
Trace:
E
Output
R
;
I
100mV
S
/Div.,
T
500ns/
Div.
I

Bot
C
tom
S
Tra
ce:
W
Inp
A
ut;
20
V
V/D
E
iv.,
F
500
O
ns/
R
Div.
M

FIGURE 24.
S
A
M
P
L
E
A
N

Curr
ent
Ampl
ifier
The
low
input
term
inal
curr
ent
nee
ded
to
drive
the
CA3
140
mak
es it
ideal
for
use
in
curr
ent
ampl
ifier
appli
catio
ns
such
as
the
one
sho
wn
in
Figu
re
25
(see
Note
14).
In
this
circu
it,
low
curr
ent
is
supp
lied
at
the
input
pote
ntial

as
th
e
po
w
er
su
pp
ly
to
lo
ad
re
si
st
or
R

L.

T
hi
s
lo
ad
cu
rr
en
t
is
in
cr
ea
se
d
by
th
e
m
ult
ipl
ic
ati
on
fa
ct
or
R

2/
R
1,
w
he
n
th
e
lo
ad
cu
rr

ent
is
mon
itore
d by
the
pow
er
sup
ply
met
er
M.
FIGURE
Thu
s, if
the
load
curr
ent
is
100
nA,
with
valu
es
sho
wn,
the
load
curr
ent
pres
ente
d to
the
sup
ply
will
be
100
A;
a
muc
h
easi
er
curr
ent
to
mea
sure
in
man
y
syst
ems
.

IL x

R2
R1

M
POWER
SUPPLY

4.3k
-15V

25.
BAS
IC
CUR
REN
T
AMP
LIFI
ER
FOR
LO
W
CUR
REN
T
MEA
SUR
EME
NT
SYS
TEM
S

Note
that
the
input
and
outp
ut
volta
ges
are
tran
sferr
ed
at
the
sam
e
pote
ntial
and

CA3140
2

5
100k

0.1 F
6
0.1 F

10M

IL
RL

on ho

Es

ly

se

th

nti

me

ally

ou tho

tp

the

ut

of

ne

cu de

ce

rr

ss

co

en upl

ary

ing

hig

is

the

cir

fre

ult cui

qu

ipl t

en

ie

fro

cy

fee

by the

db

th

eff

ac

ect

k is

sc s

pro

al

of

vid

hig

ed

fa

by

ct

out

the

or. put

ca

loa

pa

cit

ca

or

pa

wit

cit

an

the

ce

dot

an

ted

ser

the

ies

pot

res

ent

ist

ial

or

os

pro

cill

vidi

ati

ng

on

loa

in

thi

de

co

sit

upl

uat

ing

ion

T
h
e
d
o
t
t
e
d
c
o
m
p
o
n
e
n
t
s
s

Full orms
Wa .
ve Duri
Rec
ng
tifie
posit
r
Fi
gu
re
26
sh
o
w
s
a
si
ng
le
su
pp
ly,
ab
so
lut
e
va
lu
e,
id
ea
l
ful
lw
av
e
re
cti
fie
r
wi
th
as
so
ci
at
ed
w
av
ef

inver
ting
ampl
ifier
in a

ive

nega

excu

tive

rsion

goin

s,

the

excu

input

rsion

sign

such

al is

that

fed

the

thro

1N9

ugh

14

the

diod

feed

back

effec

netw

tively

ork

disc

direc

onne

tly to

cts

the

the

outp

ampl

ut.

ifier

Sim

from

ultan

the

eous

sign

ly,

al

the

path.

posit

Duri

ive

ng a

excu

nega

rsion

tive

of

goin

the

input

excu

sign

rsion

al

of

also

the

drive

input

s the

sign

outp

al,

ut

the

termi

CA3

nal

140

(No.

funct

6) of

ions

the

as a

normal
invertin
g
amplifie
r with a
gain
equal
R/R .
to When

2
1

t
h
e
e
q
u
a
l
i
t
y
o
f
t
h
e

g
u
r
e

ns

2
6

Gr

,
J.
G.
ae
m

i
s

e,

satisfi
ed,
the
full
wave
output
is
symm
etrical
.

NOTE:

ny,

14. O

t
w
o

pe

e
q
u
a
t
i
o
n
s

na

s
h
o
w
n

es

i
n

Ap

rat
io
l
A
m
pli
fie
rs
D
ig
n
an
d
pli
ca

F
i

tio

16

cG
ra
wHil
l
Bo
ok
Co
m
pa
pa
ge
30
8,
N
eg
ati
ve
Im
mi
tta
nc
e
Co
nv
ert
er
Cir
cui
ts
.

CA3140, CA3140A
R2

+15V
+15V

5k
R1

0.1 F

10k

INPUT

CA3140

0.1 F

1N914

R3

FOR X
R

1 X

6
100pF

2k

BW (-3dB) = 4.5MHz
SR = 9V/ s

2k
0.05 F

R1R2 + R3

CA3140

SIMULATED
LOAD

0.1 F

2
X+X

-15V

R3

= X=

PEAK
ADJUST
10k

100k
OFFSET
ADJUST

R2

3
2

10k

GAIN =

10k

FIGURE 28A. TEST CIRCUIT

5k
=0.5 =

R2

R1
10k
0.75 =15k
=10k
3
0.5

20VP-P Input BW (-3dB) = 290kHz, DC Output (Avg) = 3.2V

FIGURE 27. TEST CIRCUIT
AMPLIFIER (30dB GAIN)
USED FOR

OUTPUT
0
INPUT
0

WIDEBAND
NOISE
MEASUREME
NT

Top Trace: Output;

50mV/Div.,
200ns/Div.
Bottom Trace: Input;
50mV/Div., 200ns/Div.
FIGURE 28B.
SMALL SIGNAL
RESPONSE

FIGURE 26. SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL

WAVE RECTIFIER WITH

ASSOCIATED WAVEFORMS
+15V

0.01 F

CA3140

1M
2

NOISE VOLTAGE
OUTPUT

4
0.01 F

30.1k

-15V
BW (-3dB) = 140kHz
TOTAL NOISE VOLTAGE
(REFERRED TO INPUT ) = 48 V (TYP)

1k

(Measurement made with

Tektronix 7A13 differential
amplifier.)
Top Trace:

Output Signal; 5V/Div., 5 s/Div. Center Trace:

Difference Signal; 5mV/Div., 5 s/Div. Bottom Trace:
Input Signal; 5V/Div., 5 s/Div.

FIGURE 28C. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING

SETTLING TIME

CIRCUIT

FIGURE 28. SPLIT

AND

SUPPLY

ASSOCIA

VOLTAGE

TED

FOLLOWE

WAVEFO

R TEST

RMS

17

CA3140, CA3140A
Typical Performance Curves
C

GAIN BANDWIDTH PRODUCT (MHz)

20

OPEN -LOOP VOLTAGE GAIN (dB)

RL = 2k

125
100
75
50
25

RL = 2k

10

T = -55
A

S
U
P
P
L
Y

1
0

0
0

CL = 100pF

SUPPLY VOLTAGE (V)V

10

SUPPLY VOLTAGE (V)

FIGURE 30.
FIGURE 29. OPEN-LOOP
VOLTAGE
GAIN vs

T
G

SUPPLY

VOLTAGE
AND
TEMPERAT

URE

R
A

CL = 100pF

SLEW RATE (V/ s)

20

RL = 2k U
P

10

0
0

FIGURE 31. SLEW

RATE vs

V
O
L
T
A
G
E
:
V

E
V

15

5E

A
N

S
=

S
U
P
P
L

1
5
V
T

A
=
2
5
o
25
OUTPUT SWING (V PP-)

20
15
10
5
0
10K

100K
FREQUENCY (Hz)

1M

4M

RL =
QUIESCENT SUPPLY CURRENT (mA)

OUTPUT
VOLTAGE
SWING vs
FREQUEN
CY

A
T

R
E

3
2
1
0

SUPPLY
VOLTAGE (V)

Q
UI
E
S
C
E
N
T
S
U
P
P
L
Y
C
U
R
R
E
N
T
vs
S
U
P
P
L
Y
V
O
LT
A
G
E
A
N
D
T
E
M

E
R

FIGURE 32.

COMMON-MODE REJECTION RATIO (dB)

FIGURE 33. MAXIMUM

120
100
80
60
40
20
0
10
FREQUENCY (Hz)

FIGURE
34.
COMMON
MODE
REJECTI
ON
RATIO vs
FREQUE
NCY

18

CA3140, CA3140A
Typical Performance Curves

(Continued)

ENT INPUT

SUPPLY VOLTAGE: VS = 15V

o
T
= 25 C

NOISE

SUPPLY VOLTAGE: VS =
o
VOLTAGE
TA = 25 C

POWER SUPPLY REJECTION RATIO (dB)

EQUIVALENT INPUT NOISE VOLTAGE (nV/ Hz)

1000

vs

FREQUENC
Y

100

10

1
1

10

10

+PSRR

80
60

40
20
0

-PSRR

POWER SUPPLY REJECTION RATIO

(PSRR) = VIO/ VS

10

10

10

FREQ
UENC
Y (Hz)

FRE
QUE
NCY
(Hz)

FIGURE 36. POWER

SUPPLY REJECTION
RATIO vs
FREQUENCY

FIGURE 35.
EQUIVAL

Metallization
Mask Layout

100

Dimensions in parenthesis
are in millimeters and are
derived from the basic inch
dimensions as indicated.
Grid graduations are in
61

mils (10

60

The
photographs
and
dimensions represent a
chip when it is part of the
wafer. When the wafer is
cut into chips, the cleavage

19

angles
are
o
57 instead

of 90 with
respect to
the face of
the
chip.
Therefore,
the isolated
chip
is
actually
7
mils
(0.17mm)
larger
in
both
dimensions.

10

10

10

10