Cairo University

Faculty of Engineering

Department of Electronics and

Communications Engineering

ELC401A Fall 2014

Problem Set II
Problem (1)

For the previous circuit, find the region of operation of each transistor while varying the input Vin from 0
to VDD. Find the output range for proper operation (Vout tracks Vin).

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Problem (2)

For the previous circuit:

1- Find the relation between IREF1, IREF2 and IREF3.
2- Assume output load capacitance CL at Vout, find the exact expression of the Gain-Bandwidth
product (GBW) in terms of the circuit parameters.
3- Find the maximum output range as a function of Vb1 and Vb2.
4- Find the values of Vb1 and Vb2 for maximum output swing.

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Problem (3)

Compare between the two circuits in terms of:

1- DC-gain
2- GBW (assume a load capacitance CL)
3- Maximum available output swing.

Problem (3)

Find the Rout of the first circuit and hence find the Gm and Av of the second circuit.

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Problem (4)
For the two-stage opamp below, VDD = 2.5V, nCox=100A/V , , pCox=50A/V and for a total power
consumption of 6mW, find the maximum GBW for a load capacitance of CL = 1pF and such that the nondominant pole is double the GBW product. For this value, find the DC-gain and the maximum output
swing.
Assume: VOD5=VOD6 and VOD1=VOD3

Problem (5)
Find the DC-gain of the following opamp circuit.

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Problem (6)

VDD
M3

M4

Vb

M5

M6
Cc

Cc
Vout+

CL

Vout-

Vin+

M1

M2

CL

Vin-

RS
ISS2

CS

ISS1

CS

ISS2

In the differential amplifier shown above, the first stage is a degenerated differential pair and
the second stage is a common-source stage. The circuit is fully differential (i.e. half-circuit model is
applicable). Assume the following parameters:
1 , 01 for transistors 1 and 2 ,
3 , 03 for transistors 3 and 4,
and 5 , 05for transistors 5 and 6.

a. Find the Transconductance and Output Resistance for the first stage.
b. Find the total gain of the differential amplifier.
c. Ignoring CS, find all possible poles in the system and find the gain-bandwidth-product (GBW) of
the circuit.
d. This two-stage amplifier is compensated using a miller compensation capacitor CC and an ideal
unity-gain buffer. Compare between the zero location of this architecture and zero location of
the architecture without the unity-gain buffer.
e. Find the zero location due to CS.

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Problem (7)
Find all zeros and poles of the circuit and locate them on the s-plane. Assume that the capacitors shown
are the only capacitors in the circuit.

Mp1

Mp2

CC

VDD
Mp3

jw

C1
Vin1

Mn1

Mn2
I1

Vout

Vin2

CL
I2

Problem (8)
Find the output resistance ( ) and transconductance ( ) of the following fully-differential
circuit (do not ignore output resistance of transistors), = 1 2 .

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Problem (9)
C1
gm2 , ro2

gm1p , ro1p

Vout
Vin

gm1N , ro1N
rCM

Iss

Cc

CL
Ib

In the two-stage opamp, while ONLY considering the parameters and capacitors in the figure. Find the
following and fill in your results in the boxes below:
(a)
(b)
(c)
(d)

Overall DC-gain ( )
Gain-Bandwidth Product ()
Non-dominant pole ( )
Transmission Zero ( )

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