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k. It requires a signal +5V power supply and operates at 3.2 MHZ single phase
clock.
l. It is enclosed with 40 pins DIP (Dual in line package).
8085 HARDWARE ARCHITECTURE:
8085 consists of various units and each unit performs its own functions. The
various units of a microprocessor are listed below
Programmable Registers:
The general purpose registers are used to store the temporary information during
the execution of a program.
There are six other general purpose registers in 8085 namely B, C, D, E, H and L.
these are used for various data manipulators. Each is 8-bit registers.
A pair of register together can be used as a register pair to hold 16-bit. There are
BC, DE and HL register pair.
Temporary Register: (W, Z)
It is not available for user
All the arithmetic and logical operations are done in the temporary register
but user cant access it.
Special Purpose Registers:
There are two special purpose register in 8085. They are
SP-Stack Pointer -16 bit
PC-Program Counter 16 bit
Flag register 8 bit
Program Counter:
It is a 16 bit register used to point the location from which the next instruction is to
be fetched
When a single byte instruction is executed PC is automatically incremented
by 1.
Upon reset PC contents are set to 0000H and next instruct is fetched
onwards.
Stack Pointer:
This is a temporary storage memory 16 bit register. Since there are only 6 general
purpose registers, there is a need to reuse them.
The 8085 maintains stack in memory
Whenever stack is to be used previous values are pushed on stack and then
after the program is over these values are popped back.
Flag register:
It is a group of 5 flip-flops used to know status of various operations done
The flag register along with the accumulator is called PSW
PSW- Program Status Word
Flag register is given by:
7
S
0
Z
AC
CY
Instruction Register:
When an instruction is fetched, it is executed in instruction register. This register
takes the op-code value only
Instruction Decoder:
It decodes the instruction from instruction register and then to control block.
Timing and Control:
It accepts clock input from external crystal source.
This is the control section of microprocessors.
It produces required control signals for all the operations with suitable timing.
Interrupt Control:
There are five interrupt request pins through which the 8085 may be interrupted.
These are 1) TRAP, 2) RST 5.5, 3) RST 6.5, 4) RST 7.5 and
5) INTR.
Serial I/O Control:
This section is used for Serial data communication.
The Microprocessor can send data to external devices using SOD (Serial Output
Data) pin.
The Microprocessor can receive data from external devices using SID (Serial Input
Data) pin.
The serial communication can be performed by using SIM and RIM instructions.
SIM - Set Interrupt Mask
RIM - Read Interrupt Mask
Pin
Name
AD0
AD7
No.
of
Pins
8
A8 A15
ALE
RD
WR
IO/M
S0, S1
READY
SID
SOD
Description
Multiplexed Low order Address and Data lines;
Lower 8 bits of the memory address or I/O address
appear on the bus during first T state of the
machine cycle. It then becomes the data bus during
the 2nd and 3rd T states.
High order Address lines; These lines are used to
address the most significant 8-bitsofmemory address
or the 8-bits of the I/O address.
Address Latch Enable goes high when operation is
started by processor. It occurs during the first T
state of a machine cycle and enables the address to
get latched into the on-chip latch.
Read is active low input signal used to read data
from I/O device or memory
Write is active low output signal used to write data
on I/O device or memory
Input/Output or Memory Indicator signal used to
indicate whether 8085 is working i I/O mode (I/O
=1) or memory mode (I/O =0).
Bus State Indicator used to indicate type of operation
Type
Bidirection
al Tristate
Output,
Tristate
Output,
Tristate
Output,
Tristate
Output,
Tristate
Output,
Tristate
Output
HOLD
HLDA
INTR
TRAP
RST 5.5
RST 6.5
RST 7.5
INTA
RESET
IN
RESET
OUT
X1 , X 2
CLK
(OUT)
Vcc , Vss
Input
Output
Input
Input
Input
Hardware vectored interrupt request;
These interrupts have a higher priority than INTR Input
and they may be individually masked out using the
Input
SIM instruction.
INTERRUPT ACKNOWLEDGE; is used instead
of (and has the same timing as) RD during the
instruction cycle after an INTR is accepted.
System reset; Reset sets the Program Counter to
zero and resets the Interrupt Enable and HLDA flipflops. None of the other flags or registers (except the
instruction register) are affected The CPU is held in
the reset condition as long as Reset is applied.
Peripherals reset; Indicates CPU is being reset. The
signal is synchronized to the processor clock.
These are clock signals and are connected to
external LC or RC circuits. These are divide by two
so if 6 MHZ is connected to X1, X2 the operating
frequency becomes 3 MHZ
Clock Signal is used as System clock also used to
synchronize all the devices which are connected with
the processor. The period of CLK is twice the X1, X2
input period.
Power supply Vcc = +5 volts, Vss = -GND reference
Output
Input
Output
Input
Output
The 8085A uses a multiplexed Data Bus. The address is split between the
higher 8bit Address Bus and the lower 8bit Address/Data Bus.
During the first cycle the address is sent out. The lower 8bits are latched into
the peripherals by the Address Latch Enable (ALE). During the rest of the
machine cycle the Data Bus is used for memory or l/O data.
The 8085A provides RD, WR, and lO/Memory signals for bus control.
An Interrupt Acknowledge signal (INTA) is also provided.
Hold, Ready, and all Interrupts are synchronized.
The 8085A also provides serial input data (SID) and serial output data
(SOD) lines for simple serial interface.
In addition to these features, the 8085A has three maskable, restart interrupts
and one non-maskable trap interrupt. The 8085A provides RD, WR and
IO/M signals for Bus control.
Status Information
Status information is directly available from the 8085A. ALE serves as a status
strobe. The status is partially encoded, and provides the user with advanced timing
of the type of bus transfer being done. IO/M cycle status signal is provided directly
also. Decoded So, S1 Carries the following status information:
HALT, WRITE, READ, FETCH
S1 can be interpreted as R/W in all bus transfers. In the 8085A the 8 LSB of
address are multiplexed with the data instead of status. The ALE line is used as a
strobe to enter the lower half of the address into the memory or peripheral address
latch. This also frees extra pins for expanded interrupt capability.
Interrupt and Serial l/O
The8085A has5 interrupt inputs: INTR, RST5.5, RST6.5, RST 7.5, and
TRAP.
INTR is identical in function to the 8080 INT.
Each of the three RESTART inputs, 5.5, 6.5. 7.5, has a programmable mask.
TRAP is also a RESTART interrupt except it is nonmaskable.
The three RESTART interrupts cause the internal execution of RST (saving
the program counter in the stack and branching to the RESTART address) if
the interrupts
are enabled and if the interrupt mask is not set.
The non-maskable TRAP causes the internal execution of a RST
independent of the state of the interrupt enable or masks.
Since a number of memory chips can be connected and the use of memory
space can be planned based on application, there would be the necessity of
generating a chip select signal for the memory chip where the Read/Write
operation is to be performed. This is done by decoding the address bits and
determining the chip where the specified memory address is located.
Lower order data bus and address bus are multiplexed on same lines ie., AD 0
to AD7
De-multiplexing refers to separating address & data signals for read/write
operations
Memory Interface:
The memory us made up of semiconductor material used to store the programs and
data. The types of memory is
Primary or main memory
Secondary memory
Primary Memories
: RAM, ROM
Secondary Memories
: floppy, Hard disc, CD-ROM, Magnetic tape
Interface with multiple chip:
In case of multiple chips decoder circuits like 3 to 8 decoder circuit 74LS138 are
used to produce chip solid signal. These circuits are called address decoders.
I/O PORTS:
Interfacing I/O devices:
Using I/O devices data can be transferred between microprocessor and the
outside world
This can be done in groups of 8 bits using the entire data bus. This is called
parallel I/O
The other method is serial I/O where one bit is transferred at a time using the
SID and SOD pins on the microprocessor
Types of parallel interface:
There are two ways to interface 8085 with I/O devices in parallel data
transfer mode
Memory mapped IO
IO mapped IO
Memory mapped IO:
It considers them like any other memory location.
They are assigned a 16 bit address within the address range of the 8085.
The exchange of data with these devices follows the transfer of data with
memory. The user uses the same instructions used for memory.
there will be confusion between memory location and I/O device. If we sacrifice
some memory locations for the sake of I/O devices, this problem would not arise.
It means that the I/O address and memory addresses wil not be the same.
Since an I/O device is treated as memory location this interface is called memory
mapped I/O.
This is called I/O mapped I/O interface since I/O devices are treated separately
from memory
DATA TRANSFER CONCEPTS:
Data Transfer Schemes depend heavily on the environment (online or offline
proceeding), type of I/O device, (capable of parallel or serial data transfer,
synchronous or asynchronous) and the application. Data transfer schemes may be
categorized as shown below
The data transfer between two processor will be in serial mode. The data is
transferred bit by bit on a single line. This minimizes the number of
interconnecting lines. The microprocessor providing the serial data transfer facility
will have two pins for input and output of serial data and special software
instructions to affect the data transfer
8085 Timing Diagrams:
The graphical representation of the instruction execution in steps with respect to
the time (clock signal) is called timing diagram
During normal operation the microprocessor sequentially fetches, decodes and
executes one instruction after another until a Halt Instruction (HLT) is executed.
The fetching decoding and execution of a single instruction constitutes an
instruction cycle, which consists of one to five read or write operations between
processor and memory or input/output devices.
Each memory or I/O operations require a particular time period called machine
cycles. Each machine cycle consists of 3 to 6 clock periods/cycles referred to as 7
states
There are seven different machine cycles in 8085A
Op-code fetch
Memory read
Memory write
I/O read
I/O write
INTR acknowledge
Bus idle
Representation of Signals:
Clock Signal:
Single Signal:
Group of Signals:
8085 Timing Diagrams:
The graphical representation of the instruction execution in steps with respect to
the time (clock signal) is called timing diagram
The machine cycles are the basic operations performed by the processor, while
instructions are executed. The time taken for performing each machine cycle is
expressed in terms of Tstates. One T-state is the time period of one clock cycle
of the microprocessor.
The various machine cycles are
1. Op-code fetch .. - 4 / 6 T
2. Memory Read . - 3 T
3. Memory Write . - 3 T
4. I/O Read .. - 3 T
5. I/O Write . - 3 T
6. Interrupt Acknowledge - 6 / 12 T
7. Bus Idle - 2 / 3 T
Representation of Signals:
Clock Signal:
Single Signal:
Group of Signals:
The time taken by the processor to execute the op-code fetch cycle is either 4T or
6T. In this time, the first 3T-states are used for fetching the op-code from memory
and the remaining T-states are used for internal operation by the processor. The
timings of various signals during op-code fetch is shown in figure.
1. At the falling edge of first T-state(T1), the microprocessor outputs the low byte
address on AD0-AD7 lines and high byte address on A8to A15 lines. ALE is
asserted high to enable the address latch. The other control signals are asserted
as follows. IO/M=0, S0=1, S1=1.
2. At the middle of T1, The ALE is asserted low and this enables the latch to take
low byte of the address and keep on its output lines.
3. In the second T-state (T2), the memory is requested for read by asserting read
line low. When read is asserted low, the memory is enabled for placing the data
on the bus. The time allowed for memory to output the data during which read
remains low RD.
4. In the third T-state (T3), the read signal is asserted high. On the rising edge of
read signal the data is latched into microprocessor. Other control signals
remains in the same state until the next machine low.
The operation during the first two clock cycles T1 and T2 is the same as that of the
op-code fetch machine cycle. However in this case in the T 1 clock cycle the
memory address of the data byte to be read is loaded to the address bus AD 0
AD7, A8 A15
T3:
The HOLD and HLDA signals are used for direct memory access. Using DMA
bulk data transfer can take place between the memory and the I/O device by
passing the microprocessor. DMA is initiated by the external logic. It requests for a
HOLD state by inputting the HOLD signal high. The microprocessor responds by
entering the HOLD state and outputting the HLDA signal high
The signal at the HOLD pin is sampled during T2 in each machine cycle
If HOLD is high at this time HLDA is output high during T3
As soon as high but is detected at HOLD a two clock period HOLD state
initiation sequence begin. HOLD state begins at T4
The HOLD state terminates two clock periods after the HOLD signal goes
low
The 8085 has five interrupt request pins. These are TRAP, RST 7.5, RST 6.5, RST
5.5 and INTR. The locations of Interrupt Service Routine (ISR) for all interrupts
except INTR are fixed. Interrupt requests on TRAP, RST 7.5, RST 6.5, RST 5.5
cause the 8085 A to generate its own internal interrupt acknowledge instruction
and branch to respective ISRs
The 8085A samples INTR during the second last clock period of each
instructions execution.
Even though memory is not being accessed PC contents are put on the
INTERRUPTS
Interrupt is a process by which the external devices use microprocessor for
servicing by suspending the routine process served previously.
After completion of interrupt, the processor resumes its original operation.
The status of peripherals requesting service is checked frequently by the
processor and it is known as polling.
Types:
o Hardware Interrupt
o Software Interrupt
Hardware Interrupt:
When the interrupt is due to external peripheral devices then it is known as
hardware interrupts. There are 5 hardware interrupts are available in 8085 from
highest priority to lowest priority are given below.
o
o
o
o
o
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
TRAP:
It is a vectored, high priority, non maskable interrupt.
It can be disabled by any instruction.
Edge and level triggered
There are 2 ways to clear TRAP interrupt.
By resetting processor (i.e) giving a low signal on RESET IN pin.
By giving a high TRAP ACK
RST 7.5:
It is a vectored interrupt.
It has second highest priority.
Positive edge triggered and it is internally stored by DFF until it is cleared
by software interrupt.
It can be enabled or disabled by using SIM instruction
RST 6.5 & RST 5.5:
Vectored maskable interrupt.
Both are level triggered.
Can be masked using SIM instruction.
RST 6.5 has third priority whereas RST 5.5 has fourth priority.
INTR:
Maskable/Unmaskable interrupts:
Maskable interrupts are enabled and disabled under program control by
setting or resetting particular flip-flops in the processor interrupts can be
masked or unmasked resp.
In the processor those interrupts which can be masked under software
control are called maskable, whereas the interrupt which cannot be masked
under software control are called non maskable.
EI Enable Interrupt
DI Disable Interrupt
RIM Read Interrupt Mask
SIM Set Interrupt Mask