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BoundaryScanBasics

iMPACT

BoundaryScanBasics
BoundaryScan/IEEEStandard1149.1
Designcomplexity,difficultyofloadedboardtesting,andthelimitedpinaccessofsurfacemount
technologyledindustryleaderstoseekaccordonastandardtosupportthesolutionoftheseproblems.
BoundaryScan,formallyknownasIEEEStandard1149.1andmorecommonlyknownasJTAG,isprimarily
atestingstandardcreatedtoalleviatethegrowingcostofdesigningandproducingdigitalsystems.The
primarybenefitofthestandardistheabilitytotransformextremelydifficultprintedcircuitboardtesting
problems(thatcouldonlybeattackedwithadhoctestingmethods)intowellstructuredproblemsthat
softwarecanhandleeasilyandswiftly.
Thestandarddefinesahardwarearchitectureandthemechanismsforitsusetosolvetheaforementioned
problems.

Whatcanitbeusedfor?
Althoughprimarilyatestingstandardforonchipcircuitry,theproliferationofthestandardhasopenedthe
doortoawidevarietyofapplications.Thestandarditselfdefinesinstructionsthatcanbeusedtoperform
functionalandinterconnecttestsaswellasbuiltinselftestprocedures.
Vendorspecificextensionstothestandardhavebeendevelopedtoallowexecutionofmaintenanceand
diagnosticapplications.Inaddition,industrystandardextensionshavebeendevelopedtodescribe
programmingalgorithmsforreconfigurableparts.TheseextensionsareknownasIEEESTD1532andhave
beenimplementedinallXilinxdevicessince2001.
SinceIEEESTD1149.1formsthebasisofIEEESTD1532,asolidunderstandingof1149.1isbeneficial.

HowdoesIEEESTD1149.1work?
ThetoplevelschematicofthetestlogicdefinedbyIEEEStd1149.1includesthreekeyblocks:
TAPController
TheTAPControllerrespondstothecontrolsequencessuppliedthroughthetestaccessport(TAP)and
generatestheclockandcontrolsignalsrequiredforcorrectoperationoftheothercircuitblocks.
InstructionRegister
Ashiftregisterbasedcircuitseriallyloadedwiththeinstructionthatselectsanoperationtobeperformed.
TheDataRegisters
DataRegistersareabankofshiftregisterbasedcircuits.Thestimulirequiredbyanoperationareserially
loadedintothedataregistersselectedbythecurrentinstruction.Followingexecutionoftheoperation,
resultscanbeshiftedoutforexamination.

TheTestAccessPort
TheJTAGTestAccessPort(TAP)containsfourpinsthatdrivethecircuitblocksandcontroltheoperations
specified.TheTAPfacilitatestheserialloadingandunloadingofinstructionsanddata.Thefourpinsofthe
TAPare:TMS,TCK,TDIandTDO.ThefunctionofeachTAPpinisasfollows:
TCKthispinistheJTAGtestclock.ItsequencestheTAPcontrolleraswellasalloftheJTAGregisters.
TMSthispinisthemodeinputsignaltotheTAPController.TheTAPcontrollerisa16stateFSMthat
providesthecontrollogicforJTAG.ThestateofTMSattherisingedgeofTCKdeterminesthesequenceof
statesfortheTAPcontroller.TMShasaninternalpullupresistoronittoprovidealogic1tothesystemif
thepinisnotdriven.
TDIthispinistheserialdatainputtoallJTAGinstructionanddataregisters.ThestateoftheTAP
controlleraswellastheparticularinstructionheldintheinstructionregisterdetermineswhichregisteris
fedbyTDIforaspecificoperation.TDIhasaninternalpullupresistoronittoprovidealogic1tothe
systemifthepinisnotdriven.TDIissampledintotheJTAGregistersontherisingedgeofTCK.
TDOthispinistheserialdataoutputforallJTAGinstructionanddataregisters.ThestateoftheTAP
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TDOthispinistheserialdataoutputforallJTAGinstructionanddataregisters.ThestateoftheTAP
controlleraswellastheparticularinstructionheldintheinstructionregisterdetermineswhichregister
feedsTDOforaspecificoperation.Onlyoneregister(instructionordata)isallowedtobetheactive
connectionbetweenTDIandTDOforanygivenoperation.TDOchangesstateonthefallingedgeofTCKand
isonlyactiveduringtheshiftingofdatathroughthedevice.Thispinisthreestatedatallothertimes.

TheTAPController
TheJTAGTAPControllerisa16statefinitestatemachine,thatcontrolsthescanningofdataintothe
variousregistersoftheJTAGarchitecture.ThestateoftheTMSpinattherisingedgeofTCKisresponsible
fordeterminingthesequenceofstatetransitions.Therearetwostatetransitionpathsforscanningthe
signalatTDIintothedevice,oneforshiftinginaninstructiontotheinstructionregisterandoneforshifting
dataintotheactivedataregisterasdeterminedbythecurrentinstruction.

TheTAPControllerStates
TestLogicReset.ThisstateisenteredonpowerupofthedevicewheneveratleastfiveclocksofTCK
occurwithTMSheldhigh.EntryintothisstateresetsallJTAGlogictoastatesuchthatitdoesnotinterfere
withthenormalcomponentlogic,andcausestheIDCODEinstructiontobeforcedintotheinstruction
register.
RunTestIdle.Thisstateenablescertainoperationstooccurdependingonthecurrentinstruction.ForIEEE
STD1532compliantdevices,thisstatecausesgenerationoftheprogram,verifyanderasepulseswhenthe
associatedinsystemprogramming(ISP)instructionisactive.
SelectDRScan.Thisisatemporarystateenteredpriortoperformingascanoperationonadataregister
orinpassingtotheSelectIRScanstate.
SelectIRScan.Thisisatemporarystateenteredpriortoperformingascanoperationontheinstruction
registerorinreturningtotheTestLogicResetstate.
CaptureDR.Thisstateenablesdatatobeloadedfromparallelinputsintothedataregisterselectedbythe
currentinstructionontherisingedgeofTCK.Iftheselecteddataregisterdoesnothaveparallelinputs,the
registerretainsitsstate.
ShiftDR.Thisstateshiftsthedata,inthecurrentlyselectedregister,towardsTDObyonestageoneach
risingedgeofTCKafterenteringthisstate.
Exit1DR.ThisisatemporarystatethatenablestheoptionofpassingontothePauseDRstateor
transitioningdirectlytotheUpdateDRstate.
PauseDR.Thisisawaitstatethatenablesshiftingofdatatobetemporarilyhalted.
Exit2DR.ThisisatemporarystatethatenablestheoptionofpassingontotheUpdateDRstateor
returningtotheShiftDRstatetocontinueshiftingindata.
UpdateDR.Thisstatecausesthedatacontainedinthecurrentlyselecteddataregistertobeloadedintoa
latchedparalleloutput(forregistersthathavesuchalatch)onthefallingedgeofTCKafterenteringthis
state.Theparallellatchpreventschangesattheparalleloutputoftheseregistersfromoccurringduringthe
shiftingprocess.
CaptureIR.Thisstateenablesdatatobeloadedfromparallelinputsintotheinstructionregisteronthe
risingedgeofTCK.Theleasttwosignificantbitsoftheparallelinputsmusthavethevalue01asdefinedby
IEEEStd.1149.1,andtheremainingbits,ifany,arefreetobeusedforanypurpose.MostXilinxdevices
usethesebitstoindicatesecurityandinternalcontrollogicstatus.
ShiftIR.ThisstateshiftsthevaluesintheinstructionregistertowardsTDObyonestageoneachrising
edgeofTCKafterenteringthisstate.
Exit1IR.ThisisatemporarystatethatenablestheoptionofpassingontothePauseIRstateor
transitioningdirectlytotheUpdateIRstate.
PauseIR.Thisisawaitstatethatenablesshiftingoftheinstructiontobetemporarilyhalted.
Exit2IR.ThisisatemporarystatethatenablestheoptionofpassingontotheUpdateIRstateorreturning
totheShiftIRstatetocontinueshiftingindata.
UpdateIR.Thisstatecausesthevaluescontainedintheinstructionregistertobeloadedintoalatched
paralleloutputonthefallingedgeofTCKafterenteringthisstate.Theparallellatchpreventschangesat
theparalleloutputoftheinstructionregisterfromoccurringduringtheshiftingprocess.

MandatoryBoundaryScanInstructions
BYPASS.TheBYPASSinstructionenablesrapidmovementofdatatoandfromothercomponentsonaboard2/3
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BYPASS.TheBYPASSinstructionenablesrapidmovementofdatatoandfromothercomponentsonaboard
thatarerequiredtoperformtestoperations.
SAMPLE/PRELOAD.TheSAMPLE/PRELOADinstructionenablesasnapshotofthenormaloperationofa
componenttobetakenandexamined.Itenablesdatavaluestobeloadedontothelatchedparalleloutputs
oftheBoundaryScanshiftregisterpriortotheselectionofotherBoundaryScantestinstructions.
EXTEST.TheEXTESTinstructionenablestestingofoffchipcircuitryandboardlevelinterconnections.

OptionalBoundaryScanInstructions
INTEST.TheINTESTinstructionenablestestingoftheonchipsystemlogicwhilethecomponentsare
alreadyontheboard.
HIGHZ.TheHIGHZinstructionforcesalldriversintohighimpedancestates.
IDCODE.TheIDCODEinstructionenablesblindinterrogationofthecomponentsassembledontoaprinted
circuitboardtodeterminewhatcomponentsexistinaproduct.
USERCODE.TheUSERCODEinstructionenablesauserprogrammable32bitidentificationcodetobeshifted
outforexamination.Thiscanbesuedtoidentifytheprogrammedfunctionofthecomponent.
Copyright19952009,XilinxInc.Allrightsreserved.

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