Electric Power Systems Research 105 (2013) 7184

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Electric Power Systems Research

journal homepage: www.elsevier.com/locate/epsr

A generalized ultra step-up DCDC converter for high voltage

application with design considerations
Tohid Nouri, Ebrahim Babaei , Seyed Hossein Hosseini
Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran

a r t i c l e

i n f o

Article history:
Received 16 March 2013
Received in revised form 18 July 2013
Accepted 22 July 2013
Keywords:
Nonisolated DCDC converter
High voltage gain
Low voltage stress
Hybrid switching capacitor technique

a b s t r a c t
A nonisolated DCDC converter with high voltage gain and low voltage stress on switches is proposed in
this paper. For absorption of energy, n stages of diodecapacitorinductor (DCL) units are used at the
input that results in higher voltage gains. Actually, the proposed converter generalizes the voltage lift
circuit and combines it with a voltage multiplier cell. Therefore comparing to structures with one stage of
DCL unit, it will be feasible to achieve supposed voltage gain at lower duty cycles. Lower values of duty
cycle will result in increasing of converter controllability and increasing of operation region. This paper
focuses on the generalized steady state analysis of the proposed converter for three regions of operation
named as continuous conduction mode (CCM), boundary conduction mode (BCM) and discontinuous
conduction mode (DCM). Theoretical analysis and performance of the proposed converter will be veried
by both simulation and experimental results.
2013 Elsevier B.V. All rights reserved.

1. Introduction
Ever-increasing consumption of fossil fuels causes for nishing
their resources. Besides, more consumption of these resources will
lead to more environmental contamination and cost increase. Thus
use of pure and cheap energy sources has been more paid attention
by engineers [14]. As one of these sources, it can be pointed to fuel
cells. Output voltage of fuel cells is very low. Therefore in order to
produce high voltages, it is necessary to combine several of these
cells in series and parallel form. For example, for producing voltages around 100 V & 300 V, 250 & 750 cells should be connected in
series respectively. But increasing in the number of cells will lead
to decrease in efciency. Therefore for increasing of output voltage,
it will need to DCDC voltage booster converters with high gain [5].
The boost converter is the most common one for achieving this
purpose. But in practice the gain decreases at the duty cycles around
unity due to parasitic components. In addition, its control and stability at high duty cycles is very complex.
One alternative is utilizing of cascade boost converters. A cascade boost converter with soft switching (ZVS) is proposed in [6].
But the drawback is that the voltage stress on switching component is equal to high output voltage. Also quadratic converters in
[7] can achieve to high voltage gain but the drawback is that the

Corresponding author at: Faculty of Electrical and Computer Engineering, University of Tabriz, 51664 Tabriz, Iran. Tel.: +98 411 3300819; fax: +98 411 3300819.
E-mail addresses: e-babaei@tabrizu.ac.ir, babaeiebrahim@yahoo.com
(E. Babaei).
0378-7796/$ see front matter 2013 Elsevier B.V. All rights reserved.
http://dx.doi.org/10.1016/j.epsr.2013.07.012

voltage stress on switches is high yet. Thus no advantage is resulted

compared to common boost converters. Some converters based on
high frequency transformers or coupled inductors have been proposed to achieve high voltage gain without extreme duty cycles
[811]. These converters are designed based on soft switching
technique or leakage inductor energy recovery to improve efciency. However, the design of high frequency coupled inductors or
resonant components are relatively complex compared to conventional transformerless boost converters. Combining conventional
boost converters and yback converter, boost-yback converter is
achieved [12]. In this converter the leakage energy of inductors
is absorbed without losses and the voltage stress on switches is
reduced. But due to series connection of capacitors at the output,
their voltage balance should be considered. Converters with active
clamps which proposed in [13,14] can recover leakage current and
also decrease the voltage stress on main switch. Of course, the
considered advantages are achieved by implementation of more
complex circuit compared to previous ones. However more losses
are produced due to clamp circuit. Structures based on diodecapacitor voltage multiplier cells are able to solve the drawbacks
of previous converters [15,16]. The main drawback of these converters is that they cant attain to high voltage gain at duty cycles
lower than moderate values. However, cascading several voltage
multiplier cells can signicantly increase the voltage gain without a
high duty cycle operation [1719]. In [20], a converter with switching capacitors is suggested which charges n capacitors up to input
voltage and connect them in series to boost stage. Due to these
capacitors arent responsible for output voltage regulation, thus
they can operate with high efcient. However, this converter needs

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T. Nouri et al. / Electric Power Systems Research 105 (2013) 7184

several switches and the voltage stress on the last switch is equal
to output voltage. Combined structures of boost converters and
switching capacitors are investigated in [21]. But the magnitude
of output voltage is limited by the rating of switching component.
A new structure is suggested in [22] which is expandable for high
voltage applications. However negative voltage gain is the main
drawback of this converter.
Due to the aforementioned drawbacks of the boost converters
with high voltage gain, proposition of converters with high voltage gain, low voltage stress on semiconductors, low losses and
therefore high efciency is a necessary task. In [23] an interleaved
boost converter with high voltage gain is suggested which can be an
alternative to solve these objectives. This converter has a modular
structure and the output voltage and the input current ripple are
very low. Also another advantage of this converter is that the rating
of currents and voltages of the switches are reduced signicantly.
Another solution is the utilizing of relift converters [24,25]. These
converters have higher voltage gain and lower current ripple compared to the discussed previous ones. High efciency, increased
power density, simple structure and low cost are the other main
advantages of these converters. Combining this structure with voltage multiplier cells in [15,16], high voltage gain and lower voltage
stress on switches are attainable [26]. Because of low voltage stress
on switches, the use of Schottky rectier allows lower reverse
recovery current which results lower conduction losses. By applying two stages of lift circuit and an additional voltage multiplier cell
converter in [26], another high step-up transformerless converter
has been achieved [27]. The main advantages of the proposed converter are higher voltage gain and lower voltage stress across the
main switch. Extension of the suggested converter in [20] is made
by switching inductor cells for high power application in [28].
In this paper, a DCDC converter with high voltage
gain is proposed. The suggested converter uses n stages of
diodecapacitorinductor (DCL) units at the input. It is possible
to achieve high voltage gain by increasing of the stages number.
The main advantage of the proposed converter is that the voltage
stresses across the semiconductor devices remains constant at
xed voltage gains in spite of increasing n. This paper is organized
as follows:
- In Section 2, the detailed analysis of the proposed converter in
CCM, DCM and BCM is presented.
- In Section 3, design considerations for capacitors and inductors
based on the section II is discussed.
- In Section 4, input lter design and interleaving effect are discussed.
- In Section 5, real gain of the proposed converter based on real
components models is calculated.
- In Section 6, the extension of the proposed converter is given.
- In Section 7, the effect of the mismatch in inductances is analyzed.
- In Section 8, simulation and experimental results will be presented.
2. Proposed converter
Proposed converter in [26] is shown in Fig. 1. Its voltage gain is
M = Vo /Vg = (3 + d)/(1 d), where d is normalized switch Q on-time
or converter duty cycle and dened as d = Ton /T . Ton is conduction
time of switch Q and T is switching interval. Vo and Vg are output
and input voltages, respectively. The proposed converter is shown
in Fig. 2. n stages of DCL units which are inserted in truncated
line are used at the input stage of the proposed converter. Utilizing
this structure, attaining of high voltage gains is possible.
In addition voltage stress on semiconductors remains constant
or lower compared to converter of Fig. 1. In the proposed converter

VC 1

Ig Q D
1

Vg
L1

VL 2

Io

D3

C1

L2
Do1

Do 2

VL1 D
2

Vo

Co

RL

C2
VC 2

Fig. 1. Ultra step-up converter with M = Vo /Vg = (3 + d)/(1 d) proposed in [26].

during interval Ton capacitors C1 , C2 , . . ., Cn and inductors L1 , L2 ,

. . ., Ln+1 are charged by power supply. With turning off the diodes
Do1 and Do2 , capacitors Co1 and Co2 are discharged to load. When
switch Q is turned off, diodes D11 , D12 , . . ., Dn1 , Dn2 are turned off.
Capacitors C1 , C2 , . . ., Cn and inductors L1 , L2 , . . ., Ln+1 will be in series
with each other and charge the capacitors Co1 and Co2 equally that
are connected in parallel with each other. It should be noted that
the capacitors and inductors do not resonate and the capacitors
are used for voltage step-up capability. In order to simplicity of the
analysis, following assumptions have been made:
Power supply voltage is smooth and without any ripple.
Capacitors are large enough and their voltage ripple due to
switching is very low.
Three modes of operation named as CCM, BCM and DCM will be
investigated for the proposed converter.
2.1. CCM operation
Current ripple of inductors L1 , L2 , . . ., Ln+1 is negligible in this
mode and the converter performance will be analyzed at both
switching intervals in TS. The rst time interval is 0 < t < dTS in which
switch Q is on and the second one is dTS < t < TS in which switch Q
is off. Equivalent circuits of each time intervals are shown in Fig. 3.
First time interval {0 < t < dTS }: Switch Q is turned on. Diodes
D11 , D12 , . . ., Dn1 , Dn2 are forward biased. But the voltages across
diodes Do1 and Do2 , are as follows:
VDo1 = VDo2 = VCo1 Vo

(1)

Therefore these diodes are turned off. Besides, capacitors C1 , C2 ,

. . ., Cn and inductors L1 , L2 , . . ., Ln+1 will be in parallel to power

VCo1
Q

VL ( n
Cn

Dn1
C3

D31

Ig
Vg

D21
D11

VL3
C2

1)

Ln

Io

C o1
1

VCn

Vo

VC 3
L3

Co

Do1

D02

VL 2 L VC 2
2

C1

V
VL1 L C1
1

D12

D22

D32

Dn2

Co 2
V Co 2

Fig. 2. Proposed converter with n stages of DCL at input.

RL

T. Nouri et al. / Electric Power Systems Research 105 (2013) 7184

VCo1
Q

VL ( n
Cn

Dn1

Ig
Vg

D21

Ln

C o1

Vo

V
VL 3 L3 C 3

Co

C2

Do1

Ig

RL

Vg

D12

D32

Dn2

Vo
Co

C2

Do1

RL

D02

C1

V
VL1 L C1
1

Co 2

C o1
1

VL 2 L VC 2
2

D11

D22

Ln

V
VL 3 L3 C 3

D21

D02

1)

Io

VCn

C3

D31

C1

V
V L1 L C 1
1

VL ( n
Cn

Dn1

VL 2 L VC 2
2

D11

VCo1

Io

VCn

C3

D31

1)

73

D12

D22

Dn2

D32

V Co 2

Co 2
V Co 2

(a)

(b)

Fig. 3. Equivalent circuits of the proposed converter in CCM, (a) rst time interval (b) second time interval.

supply and being charged. The voltages across these components

are given by:

The currents that follow through capacitors C1 , C2 , . . ., Cn , in this

time interval are equal to:

VC1 = VC2 = = VCn = Vg

(2)

iC1,2 = iC2,2 = = iCn,2 = iL1

VL1,1 = VL2,1 = = VL(n+1),1 = Vg

(3)

Writing KVL in equivalent circuit of Fig. 3(a), voltage across

capacitors Co1 & Co2 are derived as follows:
VCo1 = VCo2 =

Vo Vg
2

The voltages across inductors are calculated as follows:

VL1,2 = VL2,2 = = VL(n+1),2 =

iL1 = iL2 = = iL(n+1)

(5)

iD11 = iL1 + iC1,1

iD12 = iL2 + iC1,1
(6)

iDn1 = iLn + iCn,1

VD1(i+1) = VD(ni)2 =

Vg + Vo
(n i), i = 0, 1, 2, ..., n 1
2(n + 1)

VD = Vo VCo1

(13)
(14)

1
Co

dTS

iC0,1 dt +
0

1
Co

Ts

iC0,2 dt = 0

(15)

dTS

In which iC0,1 & iC0,2 are the currents of capacitor Co in the rst
and second time intervals, respectively. According to Fig. 3(a):

iDn2 = iL(n+1) + iCn,1

where iC1,1 , iC2,1 , . . ., iCn,1 are currents following through capacitors
C1 , C2 , . . ., Cn during the rst time interval. According to Eq. (5) and
assuming equal values for capacitors, we have:

iC0,1 = iD Io

iD11 = iD12 = = iDn1 = iDn2 = iL1 + iC1,1

iC0,2 = Io

(7)

Switch Q current is equal to:

iQ = iL1 + iD12 + iD22 + + iDn2 iCo1,1

(8)

where ico1,1 is the current through capacitor C01 in rst time interval. Substituting Eq. (7) into Eq. (8), we can write:
iQ = (n + 1)iL1 + niC1,1 iCo1,1

(9)

Second time interval {dTS < t < TS }: In this time interval switch
Q is turned off. According to equivalent circuit of Fig. 3(b), diodes
D11 , D12 , . . ., Dn1 , Dn2 are being off. Therefore, capacitors C1 , C2 , . . .,
Cn and inductors L1 , L2 , . . ., Ln+1 will be in series to each other and
charge capacitors Co1 & Co2 which are connected in parallel. The
currents which follow through capacitors Co1 & Co2 (iCo1,2 & iCo2,2 )
and diodes Do1 & Do2 (iDo1,2 & iDo1,2 ) can be expressed as:
iCo1,2 = iCo2,2 = iD01 = iD02 =

(12)

which turn these diodes off.

Now the current through diode D and capacitors C1 , C2 , . . ., Cn are
calculated in the rst time interval. The average current of capacitor
Co in a switching period is zero:

The diodes D11 , D12 , . . ., Dn1 , Dn2 currents are given by:

..
.

nVC1 VCo1
n+1

The voltages across diodes D11 , D12 , . . ., Dn1 , Dn2 are equal to:

(4)

If the inductors L1 , L2 , . . ., Ln+1 are equal then following relation

can be written for their currents:

(11)

iL1
2

(10)

(16)

which Io is load current. Besides, referring to Fig. 3(b):

(17)

Substituting Eqs. (16) and (17) into Eq. (15) and after some
manipulation, following expression is derived for average current
through diode D during second time interval:
iD = Io
d

(18)

Furthermore average values of iC01 & iC02 during the rst time
interval is equal to:
iCo1 = iCo2 = Io
d

(19)

Charge balance of capacitors C1 , C2 , . . ., Cn during a switching

period is as below:
1
Ci

dTS

iCi,1 dt +
0

1
Ci

Ts

iCi,2 dt = 0 for i = 1, , n
dTS

(20)

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T. Nouri et al. / Electric Power Systems Research 105 (2013) 7184

Table 1
Comparison between the proposed transformerless converter and some transformer
based converters in the literature.

TS

V L1 ,

, VL n

Toff

Ton

Vgate

t
1

Vg

Proposed converter with n = 3

Proposed converter with n = 2

Conventional yback converter

(nVC1 VC o1 ) /(n 1)

Proposed converter in [8]

iQ
(n 1)iL1 niC1 iCo1

Proposed converter in [11]

iD11 , , iDn 2
iL1 iC1

iD , iDo1
I L1 / 2
Io / d

iC1, , iCn
iL1 (1 d ) / d

t
iL1
iCo1
I L1 / 2

Io / d
Fig. 4. Key waveforms of the proposed converter in CCM.

VQ,pu =

Referring to Fig. 3(b), we can write:

iCi,2 = iL1 for i = 1, , n

1d
d
iL1 = iL1
d
d

(22)

which d is dened as Toff /TS in Eq. (22) and Toff is the duration of
the second time interval.
Based on the aforementioned analysis, the key waveform of the
proposed converter in a switching period is shown in Fig. 4. The
average value of inductors voltages in each switching period is zero.
Thus, using Eqs. (3) and (12):

dTS

Ts

Vg dt +
0

dTS

 nV V 
C1
Co1
n+1

18
4
6
13

1 + MCCM
2MCCM

(25)

2.2. DCM operation

Equivalent circuit of the proposed converter in DCM in third
time interval [(d + d2 )TS < t < TS ] is shown in Fig. 6. d2 is the required
normalized time that is terminated from the start of time interval
t1 < t < t2 until inductors currents reach to zero. Current of inductor
L1 (iL1 ) in DCM is shown in Fig. 7. As can be seen, inductor current
reaches to zero and remains to this value until the switch Q is
turned on.
Knowing that the average voltage across the inductor L1 in a
switching period is zero, following expression is derived for d2 :
d2 =

dt = 0

(23)

Ig
Vo
2n + d + 1
2n + d + 1
=
=
=
Vg
Io
1d
d

2(n + 1)dVg
Vo (2n + 1)Vg

(26)

80

According to the considerations, the variation of capacitor voltage during switching intervals is negligible. Thus, substituting Eqs.
(2) and (4) into the Eq. (23) and simplication, voltage gain of the
proposed converter (MCCM) in CCM is obtained as below:
MCCM =

21

(21)

Substituting Eq. (21) in Eq. (20) and assuming that iL1 and iCi,1 are
equal to their average values in the corresponding time intervals,
the following relation for iCi,1 is obtained:
iCi1 =

Components number

7+d
1d
5+d
1d
Nd
1d
1+N
1d
N(2d)
1d

proposed converter in [11] with N = 4 has higher voltage gain compared to the proposed converter with n = 2. For the duty cycles
higher than 0.57, the proposed converter with n = 2 has higher voltage gain in comparison with the converters in the literatures. As can
be seen from Table 1, the proposed converter with n = 2 and n = 3
uses higher number of components compared to other competitors. However, the voltage gain of the proposed converter is higher
and the structure is simple. The voltage gain in the transformer
based solutions can be increased by transformer turns ratio (N).
However, using high-voltage transformers with a large turns ratio
introduces several problems such as leakage inductance and the
parasitic capacitance formed by the secondary winding of the transformer, which causes voltage and current spikes and increases loss
and noise that can signicantly degrade the system performance
and damage circuit components. Although active clamp circuit can
be used to recover the leakage energy, but the circuit complexity
will be increased.
The per unit (based on the output voltage Vo ) voltage across
switch Q can be calculated as below:

(24)

It can be seen from Eq. (24) that increasing DCL unit number will result in higher voltage gains. Table 1 shows a comparison
between the proposed transformerless converter and some transformer based converters in the literature in the case of voltage gain
and component number. It should be noticed that n is the stages
number for the proposed converter and N is the transformer turn
ratio for the transformer based converters in the literature. The
voltage gain (M) of the competitors versus duty cycle (d) is shown
in Fig. 5. As can be seen the proposed converter with n = 3 has the
highest voltage gain of all. For the duty cycles lower than 0.57 the

Proposed converter with n=2

proposed converter with n=3
Conve ntional flyback converte r with N=3
Conve ntional flyback converte r with N=4
Proposed converter in [8] with N=3
Proposed converter in [8] with N=4
Proposed converter in [11] with N=3
Proposed converter in [11] with N=4

70
60
Voltage gain (M)

iDo1
iD

Voltage gain (M)

50
40
30
20
10
0
0.1

0.2

0.3

0. 4

0. 5

0. 6

0.7

0.8

0.9

Duty cycle (d)

Fig. 5. Comparison of voltage gain of the proposed transformerless converter and
some transformer based converters.

T. Nouri et al. / Electric Power Systems Research 105 (2013) 7184

iL1

75

nVC1 VCo1
(n 1) L1

Vg
L1

I L1

t
DTS

TS

Fig. 8. Current of inductor L1 in BCM.

where ig,1 is the input current during rst time interval and is given
by:
Ig = niL1 + iL1,on + Io

(33)

iL1,on in Eq. (33) is the average value of the inductor current in

the rst time interval and can be written as follows:
2
iL1,on = d TS Vg
2L1

Fig. 6. Equivalent circuit of the proposed converter in DCM.

Having d2 and referring to Fig. 6, the average value of iL1 (iL1 ) is

equal to:



iL1 = IL1 = 1
TS
=

dTS

(d+d2 )TS

iL1,1 dt +

iL1,2 dt

iL1 = IL1 = 1
TS

1

(27)

(d + d2 )TS IL1,Peak

(28)

(29)

Referring to Fig. 7, the inductor current is equal to its peak value

(IL1,Peak ) at time t = dTS . Therefore:
iL1 (t = dTS ) = IL1,Peak =

Vg
dTS
L1

(30)

Substituting Eqs. (26) and (30) in Eq. (28), the average value of
inductor current is calculated as:

MDCM + 1
MDCM (2n + 1)

(31)

where MDCM = Vo /Vg is the voltage gain of the proposed converter

in DCM. Using power balance between input and output, MDCM can
be calculated. Thus in the rst step, it is necessary to calculate the
average value of the power supply current (Ig ):
Ig = IQ =

1
TS

TS

ig dt =
0

1
TS

(32)

ig,1 dt
0

(2n + 1) +

4(n + 1)d2
(2n + 1) +
K

(35)

2L1
RL TS

(36)

2.3. BCM operation

In this mode of operation, the switch Q is turned on at the instant
of zero transition of inductor current. BCM is the boundary between
CCM and DCM. Inductor L1 current is shown in Fig. 8.
As can be seen from Fig. 8, the DCM operation (Fig. 7) is achieved
when iL1 is larger than average value of inductor current. It
means:
IL1 = iL1 < iL1

(37)

Using Eq. (30), iL1 can be expressed as follows:

iL1 =

IL1,Peak
Vg dTS
=
2
2L1

(38)

Writing the charge balance of capacitor Co1 and after some simplication, IL1 can be determined as:
IL1 =

2
2
Io =  Io
1d
d

(39)

Substituting Eqs. (38) and (39) into Eq. (37) and considering Eq.
(36), upper limit for parameter K will be obtained as follows:
K<

dTS

where parameter K is dened as below:

Vg
t
L1

d2 Ts Vg
=
2L1

1
=
2

MDCM

Being obtained the peak value of inductors currents, the average

value can be calculated. For this purpose at rst the inductor current
equation in the rst time interval is written:

iL1 = IL1

K=

Thus:

iL1 (t) =

With the assumption of 100% efciency and using power balance

law, MDCM is obtained as below:

dTS

1
(Surface of triangle)gure,7
TS

(34)

dd

(40)

2 VVgo

Substituting Eq. (24) in Eq. (40):

2

iL1

K < Kcrit =

nVC1 VCo1
(n 1) L1

Vg
L1

(d

d 2 )TS

Fig. 7. Current of inductor L1 (iL1 ) in DCM.

(41)

which Kcrit is the critical value of parameter K at the boundary of

CCM and DCM. Superseding Eq. (24) in Eq. (41), we have:

t
dTS

dd
2(2n + 1 + d)

Kcrit =

[MCCM (2n + 1)] (1 + n)

MCCM (MCCM + 1)2

(42)

The curve of Kcrit versus d and n is drawn in Fig. 9(a). As can

be seen at xed duty cycles increasing of n, leads to decrease of

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T. Nouri et al. / Electric Power Systems Research 105 (2013) 7184

Fig. 9. Kcrit curves (a) Kcrit versus d and n, (b) Kcrit for {n = 2}.

Kcrit . For specic value of {n = 2} the curve is shown in Fig. 9(b). For
K < Kcrit , converter operates in DCM, otherwise in CCM.
According to aforementioned descriptions DCM is reachable
by one of the following selections: load current, inductances of
inductors and switching frequency. The maximum value of Kcrit is
occurred at the following duty cycle:
dm =

(3 + 6n) +

(3 + 6n)2 + 8(2n + 1)
4

(43)

Substituting Eq. (48) in (47) yields:

VC =

IL (1 d)TS
C1

(49)

Replacing Eq. (39) in Eq. (49) the variations of capacitor voltages

as derived as follows:
VC =

2Io
C1 fS

(50)

Maximum variation of capacitors voltages (VC,Max ) in a switching period is equal to:

3. Design of inductors and capacitors

VC VC,max

3.1. Design of the inductors

Considering Eqs. (51) and (52) and writing load currents versus
output voltage and load resistance, minimum values of capacitors
are obtained:

The values of inductors should be designed in such a way that

their current ripple (iL ) dont exceed from allowed values. In the
rst time interval following expression can be written:
L1

iL1
= Vg
dTS

(44)

If iL1 < iL1,max , then we have:

Lmin =

dVg
fs iL1,max

(45)

2V

o


VC,max RL fS

(52)

Design of lter capacitor of the load: According to Fig. 3(a), the

current of capacitor Co (iCo ) during the second time interval is equal
to:
ICo = Io , 0 t dTS

(53)

Substituting Eq. (54) in Eq. (47) yields:

Also minimum values of inductors for operation in CCM can be

calculated. According to aforementioned discussions, in order to
operate in CCM, K should be greater than Kcrit . Thus considering
Io = Vo /RL , lower limit for inductors will be calculated as:
Vo dd
=
4fs Io (2n + 1 + d)

VC =

Io dTS
Co

(54)

Thus:
Co =

Lmin,BC

C1

(51)

(46)

dIo
VCo fS

(55)

Assuming the maximum allowed variation of the load voltage is

Vo,Max :

3.2. Design of the capacitors

VCo Vo,Max

Voltage ripple of the capacitors (VC ) versus the available

charge (Q), is expressed as follows:

Therefore, minimum value of the capacitor Co is obtained as

below:

VC =

IC t
Q
=
C
C

(47)

Design of the capacitors in the stages: If the capacitor currents

in each time interval are approximated by their average values, thus
according to Fig. 4 in the second time interval we have:
IC1,2 = IL , dTS t TS

(48)

Co

dIo
Vo,Max fS

(56)

(57)

4. Input lter design and interleaving effect

The main drawback of the under studied converter is that the
switch Q is in series with the input power source. Thus the converter
draws high pulsating current from input power source that may

T. Nouri et al. / Electric Power Systems Research 105 (2013) 7184

77
Bode Diagram

20

I IPS

RLF

Magnitude (dB)

10

I CS

LF

-10
LF=3e-6 (H); RLF=5e-3 (Ohm)
CF=400e-6 (F); RCF=20e-3 (Ohm)
-20

RCF

I Q ,ON
dTS

CF

TS

fS

-30

20 KH

-40
-1
10

Converter side current

10

(a)

10
Frequency (kHz)

10

(b)
Fig. 10. Input lter, (a) lter circuit, (b) bode plot.

shorten battery and fuel cell life span. As a result, an input lter
is needed to suppress high frequency components. The input lter
circuit is shown in Fig. 10(a). The transfer function of the lter in
Laplace domain is obtained as below:
H(S) =

RCF CF S + 1
LF CF S 2 + (RCF + RLF )CF S + 1

Besides output power is shared between the phases and the total
power losses is reduced that leads to higher efciencies.
5. Real gain of the proposed converter using actual models
of the components

(58)

In which RCF and RLF are the ESR values of the lter. Bode plot of
the lter is shown in Fig. 10(b). It is clear that the high frequency
components are suppressed effectively by the low pass lter.
According to Fig. 10(a) the switching frequency component of
the converter side current is attenuated by 22 dB. By using of Fourier
analysis the fundamental component of the converter side current
(ICS1 ) can be written as below:

If the on state resistance of the switch Q (r(DSon) ) and forward

voltage drop of diodes (rD , VFD ), and ESR values of all inductors (rL )
and capacitors (rC ) are considered in the equivalent circuits of Fig. 3,
then the theoretical voltage gain is expressed as below:
M=

 2n + d + 1 

where:

IQ,ON
IQ,ON
=(
sin 2d) cos(t) + {
[1 cos(2d)]} sin(t) (59)



A1 =

In which IQ,ON is the average value of the switch Q current during

rst time interval and can be written as follows:

A2 =

ICS1

IQ,ON =

MCCM
Io
d

(60)

The ltered current amplitude at input power source (IIPS ) is

calculated as below:

IIPS = 10(Mag |dB )/20 ICS1

(61)

The input lter size can be further reduced by interleaving

technique named as input parallel output parallel (IPOP) that is
shown in Fig. 11. By interleaving of m modules of the proposed
converter the input current ripple is effectively reduced. In such
conditions input current switching frequency is m times of each
module switching frequency. Fig. 10(b) shows that for the same lter parameters, higher order frequencies are attenuated severely.

Module 1
Module 2

1d

4n + d + 3
2n + d + 1

1 A1
1 + A2 + A3

VFD
Vg

(62)

2n + 2

{4rD + 2d[RL + rDSon (n + 1)] + (1 d)(2n 1)rDSon }

2
d(1 d) RL
2[rC (4 d) 2drL + rD ]
A3 =
d(1 d)RL
Also the voltage across capacitor Co1 is obtained as below:

VCo1 =

Vo Vg + VFd
(2rC + rd )Vo
+
2
RL d(1 d)

(63)

Equation (62) is drawn for three cases of DCL unit number

and the plots are shown in Fig. 12. The parameters of three cases
are assumed as follows:
case (1) n = 1, Vg = 10, rDson = rd = 0.01, VFD = 0.075 V, rL = 15 m,
rC = 50 m {converter in [26]}
case (2) n = 2, Vg = 10, rDson = rd = 0.01, VFD = 0.075 V, rL = 15 m,
rC = 50 m
case (3) n = 3, Vg = 10, rDson = rd = 0.01, VFD = 0.075 V, rL = 15 m,
rC = 50 m
As can be seen from Fig. 12, the voltage gain increases considerably by increasing of n. Also at high duty cycles (typically higher
than d = 0.92) the voltage gain decreases sharply due t parasitic
components.
6. Extension of the converter

Module m
Fig. 11. IPOP technique.

The voltage step-up ratio can be increased by applying another

voltage multiplier cell. The proposed converter with two-voltage
multiplier cell is shown in Fig. 13. The voltage step-up ratio (M)

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T. Nouri et al. / Electric Power Systems Research 105 (2013) 7184

70
60
50
Case 1: Blue curve
Case 2: Red curve
Case 3: Black curve

40
30
20
10
0

0.2

0.4

0.6

0.8

D
Fig. 12. Calculated real voltage gain versus duty cycle.

Co3
Co1

Ln 1

Cn

Dn1

Ig

Vg

C2

D21

Fig. 15. Power circuits of the proposed converter with: (a) {n = 2} (b) {n = 3}.

VC3
L3 VL2

Vo

Co4

RL

7. Analyzing of the mismatch in the inductances of the

proposed converter

Do1 Do2

VC 2
L2 VL2

D11

VCo1

VCn

n stages
C3

D31

VL n 1

Io

L
Dx1 Dx 2

C1
VC1
L1 VL1

D12

D22

D32

Dn2

VCo2

Co2
Fig. 13. Extension of the proposed converter.

and the per unit value of the voltage stress across switch Q (VQ,pu )
are obtained as below:
M=

Vo
(2n + 1) + (2 + n)D
=
Vg
1D

VQ,pu =

(64)

The used inductors in the proposed converter may have some

mismatch to each other. When the switch Q is in on state, the inductors are charged. The current ripple of the largest inductor is the
least of all. When the switch is turned off, all inductors are discharged in series and their currents are equal to the largest inductor
current. It means that the largest inductor current remains constant
at the instant of switch Q turn off and the other inductors currents
decrease sharply to the largest inductor current. It is assumed that
inductance L1 is the largest of all. The current of an arbitrary inductance Lj (j = 2, . . ., n + 1) is drawn respective to inductance L1 current
that is shown in Fig. 14. The current ripple difference is obtained as
below:

j =

M+1
M(d + 2)

(65)

L1 Lj

L1 Lj

Vg dTS

(66)

The average value of inductor Lj is given by

By comparing Eqs. (25) and (65) it can be concluded that the

voltage stress across switch Q is decreased in the converter shown
in Fig. 13.

i Lj

ILj = IL1 +

dTS j
Surface of hatched area
= IL1 +
TS
2TS

100

I Lj

VQ [V]

i L1

I L1

dTS (1-d)TS
Fig. 14. Effect of individual inductance mismatch on current waveforms.

0.0
0.000

0.100

0.200

0.300

0.400

Fig. 16. Simulation results of transient voltage across switch Q.

(67)

T. Nouri et al. / Electric Power Systems Research 105 (2013) 7184

Replacing Eqs. (39) and (66) in Eq. (67) yields:

ILj =

d2 Vg
2Io
+
1d
2fS

L1 Lj

14.0

IQ (CSC)

(68)

L1 Lj

8. Simulation and experimental verication

0.0

Simulations are carried out and laboratory prototypes are built

to verify the satisfying operation of the proposed converter. Power
circuits of the proposed converters are shown in Fig. 15. The transistors and diodes of the prototypes are BUP314 and MUR860G,

8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0

IPSC

79

CSC1

CSC2

0.60000

0.60020

Fig. 17. Simulation results of CSC and IPSC for the converter of Fig. 15(a).

7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
0.60020

(a)

0.60000

IPSC

0.60000

0.60020

(b)

Fig. 18. Simulation results of the IPOP structure, (a) modules currents, (b) total modules currents and ltered IPSC.

Fig. 19. Experimental results of the IPOP structure (a) rst module switch current (CSC1) (2 A/Div), (b) second module switch current (CSC2) (2 A/Div), (c) ltered IPSC
(2 A/Div), (d) ripple content of IPSC (0.1 A/Div).

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T. Nouri et al. / Electric Power Systems Research 105 (2013) 7184

Fig. 20. Experimental results of the proposed converter (Fig. 15(a)) with d = 0.6 in CCM, (a) output voltage and the voltage across switch Q, (b) input current, (c) inductor
current and its ripple content, (d) capacitor C1 current (1A/Div), (e) capacitor Co1 current (0.5 A/Div).

respectively. Power supply, switching condition and load are specied as below:
Vg = 10 V, d = 0.6 , RL = 288 , fS = 20 KHz
Capacitors and inductors are designed based on {n = 2}. According to Eq. (62) the voltage gain of the proposed converter {n = 2} is
12. Thus the output voltage will be 120 V. The load current in proposed converter is 0.4166 A. According to Eq. (39), the average value
of the inductor current is obtained 2.08 A. Considering 5.5% ripple
in inductor currents, minimum value of the inductors will be 2.6
(mH) according to (45). Assuming 0.1 (V) ripple in the voltages of
stages capacitors, minimum values of these capacitors will be 400

(f) by using of (52). Also with the same allowable voltage ripple for
output voltage, according to Eq. (57), the output ltering capacitor
will be 280 (f). The component parameters of the proposed converter prototype are summarized in Table 2. It should be noticed
that, the used elements in the IPOP structure (except the input lter
parameters) are the same as that of one module. Fig. 16 shows the
transient voltage across switch Q. As can be seen the voltage spike
at transient state is not very large. Fig. 17 shows the simulation
results of the converter side current (CSC) and the ltered input
power source current (IPSC) for the converter of Fig. 15(a). The
ripple magnitude of the ltered current is approximately 0.6 (A).
Simulation and experimental results of the IPOP structure with two
modules of the converter of Fig. 15(a) are shown in Figs. 18 and 19,

T. Nouri et al. / Electric Power Systems Research 105 (2013) 7184

Table 2
Component parameters of the proposed converter prototype.
Component

Specication

Load power (Po )

Input voltage (Vg )
Switching frequency (fS )
Inductors (L1 = L2 = L3 )
Capacitors (C1 = C2 = Co1 = Co2 )
Output capacitors (Co )
Input lter inductor (LF ) and capacitor (CF )
Input lter inductor (LF ) and capacitor (CF )
(IPOP structure)

50 (W)
10 (V)
20 KHz
2.6 mH
460 F
280 F
3 H, 220 F
1 H, 20 F

respectively. The CSC ripple is lower comparing to use one converter module. Therefore a smaller lter (LF = 1 H, CF = 20 F) is
used to cancel out high frequency ripples. The ripple magnitude of
the ltered current is approximately 0.25 (A). As can be seen the
simulation and experimental results match each other fairly.
Fig. 20 shows the experimental results of the proposed converter
(Fig. 15(a)) in CCM with {n = 2}. According to Eq. (24), the ideal voltage gain without the parasitic components consideration is 140 (V).
However, the parasitic components have signicant effects on the
voltage gain according to Eq. (62) that yields 120 (V) output voltage and it is consistent with the experimental results of Fig. 20(a).
The voltage across the switch is nearly 66 (V), according to Eq. (25)
(Fig. 20(a)). It should be noticed from Fig. 20(e) and Fig. 20(d) that

81

the capacitors C1 and C2 inrush currents arent too high to increase

the switching loss considerably. Figs. 21 and 22 show the inductor L1 current and its average value, in BCM (L1 = 66 H) and DCM
(L1 = 40 H), respectively. As can be seen from Fig. 21(a), iL1 reaches
to zero at the instant of the switch turn on that demonstrates the
BCM. Experimental result of output voltage for BCM is shown in
Fig. 21(b). The voltage gain of the proposed converter under BCM is
equal to 13.6 according to Eq. (35). Then the output voltage will be
136 (V). The output voltage in the experimental results is around
110 (V). In DCM, the current reaches zero at the second time interval
and remains zero for a while, which is shown in Fig. 22(a). Experimental result of output voltage for DCM is shown in Fig. 22(b).
The voltage gain of the proposed converter under DCM is equal to
16.6 according to Eq. (35). Then the output voltage will be 166 (V).
The output voltage in the experimental results is around 143 (V). It
should be noted that the difference between mathematical voltage
gain and experimental results is due to parasitic components such
as ESR of inductors and capacitors, on state resistance of switch Q
and diodes, and forward voltage drop across diodes, that were not
take into account for voltage gain calculation in DCM operation.
Fig. 23 shows the experimental results of the proposed converter
(Fig. 15(b)) for different duty cycles values (d = 0.4, 0.5, 0.6). The
output voltage and the voltage across the switch Q are given for
each case. The results have satisfying conformity to their respected
analyzed values. The simulation and experimental results of 23%
mismatch between L1 and L2 are shown in Fig. 24 (L1 = 2.6 mH and

Fig. 21. Experimental results of the proposed converter (Fig. 15(a)) with d = 0.6 in BCM, (a) inductor current and its average value, (b) output voltage.

Fig. 22. Experimental results of the proposed converter (Fig. 15(a)) with d = 0.6 in DCM, (a) inductor current and its average value, (b) output voltage.

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T. Nouri et al. / Electric Power Systems Research 105 (2013) 7184

Fig. 23. Experimental results of the output voltage and the voltage across switch Q for the proposed converter (Fig. 15(b)) with (a) d = 0.4, (b) d = 0.5, (c) d = 0.6.

L2 = 2 mH). The simulation results in Fig. 24(a) show both DC and

ripple content of the inductors currents. The experimental result
in Fig. 24(b) deals with the ripple content of the inductor currents.
As can be seen the results match the carried analysis in section 7
reasonably well.
The measured efciencies of the proposed converter (Fig. 15(a))
with both one and two modules implementation are shown in
Fig. 25. The output voltage is xed at 120 V.As can be seen from
Fig. 25(a) for low input powers the converter efciency is held in
satisfactory range. As the power level increases, the efciency is
decreased. It is mainly due to series connection of the switch Q

with the input power source that is a drawback of the proposed

converter. Increasing of load power causes higher amount of
current drawn from the input power source. Therefore, both on
state and switching losses of the switch Q are increased that reduce
the converter efciency. Another contributor to low efciency
is the long conduction path. In the rst switching interval, the
current path consists of the rDSon of the switch Q and the on state
resistance of diodes. By IPOP structure the efciency is improved
that enables the converter application in higher power levels.
By increasing of the input voltage from Vg = 10 V to Vg = 15 V the
efciency is increased that is shown in Fig. 25(b) for both one and

Fig. 24. Simulation and Experimental results of the proposed converter considering 23% mismatch in inductances L1 and L2 , (a) Simulation results with both DC and ripple
contents, (b) Experimental results with only ripple contents (20 mA/Div).

T. Nouri et al. / Electric Power Systems Research 105 (2013) 7184

83

Fig. 25. Measured efciency of the proposed converter (Fig. 15(a)) with, (a) Vg = 10 (V), (b) Vg = 15 (V).

Fig. 26. Measured efciency of the proposed converter (Fig. 15(b)), (a) Vo = 120 (V), (b) Vg = 15 (V).

two modules implementation of the converter. With increasing

of input voltage, lower current is demanded for the same output
power which reduces both on state and switching losses of switch
Q and diodes. Therefore the efciency is increased. The measured
efciencies of the proposed converter (Fig. 15(b)) are shown in
Fig. 26. Fig. 26(a) shows the measured efciency with constant
output voltage. The efciency improvement due to increasing of
input voltage can be seen from the measurements. By comparing
of Fig. 26(a) and Fig. 25, it is clear that the efciency is decreased
with increasing of n for the same output voltage. Fig. 26(b) shows
the measured efciency with Vg = 15 V and d = 0.4. By increasing of
d, the output voltage level is increased that causes the efciency
improvement for the same output power.

9. Conclusion
This paper proposed a generalized structure for DCDC converters which used n stages of DCL units at the input stage. With
increasing of the n, it was possible to achieve higher voltage gains.
In the other words, it was possible to obtain the proposed voltage gain with lower values of duty cycles compared to the custom
DCDC converters in literatures. Three regions of operation named
as CCM, BCM and DCM have been investigated in detail for the
proposed converter. The main disadvantage of the proposed converter is that with higher stages number, the switch Q current stress
would be increased that deteriorate the converter efciency at high
power levels. However, it was shown that using IPOP technique
the converter could be applied for higher power application due
to efciency improvement. Another disadvantage of the proposed
converter is that for higher voltage gain, more passive components
should be used. However, the circuit structure is simple and generalization of the converter will be achieved easily. Finally simulation
and experimental results conrmed the correctness of carried analysis.

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