Objective : To design a three beta-multiplier based current reference, using only

CMOS transistors in TSMC 0.25u CMOS design library.

DESIGN 1

SCHEMATIC :

Parameters and Design requirements:

Technology - CMOS TSMC 0.3m process
Power supply Vdd =2.5V
Reference Current Iref= 10uA
NMOS: tsmc25N
kn'=2.7475x10-4 Vth=0.49V
PMOS :tsmc25P
kp'=0.9575x10-4 Vth=0.54V
CALCULATIONS :
The widths of the transistors can be calculated by using the current equation.
The current flowing through M1 transistor can be given by :
M1 :
Veff=VGS-VTHN ; Veff = 6% Of Vdd = (6/100)(2.5) = 0.15 V
Iref = (1/2) kn'(W/L)(Veff2)
10x10-6
= (1/2)(W/L)(2.7475x10-4)(0.15)2 ; L = 0.6um
W=1.95um
M3B :
Iref = (1/2) kp'(W/L)(Veff2)
10x10-6= (1/2)(W/L)(0.9575x10-4)(0.15)2 ; L=0um
W= 8.4um
The transistors M3T, M4T and M4B will have the same sizes as M3B.
M2 :
The size of M2 is k times size of M1.
For k=4
W=7.8um ; L =um
For Startup Circuit :
The PMOS should have small drive. Hence the width is considered to be less
than length .Hence the PMOS Width=975nm
; L=5um
The bottom NMOS should have large drive, hence it has the same width as
bottom transistor W=1.95x10-6
L=0.6x10-6
The top NMOS size is also considered to be the same as M1 i.e
W=1.95um
L=0.6x10-6um
DESIGN QUESTION 1 :
TO FIND THE VALUE OF RESISTANCE R :

(Theoritical)
Vgs1=Vgs2+Iref*R ;
------- I
'
I=(1/2) kn (W/L)(Vgs-Vth)2 ;
Vgs=(2ID/) + VTH ;
2=K* 1 (Since W2= K*W1)

{= kn '(W/L)}

Substituting Vgs1 and Vgs2 in I we get

(1/R)= (2 kn '(W/L)*Iref) ;
Substituting the values of Iref W and L in the above equation we get
R= 7.484K.
(Practical )
By sweeping the resistance from 5K to 10K with respect to current at the
drain of M2, the value of resistance R at 10uA is 8.316K
Plot showing the resistance R at 10uA :

The Resistance R at 10uA is 8.315K

SCHEMATIC Showing Vgs, Vds, I in Beta Multiplier :

Table Showing Sizes, Voltages and Currents of Every Transistor in the Design :
Device

W(um)

L(nm)

VGS-Vt(mV)

8.316 K

M1

1.95

600

158.5m

623.6m

10.

M2

7.8

600

92.6

689m

10

M3B

8.4

900

-178.7m

-1.104

-10.

M3T

8.4

900

-164.1m

-771.4m

-10.

M4B

8.4

900

-178.7m

-1.104

-10

M4T

8.4

900

-164.1m

-771.4m

-10

Startup

450

45u

-1.587

-2.476

-711.9n

450

450

45.87m

1.105

1f

VDS(V)

Ibias(uA)

Pmos
Startup

Nmos(Top)
Startup

450

450

114.2m

23.77m

711.9n

Bias PmosB

8.4

900

-178.7m

-1.104

-10

Bias PmosT

8.4

900

-164.1m

-771.4m

-10.

Nmos diode

7.8

600

158.5

623.6m

10

Nmos(Bottom)

Connected

DESIGN QUESTION 2:
Plots Iref1 and Iref2 with respect to Vdd along with Mismatch.
Sweeping Vdd from 2V to 3V.

The mismatch is in nanoamperes.

Percentage of Mismatch is given by :
I
I
matching(%) ref 1 ref 2 100
Iref 2

which is less than 5%.

DESIGN QUESTION 3
Bias for Nmos diode connected transitor whose size is same the size of
M2.
Plot for gm of this transistor for -20C to 80C is as shown below :

Vbais VS Temp:

Vbais VS Vdd:

DESIGN 2 :

SCHEMATIC :

Parameters and Design requirements:

Technology - CMOS TSMC 0.3m process
Power supply Vdd =2.5V
Reference Current Iref= 10uA
NMOS: tsmc25N
kn'=2.7475x10-4 Vth=0.49V
PMOS :tsmc25P
kp'=0.9575x10-4 Vth=0.54V
The calculations of the widths are similar to design 1. In this cascode design
there are two more transistors M1T and M2T whose widths are similar to
M1B and M2B.

Plot showing the resistance R at 10uA :

The Resistance R at 10uA is 8.226K

SCHEMATIC Showing Vgs, Vds, I in Cascode Design :

Table Showing Sizes, Voltages and Currents of Every Transistor in the Design :
Device

W(um)

8.140K

M1B

1.95

L(nm)
600

VGS-Vt(mV)
158.5m

VDS(V)

Ibias(uA)

623.6m

10

M1T

1.95

600

164.5m

740.3m

10

M2B

7.8

600

92.95m

544.6m

10

M2T

7.8

600

124.8m

146.2m

10

M3B

8.4

900

-181.7m

-367.5m

-10

M3T

8.4

900

-164.2m

-768.7m

-10

M4B

8.4

900

-181.8m

-956.4m

-10

M4T

8.4

600

-164.1m

-771.4m

-10

Startup

450nm

45u

-1.587

-2.476

-711.9n

1.95

600

45.87m

1.105

10f

1.95

600

114.2m

23.77m

711.9n

Bias PmosB

8.4

600

-179.3m

-978m

-10

Bias PmosT

8.4

600

-164.2m

-771.5m

-10

Nmos diode

1.95

600

158.5m

623.6m

10

1.95

600

126.6m

127m

10

Pmos
Startup
Nmos(Top)
Startup
Nmos(Bottom)

Connected
Bias Nmos T

DESIGN QUESTION 2:
Plots Iref1 and Iref2 with respect to Vdd along with Mismatch.
Sweeping Vdd from 2V to 3V.

The mismatch is in nanoamperes.

DESIGN QUESTION 3
Bias for Nmos diode connected transitor whose size is same the size of
M2.
Plot for gm of this transistor for -20C to 80C is as shown below :
Vref VS Temp

DESIGN 3 :

Parameters and Design requirements:

Technology - CMOS TSMC 0.3m process
Power supply Vdd =2.5V
Reference Current Iref= 10uA
NMOS: tsmc25N
kn'=2.7475x10-4 Vth=0.49V
PMOS :tsmc25P
kp'=0.9575x10-4 Vth=0.54V
SCHEMATIC :

CALCULATIONS :
The widths of the transistors can be calculated by using the current equation.
The current flowing through M1 transistor can be given by :
MA1 & MA2 :
Veff=VGS-VTHN ; Veff = 6% Of Vdd = (6/100)(2.5) = 0.15 V
Iref = (1/2) kn'(W/L)(Veff2)
10x10-6
= (1/2)(W/L)(2.7475x10-4)(0.15)2 ; L = 0.6um
W=1.95um
MA3 & MA4 :
Iref = (1/2) kp'(W/L)(Veff2)
10x10-6= (1/2)(W/L)(0.9575x10-4)(0.15)2 ; L=0um
W= 8.4um
The transistors M3, M4 and will have the same sizes as MA3.
M2 :
The size of M2 is k times size of M1.
For k=4
W=7.8um ; L =um
For Startup Circuit :
The PMOS should have small drive. Hence the width is considered to be less
than length .Hence the PMOS Width=975nm
; L=5um
The bottom NMOS should have large drive, hence it has the same width as
bottom transistor W=1.95x10-6
L=0.6x10-6
The top NMOS size is also considered to be the same as M1 i.e

W=1.95um

L=0.6x10-6um

Plot showing the resistance R at 10uA :

The Resistance R at 10uA is 8.186K

SCHEMATIC Showing Vgs, Vds, I :

Device

W(um)

L(nm)

VGS-Vt(mV)

8.185K

MA1

1.95

600

167.5

1.728

11.93

MA2

1.95

600

167.3

1.755

11.9

MA3

8.4

600

-174

-771.7m

-11.93

MA4

8.4

600

-174

-744.5m

-11.9

M1

1.95

600

158.5

623.6m

10

M2

7.8

600

92.96

542.3m

10

M3

8.4

600

-155.1

-1.876

-10

M4

8.4

600

-155.1

-1.876

-10

Startup

975nm

5.025u

-1.422

-2.313

10.79

VDS(V)

Ibias(uA)

Pmos
Startup

1.95

600

45.18

187.1m

10.29f

1.95

600

121.2m

1.132

10.79

Bias Pmos

8.4

600

-155.1

-1.876

-10

Nmos diode

1.95

600

158.5

623.6m

10

Nmos(Top)
Startup
Nmos(Bottom)

Connected

DESIGN QUESTION 2:
Plots Iref1 and Iref2 with respect to Vdd along with Mismatch.
Sweeping Vdd from 2V to 3V.

The mismatch is almost zero .

DESIGN QUESTION 3 :