Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
Solutions
1. (3 points) Do sample problem 1.c from the State Machine timing handout.
SM Clock
(Clock)
TpFFmax (35)
TpComb max (44)
Tsetup min (10)
Tclk/2 + 6 = 89 ns
Tclk = 83 ns
2. (3 points) Do sample problem 1.d from the State Machine timing handout.
SM Clock
Delayed Clock
TpFFmax (35)
TpComb max (44)
2 (TpInv max) (26)
3. (3 points) Do sample problem 3.c from the State Machine timing handout.
Input Clock
SM Clock
250 ns
TpOut min = 250 + 67 - 6 = 311 nsec
i.
Rising edge on
Output reg.
311/6 = 52 inverters
ii. 61 ns required from clock on input reg. to output reg. clock: 61/6 = 11 inverters
(R)
(S)
(T)
CK
CK
CK
Q
(U)
Q
CK
CLOCK
5. Assuming the same timing parameters as in the previous problem, consider the circuit
below. You should find that it may not work properly at any frequency. Explain why.
Answer: Depending on the exact propagation delay of flip-flops U and R, either the
setup or the hold time for flip-flop S may not be met. For example, flip-flop R has an
exact propagation delay of 8 nsec and flip-flop U has an exact propagation delay of 10
nsec, a setup time violation will occur at flip-flop S. If the two delays are reversed, a
hold time violation will occur at flip-flop S.
(R)
(S)
(T)
CK
CK
CK
Q
(U)
CLOCK
CK
00
01
11
10
f
W
V,W
X
X
d