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Feeder Relay
Instruction Manual
Preface
Preface
Introduction
This guide and the relevant operating or service manual documentation for the equipment provide
full information on safe handling, commissioning and testing of this equipment.
Documentation for equipment ordered from NR Electric Co., Ltd. is dispatched separately from
manufactured goods and may not be received at the same time. Therefore this guide is provided
to ensure that printed information normally present on equipment is fully understood by the
recipient.
Before carrying out any work on the equipment, the user should be familiar with the contents of
this manual and read relevant chapters carefully.
This chapter describes the safety precautions recommended when using the equipment. Before
installing and using the equipment, this chapter must be thoroughly read and understood.
Are familiar with the installation, commissioning, and operation of the equipment and of the
system to which it is being connected;
Are able to safely perform switching operations in accordance with accepted safety
engineering practices and are authorized to energize and de-energize equipment and to
isolate, ground, and label it;
Are trained in the care and use of safety apparatus in accordance with safety engineering
practices;
Preface
means that death, severe personal injury, or considerable equipment damage will
occur if safety precautions are disregarded.
WARNING
means that death, severe personal injury, or considerable equipment damage could
occur if safety precautions are disregarded.
CAUTION
means that light personal injury or equipment damage may occur if safety
precautions are disregarded. This particularly applies to damage to the device and to
resulting damage of the protected equipment.
WARNING!
The firmware may be upgraded to add new features or enhance/modify existing features, please
make sure that the version of this manual is compatible with the product in your hand.
WARNING!
During operation of electrical equipment, certain parts of these devices are under high voltage.
Severe personal injury or significant equipment damage could result from improper behavior.
Only qualified personnel should work on this equipment or in the vicinity of this equipment. These
personnel must be familiar with all warnings and service procedures described in this manual, as
well as safety regulations.
In particular, the general facility and safety regulations for work with high-voltage equipment must
be observed. Noncompliance may result in death, injury, or significant equipment damage.
DANGER!
Never allow the current transformer (CT) secondary circuit connected to this equipment to be
opened while the primary system is live. Opening the CT circuit will produce a dangerously high
voltage.
WARNING!
z
Exposed terminals
Do not touch the exposed terminals of this equipment while the power is on, as the high
voltage generated is dangerous.
Residual voltage
Hazardous voltage can be present in the DC circuit just after switching off the power supply. It
takes a few seconds for the voltage to discharge.
II
Preface
CAUTION!
z
Earthing
The earthing terminal of the equipment must be securely earthed.
Operating environment
The equipment must only be used within the range of ambient environment detailed in the
specification and in an environment free of abnormal vibration.
Ratings
Before applying AC voltage and current or the power supply to the equipment, check that they
conform to the equipment ratings.
External circuit
When connecting the output contacts of the equipment to an external circuit, carefully check
the supply voltage used in order to prevent the connected circuit from overheating.
Connection cable
Carefully handle the connection cable without applying excessive force.
AND gate: all the input signals are 1, then the output is 1
III
Preface
Copyright
Version: 2.00
P/N: EN_DYBH5321.0086.0001
Tel: +86-25-87178185,
Fax: +86-25-87178208
Email: nr_techsupport@nari-relays.com
We reserve all rights to this document and to the information contained herein. Improper use in particular reproduction and dissemination
to third parties is strictly forbidden except where expressly authorized.
The information in this manual is carefully checked periodically, and necessary corrections will be included in future editions. If
nevertheless any errors are detected, suggestions for correction or improvement are greatly appreciated.
We reserve the rights to make technical improvements without notice.
IV
Preface
Documentation Structure
The manual provides a functional and technical description of this relay and a comprehensive set
of instructions for the relays use and application.
The chapter contents are summarized as below:
1 Introduction
Briefly introduce the application, functions and features about this relay.
2 Technical Data
Introduce the technical data about this relay, such as electrical specifications, mechanical
specifications, ambient temperature and humidity range, communication port parameters, type
tests, setting ranges and accuracy limits and the certifications that our products have passed.
3 Operation Theory
Introduce a comprehensive and detailed functional description of all protective elements.
4 Supervision
Introduce the automatic self-supervision function of this relay.
5 Management Function
Introduce the management functions (such as metering, control and recording etc.) of this relay.
6 Hardware
Introduce the main function carried out by each module of this relay and providing the definition of
pins of each module.
7 Settings
List of all the settings and their ranges and step sizes, together with a brief explanation of each
setting and some notes about the setting application.
9 Configurable Function
Introduce the configurable function (such as protection function configuration, LED configuration,
binary input configuration and binary output configuration etc.) of this relay.
10 Communication
Introduce the communication port and protocol which this relay can support, the IEC60870-5-103,
IEC61850 and DNP3.0 protocols are introduced in details.
V
Preface
11 Installation
Introduce the recommendations on unpacking, handling, inspection and storage of this relay. A
guide to the mechanical and electrical installation of this relay is also provided, incorporating
earthing recommendations. A typical wiring connection to this relay is indicated.
12 Commissioning
Introduce how to commission this relay, comprising checks on the calibration and functionality of
this relay.
13 Maintenance
A general maintenance policy for this relay is outlined.
VI
1 Introduction
1 Introduction
Table of Contents
1.1 Application ........................................................................................................1-1
1.2 Functions ..........................................................................................................1-1
1.3 Features ............................................................................................................1-3
List of Figures
Figure 1.1-1 Functional diagram of PCS-9611 ........................................................................ 1-1
1-a
1 Introduction
1-b
1 Introduction
1.1 Application
The PCS-9611 relay is a protection, control and monitoring unit for various primary equipments
(such as overhead line, underground cable and transformer etc.) on solidly grounded, impedance
grounded, Peterson coil grounded and ungrounded system. This relay is suitable for wall surface
mounted indoors or outdoors or flush mounted into a control panel.
This relay can sample the analog values from the traditional instrument transformers, or receive
the sampled values from the electronic current and voltage transformers (via a merging unit). The
binary inputs and outputs of this relay can be configured according to the demands of a practical
engineering through the PCS-Explorer configuration tool auxiliary software, which can meet some
special requirements of protection and control functions.
This relay can fully support the IEC61850 communication protocol and GOOSE function, and can
completely meet the demands of a modern digitalized substation.
The function diagram of this relay is shown in Figure 1.1-1.
1.2 Functions
The functions of this relay include protective functions, management functions and auxiliary testing
functions, and the functions of this relay are listed in the following tables.
z
Protective functions
1-1
1 Introduction
Protective Functions
50P
51P
67P
50G
51G
67G
51SG
67SG
27
Undervoltage protection
59
Overvoltage protection
47
59G
49
46
46BC
81U
Under-frequency protection
81O
Over-frequency protection
81R
50BF
79
25
SOTF
MR
Mechanical protection
50DZ
37
Undercurrent protection
AI
Analog inputs
Voltage and current drift auto adjustment
Self supervision
VTS
CTS
Management functions
Management Functions
Metering
Circuit breaker status monitoring
2
TCS
1-2
1 Introduction
1024 supervision alarm records
1024 control operation records
1024 user operation records
FDR
SOE
1.3 Features
z
This device is based on a 32-bit high performance dual-core processor, internal high speed
bus and intelligent I/O ports, and the hardware is in module design and can be configured
flexibly, featuring interchangeability and easy extension and maintenance.
Modularized hardware design makes this relay be easily upgraded or repaired by a qualified
service person. Various function optional modules can satisfy various situations according to
the different requirements of the users.
The adoption of 16-bit A/D converter and the dual-channel sampling technology can ensure
the accuracy and reliability of protection sampling and the correctness of protection operation.
It is also provides dedicated current transformers for metering, and ensures the high accuracy
of telemetering with 48-point high speed sampling rate per cycle.
This device can sample the analog values from the traditional instrument transformers, or
receive the sampled values from the electronic transformers. It can support the protocol
IEC60044-8, IEC61850-9-2 and GOOSE.
Various algorithms for protection and measurement have been completed in this device for
the feature of electronic transformer sampling, such as the error prevention method of
multi-algorithms data anomaly for the digital channels, to realize high accuracy and reliability
under various conditions of network faults or communication interruption.
This device has powerful GOOSE functions, and the connection and cooperation between
some devices can be realized without using electrical cables, to facilitate the realization of
such functions as simple bus differential protection, overload interlock shedding function and
backup automatic transfer function etc.
1-3
1 Introduction
This device has fully realized the technology to integrate six functions into one device:
protection, measurement, control, remote signaling, merging unit function and remote module
functions, to improve the reliability.
Various methods of GPS time synchronization are supported in this relay, including SNTP,
IEEE1588 (V2), pulse per second (PPS) and IRIG-B synchronization.
The protection modules are completely separated from other modules, and are independent
in both hardware and software. The protection functions do not depend on the communication
network, so the failure of communication network will not affect the normal operation of the
protection functions.
Mature protection configuration, fast speed and high security performance can meet the
practical requirements. Each protective element is independent, so it is very convenient for
whether adopting the selected protective element.
This device constantly measures and calculates a large amount of analog quantities, such as
phase voltage, phase-to-phase voltage, neutral voltage, phase current, neutral current, active
power, reactive power, power factor and frequency etc.
The human machine interface (HMI) with a small control module (a 240128-dot LCD, a 9-key
keypad and 20 LED indicators) on the front panel is very friendly and convenient to the user.
This device can communicate with a SAS or RTU via different communication intermediates:
Ethernet network, RS-485 serial ports. The communication protocol of this device is optional:
IEC61850, IEC60870-5-103 or DNP3.0.
This device can detect the tripping circuit of the circuit breaker and monitor the operation
(close or trip) time of a circuit breaker by checking the auxiliary contacts of the circuit breaker.
Complete event recording function is provided: 64 latest protection operation reports, 1024
latest supervision records, 1024 latest control operation records, 1024 latest user operation
records and 1024 latest records of time tagged sequence of event (SOE) can be recorded.
Powerful fault and disturbance recording function is supported: 64 latest fault or disturbance
waves, the duration of a wave recording is configurable.
1-4
2 Technical Data
2 Technical Data
Table of Contents
2.1 General Specification.......................................................................................2-1
2.1.1 Electrical Specifications ..................................................................................................... 2-1
2.1.2 Mechanical Specifications.................................................................................................. 2-2
2.1.3 Ambient Temperature and Humidity ................................................................................... 2-2
2.1.4 Communication Interfaces ................................................................................................. 2-3
2.1.5 Type Test ........................................................................................................................... 2-4
2 Technical Data
2-b
2 Technical Data
IEC60255-11: 2008
Rated voltage
Variation
80% ~ 120%
Burden
Traditional AC inputs
Digital AC inputs
ABC
50Hz, 60Hz
Nominal range
fn 5Hz
Application object
For protection
1A
For metering
5A
1A
5A
30In
30In
2In
2In
continuously
3In
3In
2In
2In
for 10s
30In
30In
12In
12In
for 1s
100In
100In
30In
30In
250In
250In
75In
75In
< 0.15VA/phase
< 0.25VA/phase
< 0.20VA/phase
< 0.40VA/phase
Burden (@ In)
ABC
50Hz, 60Hz
Nominal range
fn 5Hz
Linear to
130V
Thermal
continuously
130V
withstand
10s
200V
capability
1s
250V
Burden
Up to 38
Rated voltage
24V
30V
48V
Rated current
1.20mA
1.50mA
Pickup voltage
Dropout voltage
2.40mA
110V
125V
220V
250V
1.10mA
1.25mA
2.20mA
2.50mA
2-1
2 Technical Data
Maximum permitted voltage
2000Vac, 2800Vdc
< 1ms
Tripping output
Signal output
Up to 20
Up to 10
Output model
Potential-free contact
Potential-free contact
380Vac, 250Vdc
380Vac, 250Vdc
Continuous carry
Pickup time
< 8ms
< 8ms
Dropout time
< 5ms
< 5ms
Bounce time
1ms
1ms
loaded contact
unloaded contact
Breaking capacity
Durability
Trepanning dimensions
Mounting way
Flush mounted
Display language
Housing material
Aluminum
Housing color
Silver grey
Location of terminals
Protection class
IEC60225-1: 2009
IEC60225-1: 2009
-40C ~ +70C
Permissible humidity
Altitude
< 3000m
2-2
2 Technical Data
Electrical
Ethernet
Optical
Parameters
Port number
2 or 4
Connector type
RJ-45
Transmission rate
100Mbits/s
Transmission standard
100Base-TX
Transmission distance
< 100m
Protocol
IEC60870-5-103:1997 or IEC61850
Safety level
Port number
Connector type
ST
Transmission rate
100Mbits/s
Transmission standard
100Base-FX
Multi-mode
Wavelength
1300nm
Transmission distance
< 1500m
Protocol
IEC60870-5-103:1997 or IEC61850
RS-485 (EIA)
Parameters
Port number
0 or 2
Baud rate
4800 ~ 115200bps
Transmission distance
Maximal capacity
32
Protocol
IEC60870-5-103:1997 or DNP3.0
Safety level
RS-232 (EIA)
Parameters
Port number
Baud rate
4800 ~ 115200bps
Printer type
EPSON LQ-300K
Safety level
RS-485 (EIA)
Parameters
Port number
Transmission distance
< 500m
Maximal capacity
32
Timing standard
PPS, IRIG-B
Safety level
2-3
2 Technical Data
Electrical Ethernet
(in front panel)
Parameters
Port number
Connector type
RJ-45
Transmission rate
100Mbits/s
Transmission standard
100Base-TX
Transmission distance
< 100m
Safety level
Optical Ethernet
Parameters
Optical fiber material
Glass fiber
Multi-mode
Connector type
LC
ST
Wavelength
1310nm
820nm
Transmission distance
< 2000m
-20dBm
Reception sensitivity
-30dBm
humidity test
Overvoltage category
Insulation measurement
Pollution degree
- Common mode
2.5kV
- Differential mode
1.0kV
8.0kV
15.0kV
2-4
2 Technical Data
Radio frequency interference tests
- Frequency sweep
- Radiated amplitude-modulated
10V/m(RMS), f=801000MHz
- Spot frequency
- Radiated amplitude-modulated
- Radiated pulse-modulated
Fast transient disturbance tests
10Vm(RMS), f=80/160/450/900MHz
10Vm(RMS), f=900MHz
IEC60255-22-4: 2008, Class IV
- Communication terminals
IEC60255-11: 2008
- Voltage dips
IEC60255-21-1:1988, Class I
Shock test
IEC60255-21-2:1988, Class I
Bump test
IEC60255-21-2:1988, Class I
Seismic test
IEC60255-21-3:1988, Class I
2-5
2 Technical Data
0.05In ~ 30.0In
Pickup current
1.00Setting
Dropout current
0.95Setting
Time setting
0.00s ~ 100.00s
Pickup time
35ms
Dropout time
35ms
1% Setting + 35ms
2.00V ~ 70.00V
2.00V ~ 120.00V
Operating time
35ms
Characteristic angle
Block logic
Operating time
35ms
0.05In ~ 4.0In
Pickup current
1.00Setting
Dropout current
0.95Setting
0.05 ~ 100.00
Pickup time
35ms
Dropout time
35ms
0.05In ~ 30.0In
Pickup current
1.00Setting
Dropout current
0.95Setting
2-6
2 Technical Data
Time setting
0.00s ~ 100.00s
Pickup time
35ms
Dropout time
35ms
1% Setting + 35ms
Characteristic angle
Block logic
Operating time
35ms
0.05In ~ 4.0In
Pickup current
1.00Setting
Dropout current
0.95Setting
0.05 ~ 100.00
Pickup time
35ms
Dropout time
35ms
5% of reference (calculated) value + 2.5% current
Pickup current
1.00Setting
Dropout current
0.95Setting
Time setting
0.00s ~ 100.00s
Pickup time
35ms
Dropout time
35ms
1% Setting + 35ms
Characteristic angle
Block logic
Operating time
35ms
2-7
2 Technical Data
Pickup current
1.00Setting
Dropout current
0.95Setting
0.05 ~ 100.00
Pickup time
35ms
Dropout time
35ms
5% of reference (calculated) value + 1.5% current
0.05In ~ 4.0In
Pickup current
1.00Setting
Dropout current
0.95Setting
Time setting
0.00s ~ 100.00s
Pickup time
50ms
Dropout time
50ms
1% Setting + 50ms
0.05In ~ 3.0In
Pickup current
1.00Setting
Dropout current
0.98Setting
0.01s ~ 6000.00s
Pickup time
35ms
Dropout time
35ms
2.00V ~ 120.00V
Pickup voltage
1.00Setting
Dropout voltage
Time setting
0.00s ~ 100.00s
Pickup time
80ms
Dropout time
80ms
1% Setting + 80ms
2-8
2 Technical Data
57.70V ~ 200.00V
Pickup voltage
1.00Setting
Dropout voltage
Time setting
0.00s ~ 100.00s
Pickup time
50ms
Dropout time
50ms
1% Setting + 50ms
2.00V ~ 160.00V
Pickup voltage
1.00Setting
Dropout voltage
0.95Setting
Time setting
0.00s ~ 100.00s
Pickup time
50ms
Dropout time
50ms
1% Setting + 50ms
2.00V ~ 120.00V
Pickup voltage
1.00Setting
Dropout voltage
0.95Setting
Time setting
0.00s ~ 100.00s
Pickup time
50ms
Dropout time
50ms
1% Setting + 50ms
45.00Hz ~ 60.00Hz
Over-frequency setting
50.00Hz ~ 65.00Hz
Pickup frequency
1.00Setting
Dropout frequency
1.00Setting
0.01Hz
Time setting
0.00s ~ 100.00s
Pickup time
50ms
Dropout time
50ms
1% Setting + 50ms
Blocking element
Undervoltage blocking setting
10.00V ~ 120.00V
2-9
2 Technical Data
Operating time
35ms
-10.00Hz/s ~ 10.00Hz/s
1.00Setting
1.00Setting
0.20Hz/s
Time setting
0.00s ~ 100.00s
Pickup time
50ms
Dropout time
50ms
1% Setting + 50ms
0.05In ~ 30.0In
Pickup current
1.00Setting
Dropout current
0.97Setting
Time setting
0.00s ~ 100.00s
Pickup time
35ms
Dropout time
35ms
1% Setting + 35ms
0.05In ~ 30.0In
Pickup current
1.00Setting
Dropout current
0.97Setting
Time setting
0.00s ~ 100.00s
Pickup time
35ms
Dropout time
35ms
1% Setting + 35ms
0.05In ~ 5.0In
Pickup current
1.00Setting
Dropout current
0.90Setting
Time setting
0.00s ~ 100.00s
Pickup time
35ms
Dropout time
35ms
1% Setting + 35ms
2-10
2 Technical Data
0.10 ~ 1.00
Pickup ratio
1.00Setting
Dropout ratio
0.95Setting
Time setting
0.00s ~ 200.00s
Pickup time
70ms
Dropout time
70ms
1% Setting + 70ms
0.05In ~ 5.0In
Pickup current
1.00Setting
Dropout current
0.95Setting
Time setting
0.00s ~ 100.00s
Pickup time
35ms
Dropout time
35ms
1% Setting + 35ms
0.1In ~ 1.0In
Pickup current
1.00Setting
Dropout current
1.10Setting
Time setting
0.00s ~ 100.00s
Pickup time
35ms
Dropout time
35ms
1% Setting + 35ms
Range
Accuracy
Phase range
0 ~ 360
0.5% or 1
Frequency
35.00Hz ~ 70.00Hz
0.01Hz
0.05 ~ 1.40In
0.2% of rating
Voltage
0.05 ~ 1.20Un
0.5% of rating
2-11
2 Technical Data
Apparent Power (VA)
0.5% of rating
Energy (Wh)
Energy (Varh)
0.05 ~ 1.40In
2.0% of rating
Voltage
0.05 ~ 1.20Un
0.5% of rating
3.0% of rating
Energy (Wh)
Energy (Varh)
Local or remote
1s
3s
3s/day
1ms
Maximum duration
Recording position
1ms
Potential-free contact
Resolution of SOE
2ms
2.4 Certification
z
ISO9001: 2000
ISO14001: 2004
OHSAS18001: 1999
ISO10012: 2003
2-12
2 Technical Data
CMMI L4
2-13
2 Technical Data
2-14
3 Operation Theory
3 Operation Theory
Table of Contents
3.1 Overview ...........................................................................................................3-1
3.2 Fault Detectors .................................................................................................3-1
3.3 Overcurrent Protection ....................................................................................3-4
3.3.1 Definite Time Overcurrent Protection................................................................................. 3-4
3.3.2 Inverse Definite Minimum Time Overcurrent Protection..................................................... 3-6
3.3.3 Voltage Control Element for Overcurrent Protection .......................................................... 3-8
3.3.4 Directional Element for Overcurrent Protection.................................................................. 3-9
3.3.5 Harmonic Blocking Element for Overcurrent Protection....................................................3-11
3.3.6 Overcurrent Protection Settings....................................................................................... 3-12
3 Operation Theory
3 Operation Theory
List of Figures
Figure 3.3-1 Demonstration characteristic of the overcurrent protection ........................... 3-5
Figure 3.3-2 Logic diagram of the stage 1 overcurrent protection ....................................... 3-5
Figure 3.3-3 Logic diagram of the stage 4 overcurrent protection ....................................... 3-7
Figure 3.3-4 Logic diagram of the OC1 phase A voltage control element ........................... 3-9
Figure 3.3-5 Operation characteristic of the OC directional element ................................. 3-10
Figure 3.3-6 Logic diagram of the OC1 phase A directional element ................................. 3-10
Figure 3.3-7 Logic diagram of the OC1 phase A harmonic blocking element ....................3-11
Figure 3.4-1 Characteristic curve of the thermal overload model ...................................... 3-15
3-c
3 Operation Theory
3 Operation Theory
Figure 3.17-6 Logic diagram of the dead check element for AR......................................... 3-56
Figure 3.18-1 Logic diagram of the manual closing function ............................................. 3-59
Figure 3.18-2 Logic diagram of the synchronism check element for manual closing...... 3-60
Figure 3.18-3 Logic diagram of the dead check element for manual closing.................... 3-61
Figure 3.19-1 Logic diagram of the No.1 mechanical protection........................................ 3-63
Figure 3.20-1 Logic diagram of the dead zone protection................................................... 3-64
Figure 3.21-1 Logic diagram of the undercurrent protection.............................................. 3-65
3-e
3 Operation Theory
3-f
3 Operation Theory
3.1 Overview
The PCS-9611 relay is a microprocessor based relay which can provide mature protection for
various primary equipments (such as overhead line, underground cable and transformer etc.). The
following sections detail the individual protection functions of this relay.
NOTE! In each functional element, the signal input [XXXX.En1] is used for inputting the
enabling signals; and the signal input [XXXX.Blk] is used for inputting the blocking signals.
The XXXX is the name code of the functional element (such as 50/51P1, 49,
50/51G2 etc.). They can be configured through PCS-Explorer configuration tool
auxiliary software. If the signal input [XXXX.En1] is not used, its default value is 1; and if
the signal input [XXXX.Blk] is not used, its default value is 0.
The startup conditions of the auto-recloser are satisfied if the auto-recloser is enabled and
ready for operating.
2.
Any one of the phase currents is in excess of the setting of the stage 1 overcurrent protection
multiplied by 0.95 if the stage 1 overcurrent protection is enabled.
3.
Any one of the phase currents is in excess of the setting of the stage 2 overcurrent protection
multiplied by 0.95 if the stage 2 overcurrent protection is enabled.
4.
Any one of the phase currents is in excess of the setting of the stage 3 overcurrent protection
multiplied by 0.95 if the stage 3 overcurrent protection is enabled.
5.
Any one of the phase currents is in excess of the setting of the stage 4 overcurrent protection
multiplied by 0.95 if the stage 4 overcurrent protection is enabled.
6.
The No.1 zero sequence current is in excess of the setting of the stage 1 of the No.1 zero
sequence overcurrent protection multiplied by 0.95 if the stage 1 of the No.1 zero sequence
overcurrent protection is enabled.
7.
The No.1 zero sequence current is in excess of the setting of the stage 2 of the No.1 zero
sequence overcurrent protection multiplied by 0.95 if the stage 2 of the No.1 zero sequence
overcurrent protection is enabled.
8.
The No.1 zero sequence current is in excess of the setting of the stage 3 of the No.1 zero
sequence overcurrent protection multiplied by 0.95 if the stage 1 of the No.3 zero sequence
overcurrent protection is enabled.
9.
The No.1 zero sequence current is in excess of the setting of the stage 4 of the No.1 zero
sequence overcurrent protection multiplied by 0.95 if the stage 1 of the No.4 zero sequence
overcurrent protection is enabled.
3-1
3 Operation Theory
10. The No.2 zero sequence current is in excess of the setting of the stage 1 of the No.2 zero
sequence overcurrent protection multiplied by 0.95 if the stage 1 of the No.2 zero sequence
overcurrent protection is enabled.
11. The No.2 zero sequence current is in excess of the setting of the stage 2 of the No.2 zero
sequence overcurrent protection multiplied by 0.95 if the stage 2 of the No.2 zero sequence
overcurrent protection is enabled.
12. The No.2 zero sequence current is in excess of the setting of the stage 3 of the No.2 zero
sequence overcurrent protection multiplied by 0.95 if the stage 3 of the No.2 zero sequence
overcurrent protection is enabled.
13. The No.2 zero sequence current is in excess of the setting of the stage 4 of the No.2 zero
sequence overcurrent protection multiplied by 0.95 if the stage 4 of the No.2 zero sequence
overcurrent protection is enabled.
14. The negative sequence current is in excess of the setting of the stage 1 negative sequence
overcurrent protection multiplied by 0.95 if the stage 1 negative sequence overcurrent
protection is enabled.
15. The negative sequence current is in excess of the setting of the stage 2 negative sequence
overcurrent protection multiplied by 0.95 if the stage 2 negative sequence overcurrent
protection is enabled.
16. The sensitive earth fault current is in excess of the current setting of the stage 1 sensitive
earth fault protection multiplied by 0.95 if the stage 1 sensitive earth fault protection is
enabled.
17. The sensitive earth fault current is in excess of the current setting of the stage 2 sensitive
earth fault protection multiplied by 0.95 if the stage 2 sensitive earth fault protection is
enabled.
18. The sensitive earth fault current is in excess of the current setting of the stage 3 sensitive
earth fault protection multiplied by 0.95 if the stage 3 sensitive earth fault protection is
enabled.
19. The sensitive earth fault current is in excess of the current setting of the stage 4 sensitive
earth fault protection multiplied by 0.95 if the stage 4 sensitive earth fault protection is
enabled.
20. Any one of the phase currents is in excess of the setting of the SOTF overcurrent protection
multiplied by 0.97 if the SOTF overcurrent protection is enabled.
21. The No.1 zero sequence current is in excess of the setting of the zero sequence SOTF
overcurrent protection multiplied by 0.97 if the zero sequence SOTF overcurrent protection is
enabled.
22. Any one of the phase currents is in excess of [49.K_Trp][49.Ib_Set] if the thermal overload
protection is enabled.
23. The ratio of negative to positive phase sequence current (I2/I1) is in excess of the ratio setting
3-2
3 Operation Theory
of the broken conductor protection multiplied by 0.95 if the broken conductor protection is
enabled.
24. Any one of the initiation signals of the breaker failure protection is detected if the breaker
failure protection is enabled.
25. The voltages are less than the setting of the stage 1 undervoltage protection multiplied by the
dropout coefficient setting of the stage 1 undervoltage protection if the stage 1 undervoltage
protection is enabled.
26. The voltages are less than the setting of the stage 2 undervoltage protection multiplied by the
dropout coefficient setting of the stage 2 undervoltage protection if the stage 1 undervoltage
protection is enabled.
27. The voltages are greater than the setting of the stage 1 overvoltage protection multiplied by
the dropout coefficient setting of the stage 1 overvoltage protection if the stage 1 overvoltage
protection is enabled.
28. The voltages are greater than the setting of the stage 2 overvoltage protection multiplied by
the dropout coefficient setting of the stage 2 overvoltage protection if the stage 2 overvoltage
protection is enabled.
29. The zero sequence voltage is greater than the setting of the stage 1 zero sequence
overvoltage protection multiplied by 0.95 if the stage 1 zero sequence overvoltage protection
is enabled.
30. The zero sequence voltage is greater than the setting of the stage 2 zero sequence
overvoltage protection multiplied by 0.95 if the stage 2 zero sequence overvoltage protection
is enabled.
31. The negative sequence voltage is greater than the setting of the negative sequence
overvoltage protection multiplied by 0.95 if the negative sequence overvoltage protection is
enabled.
32. The frequency is less than the setting of the stage 1 under-frequency protection and all the
phase-to-phase voltages are greater than the voltage setting of the voltage blocking element
of the frequency protection if the stage 1 under-frequency protection is enabled and ready for
operating.
33. The frequency is less than the setting of the stage 2 under-frequency protection and all the
phase-to-phase voltages are greater than the voltage setting of the voltage blocking element
of the frequency protection if the stage 2 under-frequency protection is enabled and ready for
operating.
34. The frequency is less than the setting of the stage 3 under-frequency protection and all the
phase-to-phase voltages are greater than the voltage setting of the voltage blocking element
of the frequency protection if the stage 3 under-frequency protection is enabled and ready for
operating.
35. The frequency is less than the setting of the stage 4 under-frequency protection and all the
3-3
3 Operation Theory
phase-to-phase voltages are greater than the voltage setting of the voltage blocking element
of the frequency protection if the stage 4 under-frequency protection is enabled and ready for
operating.
36. The frequency is greater than the setting of the stage 1 over-frequency protection and all the
phase-to-phase voltages are greater than the voltage setting of the voltage blocking element
of the frequency protection if the stage 1 over-frequency protection is enabled and ready for
operating.
37. The frequency is greater than the setting of the stage 2 over-frequency protection and all the
phase-to-phase voltages are greater than the voltage setting of the voltage blocking element
of the frequency protection if the stage 2 over-frequency protection is enabled and ready for
operating.
38. The rate-of-change of frequency is greater than the setting of the stage 1 frequency
rate-of-change protection if the stage 1 frequency rate-of-change protection is enabled.
39. The rate-of-change of frequency is greater than the setting of the stage 2 frequency
rate-of-change protection if the stage 2 frequency rate-of-change protection is enabled.
40. The rate-of-change of frequency is greater than the setting of the stage 3 frequency
rate-of-change protection if the stage 3 frequency rate-of-change protection is enabled.
41. The rate-of-change of frequency is greater than the setting of the stage 4 frequency
rate-of-change protection if the stage 4 frequency rate-of-change protection is enabled.
42. Anyone the binary inputs of the mechanical protections is energized if the corresponding
mechanical protection is enabled.
43. All the phase currents are less than the setting of the undercurrent protection multiplied by
1.10 if the undercurrent protection is enabled and the relevant circuit breaker is closed.
44. Anyone of the phase currents is greater than the setting of the dead zone protection multiplied
by 0.95 if the dead zone protection is enabled and the relevant circuit breaker is opened.
The FD (Fault Detector) element will reset to normal operation status 10s later if the auto-recloser
is enabled or 500ms later if the auto-recloser is disabled, after the last one of the above items is
reverted.
3 Operation Theory
The first three stages of overcurrent protection only have definite time characteristics, and they
have the same protective functional logic. The stage 4 overcurrent protection can be set as either
definite time (DT) or inverse definite minimum time (IDMT). The demonstration characteristic
figure of the DT overcurrent protection and IDMT overcurrent protection is shown as below.
tDelay
DT OC
tDelay
IDMT OC
50/51P2.t_Op
50/51P1.t_Op
50/51P2.I_Set
50/51P1.I_Set
Inom
Inom
The logic diagram of the stage 1 overcurrent protection is shown in Figure 3.3-2. The overcurrent
block is a level detector that detects whether the current magnitude is above the threshold.
The stage 2 overcurrent protection and the stage 3 overcurrent protection have the same logic
diagrams with the stage 1 overcurrent protection, but the operation thresholds are [50/51P2.I_Set]
and [50/51P3.I_Set] respectively.
The logic diagram of the stage 4 overcurrent protection with definite time characteristic is shown in
Figure 3.3-3, if the setting [50/51P4.Opt_Curve] is set as 0.
Where:
[50/51P1.I_Set] is the current setting of the stage 1 overcurrent protection;
tOC1 is the setting [50/51P1.t_Op], the time setting of the stage 1 overcurrent protection;
[50/51P1.En] is the logic setting of the stage 1 overcurrent protection;
3-5
3 Operation Theory
[50/51P1.En1] is the binary signal for enabling the stage 1 overcurrent protection;
[50/51P1.Blk] is the binary signal for blocking the stage 1 overcurrent protection;
50/51P1.VCE_x (x: A, B, C) denotes the state of the voltage control element of the stage 1
overcurrent protection, see Section 3.3.3 for more details about the voltage control element;
50/51P1.Dir_x (x: A, B, C) denotes the state of the directional element of the stage 1
overcurrent protection, see Section 3.3.4 for more details about the directional element;
50/51P1.HmBlk_x (x: A, B, C) denotes the harmonic blocking element of the stage 1
overcurrent protection, see Section 3.3.5 for more details about the harmonic blocking
element.
k
+ C Tp
t =
(I / I ) 1
Where:
k = Constant, the setting [50/51P4.K].
= Constant, the setting [50/51P4.Alpha].
C = Constant, the setting [50/51P4.C].
t = Operation time.
I = Measured phase current.
Ip is the current threshold setting; the current setting of the stage 4 overcurrent [50/51P4.I_Set]
is used as the Ip in this relay. If the stage 4 overcurrent protection is used as IDMT overcurrent
protection, the range of the setting [50/51P4.I_Set] is 0.05In ~ 4In.
Tp is the time multiplier setting; the multiplier setting of the IDMT overcurrent protection
[50/51P4.TMS] is used as Tp in this relay. If the stage 4 overcurrent protection is used as
IDMT overcurrent protection, the range of the setting [50/51P4.TMS] is 0.05 ~ 100.00.
3-6
3 Operation Theory
Some recommended types of IDMT characteristic curves are applied in this relay. It is also can be
programmed according to the demand of the special practical application through the
PCS-Explorer configuration tool auxiliary software.
The setting [50/51P4.Opt_Curve] can be used to select the expected curve.
Setting Value
Standard
Time Characteristic
Definite Time
IEC
Standard Inverse
0.14
0.02
0.00
IEC
Very Inverse
13.5
1.00
0.00
IEC
Extremely Inverse
80.0
2.00
0.00
IEC
0.05
0.04
0.00
IEC
120.0
1.00
0.00
IEEE (ANSI)
Extremely Inverse
28.20
2.00
0.1217
IEEE (ANSI)
Very Inverse
19.61
2.00
0.491
IEEE (ANSI)
Inverse
0.0086
0.02
0.0185
IEEE (ANSI)
Moderately Inverse
0.0515
0.02
0.114
10
IEEE (ANSI)
64.07
2.00
0.25
11
IEEE (ANSI)
28.55
2.00
0.712
12
IEEE (ANSI)
0.086
0.02
0.185
13
User Programmable
Where:
[50/51P4.I_Set] is the current setting of the stage 4 overcurrent protection;
3-7
3 Operation Theory
tOC4 is the setting [50/51P4.t_Op], the time setting of the stage 4 overcurrent protection;
[50/51P4.En] is the logic setting of the stage 4 overcurrent protection;
[50/51P4.En1] is the binary signal for enabling the stage 4 overcurrent protection;
[50/51P4.Blk] is the binary signal for blocking the stage 4 overcurrent protection;
[50/51P4.Opt_Curve] is the setting for selecting the inverse time characteristic curve;
50/51P4.VCE_x (x: A, B, C) denotes the state of the voltage control element of the stage 4
overcurrent protection, see Section 3.3.3 for more details about the voltage control element;
50/51P4.Dir_x (x: A, B, C) denotes the state of the directional element of the stage 4
overcurrent protection, see Section 3.3.4 for more details about the directional element;
50/51P4.HmBlk_x (x: A, B, C) denotes the harmonic blocking element of the stage 4
overcurrent protection, see Section 3.3.5 for more details about the harmonic blocking
element.
Ia>
Ib>
Ic>
Note that the voltage dependent overcurrent relays are more often applied in practical protection
applications in order to give adequate overcurrent relay sensitivity for close up fault conditions.
The fault characteristic of this protection must then coordinate with any of the downstream
overcurrent relays that are responsive to the current decrement condition. It therefore follows that
if this relay is to be applied on an outgoing feeder from a generator station, the use of voltage
controlled overcurrent protection in the feeder relay may allow better coordination with the VCO
relay on the generator.
For the operation accuracy of the VCO protection, it is necessary to take the status of the voltage
transformer into account. If the voltage transformer has a fault, the numerical relay will issue a
[VTS.Alm] signal and block all the elements that relate to the voltage measurement.
The logic diagram of the voltage control overcurrent protection is shown in Figure 3.3-2. Each
stage of the overcurrent protection can be set with voltage control by its relevant independent
setting respectively. The detailed logic diagram for the voltage control element of phase A for the
stage 1 overcurrent protection is shown as below. The logic diagrams for voltage control elements
3-8
3 Operation Theory
Figure 3.3-4 Logic diagram of the OC1 phase A voltage control element
Where:
[50/51P.Upp_VCE] is the voltage setting of the undervoltage control element;
[50/51P.U2_VCE] is the voltage setting of the negative sequence overvoltage control element;
[VTS.En] is the logic setting of the protection voltage transformer supervision function;
[50/51P1.En_VCE] is the logic setting of the voltage control element for the OC1 protection;
[50/51P.En_VTS_Blk] is the logic setting of the function which can block all the OC protective
elements that relate to the voltage measurement when the voltage transformer is failed;
[VTS.Alm] is the alarm signal of the protection voltage transformer supervision.
Operate Current
Polarizing Voltage
A Phase
Ia
Ubc
B Phase
Ib
Uca
C Phase
Ic
Uab
Under system fault conditions, the fault current vector will lag its nominal phase voltage by an
angle dependent upon the system X/R ratio. It is therefore a requirement that the relay operates
with maximum sensitivity for currents lying in this region. This is achieved by means of the relay
characteristic angle (RCA) setting; this defines the angle by which the current applied to the relay
must be displaced from the voltage applied to the relay to obtain maximum relay sensitivity.
For a close up three-phase fault, all three voltages will collapse to zero and no healthy phase
voltage will be present. For this reason, the relay includes a synchronous polarization feature that
stores the pre-fault positive sequence voltage information and continues to apply it to the
directional overcurrent elements for a time period of 25 fundamental wave cycles, after which, it
will keep the result of the directional element, this ensures that either the instantaneous or the time
delayed directional overcurrent elements will be allowed to operate, even with a three-phase
voltage collapse.
The relay characteristic angle (RCA) is configurable through the setting [50/51P.RCA]. A
3-9
3 Operation Theory
RCA
I
Forward
The setting [50/51Px.Opt_Dir] (x: 1~4) is used to select the directional mode for the stage x (x: 1~4)
overcurrent protection respectively.
Setting Value
Directional Mode
Non-directional
Forward directional
Reverse directional
Any of the four overcurrent stages may be configured to be directional. When the element is
selected as directional, a VTS block option is available. When the relevant setting is set as 1,
operation of the voltage transformer supervision (VTS) will block the stage if the relevant
directional element is in service. When the relevant setting is set as 0, the stage will revert to
non-directional upon operation of the VTS.
The logic diagram of the phase directional overcurrent protection is shown in Figure 3.3-2. Each
stage of the overcurrent protection can be set with directional element control by its relevant
independent setting respectively. The detailed logic diagram for the phase A directional element
for the stage 1 overcurrent protection is shown as below. The logic diagrams of voltage control
elements of phase B and phase C can be gotten on the analogy of this.
[50/51P.En_VTS_Blk]
[VTS.En]
[VTS.Alm]
Ia (present measure)
Ubc(present measure)
Ubc(in memory)
&
Phase A
Direction
Check
50/51P1.Dir_A
[50/51P1.Opt_Dir] 0
Where:
[50/51P1.Opt_Dir] is the setting which is used to select the directional mode (non-directional,
3-10
3 Operation Theory
forward, reverse) of the directional element for the stage 1 overcurrent protection;
[VTS.En] is the logic setting of the protection voltage transformer supervision function;
[50/51P.En_VTS_Blk] is the logic setting of the function which can block all the OC protective
elements that relate to the voltage measurement when the voltage transformer is failed;
[VTS.Alm] is the alarm signal of the protection voltage transformer supervision.
Phase B
Phase blocking
Cross blocking
Maximum blocking
Phase C
Ic2/ Ic1 >
Max(Ia2, Ib2, Ic2)/ Ic1 >
When the fundamental current is greater than the setting [50/51P.I_Rls_HmBlk], the harmonic
blocking element of the corresponding phase is released.
The following figure shows the logic diagram of the harmonic blocking element of phase A for the
stage 1 overcurrent protection. The logic diagrams of the harmonic blocking elements of phase B
and phase C can be gotten on the analogy of this.
Figure 3.3-7 Logic diagram of the OC1 phase A harmonic blocking element
Where:
[50/51P1.En_HarmBlk] is the logic setting of the harmonic blocking element of the stage 1
overcurrent protection;
[50/51P.K_Hm2] is the percent setting of the harmonic blocking element for OC protection;
[50/51P.I_Rls_HmBlk] is the current setting for releasing the harmonic blocking element;
[50/51P.Opt_Hm_Blk] is the setting for selecting the harmonic blocking criterion;
3-11
3 Operation Theory
Ix1 (x: a, b or c) is the fundamental current; Ix2 (x: a, b or c) is the 2nd harmonic current;
Imax is the maximum phase current; Imax2 is the maximum 2nd harmonic current.
Menu text
50/51P.U2_VCE
50/51P.Upp_VCE
50/51P.RCA
Explanation
The voltage setting of the negative sequence
voltage blocking element (phase voltage)
The voltage setting of the low voltage blocking
element (phase-to-phase voltage)
The relay characteristic angle for the directional
overcurrent protection
Range
Step
2~70V
0.001V
2~120V
0.001V
-180~179
0~1
0.05~1.00
0.001
0.05In~30In
0.001A
1~3
0.05In~30In
0.001A
0~100s
0.001s
0~1
0~2
0~1
0~1
50/51P.En_VTS_Blk
50/51P.K_Hm2
50/51P.I_Rls_HmBlk
50/51P.Opt_Hm_Blk
50/51P1.I_Set
50/51P1.t_Op
10
50/51P1.En_VCE
11
50/51P1.Opt_Dir
12
50/51P1.En_Hm_Blk
13
50/51P1.En
14
50/51P1.OutMap
15
50/51P2.I_Set
16
50/51P2.t_Op
0x00000000 ~
overcurrent protection
0x7FFFFFFF
3-12
0.05In~30In
0.001A
0~100s
0.001s
3 Operation Theory
17
50/51P2.En_VCE
0~1
0~2
0~1
0~1
50/51P2.Opt_Dir
19
50/51P2.En_Hm_Blk
20
50/51P2.En
21
50/51P2.OutMap
22
50/51P3.I_Set
23
50/51P3.t_Op
24
50/51P3.En_VCE
0x00000000 ~
overcurrent protection
0x7FFFFFFF
0.05In~30In
0.001A
0~100s
0.001s
0~1
0~2
0~1
0~1
50/51P3.Opt_Dir
26
50/51P3.En_Hm_Blk
27
50/51P3.En
28
50/51P3.OutMap
29
50/51P4.I_Set
30
50/51P4.t_Op
31
50/51P4.En_VCE
0x00000000 ~
overcurrent protection
0x7FFFFFFF
0.05In~30In
0.001A
0~100s
0.001s
0~1
0~2
0~1
0~1
50/51P4.Opt_Dir
33
50/51P4.En_Hm_Blk
34
50/51P4.En
35
50/51P4.OutMap
36
50/51P4.Opt_Curve
0x00000000 ~
overcurrent protection
0x7FFFFFFF
0~13
1
1
3-13
3 Operation Theory
37
50/51P4.TMS
38
50/51P4.tmin
39
50/51P4.K
40
50/51P4.C
41
50/51P4.Alpha
0.05~100.0
0.001
0~100s
0.001s
0.001~120.0
0.0001
0.00~1.00
0.0001
0.01~3.00
0.0001
T = ln
z
I2
I 2 (k I B ) 2
T = ln
I 2 I p2
I 2 (k I B ) 2
Where:
T = Time to trip (in seconds);
3 Operation Theory
The 1st ~ 7th harmonics of the phase current are taken into account in the calculation of the RMS
value of the largest phase current.
The input signal [49.Clr] (it can be led from a binary input of this relay) can clear the thermal
accumulation without blocking the thermal overload protection, if it is energized.
The thermal overload protection also can be used to issue an alarm signal [49.Alm], if the logic
setting [49.En_Alm] is set as 1.
The logic diagram of the thermal overload protection is shown as below.
Where:
Imax_rms is the maximum RMS phase current;
[49.K_Trp] is the factor setting of the thermal overload protection;
[49.Ib_Set] is the reference current setting of the thermal overload protection;
3-15
3 Operation Theory
Menu text
49.Ib_Set
49.Tau
49.K_Trp
Explanation
The reference current setting of the thermal
overload protection
The time constant setting of the IDMT overload
protection
Range
Step
0.05In~3.0In
0.001A
10~6000s
0.001s
1.0~3.0
0.001
1.0~3.0
0.001
0~1
0~1
49.K_Alm
49.En_Trp
49.En_Alm
49.OutMap
0x00000000 ~
protection
0x7FFFFFFF
3-16
3 Operation Theory
When this relay is used in non-effective grounding (such as the delta side of a transformer) or
small current grounding system, the grounding zero sequence current during earth fault is
basically small capacitive current. Correct selection of faulty phase in zero sequence protection
can not be ensured by detection of such a current. Since all protection equipments are connected
with each other via network and information resource can be shared in the substation automation
system, so the faulty feeder can be identified firstly by comparing information from various feeders
which are connected to the same busbar and then decided finally by trial tripping of the circuit
breaker of the selected feeder. In this case, the zero sequence current has to be led from a zero
sequence current transformer.
When this relay is used in small resistance grounding system, the grounding zero sequence
current during earth fault is larger and can be used for tripping directly. All stages are equipped for
the zero sequence current protection. In this case, the zero sequence current for tripping can be
calculated or directly led from a zero sequence current transformer.
Here, take the No.1 zero sequence overcurrent protection as an example to explain the operation
theory of the zero sequence overcurrent protection. The operation theory of the No.2 zero
sequence overcurrent protection can be gotten on the analogy of this.
The following figure shows the logic diagram of the No.1 zero sequence protection. The No.2 zero
sequence protection has the same logic diagram with the No.1 zero sequence protection.
Figure 3.5-1 Logic diagram of the No.1 zero sequence overcurrent protection
Where:
3-17
3 Operation Theory
[50/51Gx.3I0_Set] (x: 1~4) is the current setting of the stage x (x: 1~4) zero sequence
overcurrent protection;
tROCx (x: 1~4) is the setting [50/51Gx.t_Op] (x: 1~4), the time setting of the stage x (x: 1~4)
zero sequence overcurrent protection;
[50/51Gx.En] (x: 1~4) is the logic setting of the stage x (x: 1~4) zero sequence overcurrent
protection;
[50/51Gx.En1] (x: 1~4) is the binary signal for enabling the stage x (x: 1~4) zero sequence
overcurrent protection;
[50/51Gx.Blk] (x: 1~4) is the binary signal for blocking the stage x (x: 1~4) zero sequence
overcurrent protection;
[50/51G4.Opt_Curve] is the setting for selecting the inverse time characteristic curve;
50/51Gx.Dir (x: 1~4) denotes the status of the zero sequence directional element, see
Section 3.5.3 for more details about the directional element;
50/51Gx.HmBlk (x: 1~4) denotes the status of the harmonic blocking element, see Section
3.5.4 for more details about the harmonic blocking element.
Figure 3.5-2 Logic diagram of the No.1 zero sequence IDMT overcurrent protection
Where:
[50/51G4.3I0_Set] is the current setting of the No.1 stage 4 ROC protection;
[50/51G4.En] is the logic setting of the No.1 stage 4 ROC protection;
[50/51G4.En1] is the binary signal for enabling the stage 4 ROC protection;
[50/51G4.Blk] is the binary signal for blocking the stage 4 ROC protection;
3-18
3 Operation Theory
[50/51G4.Opt_Curve] is the setting for selecting the inverse time characteristic curve;
50/51G4.Dir denotes the status of the zero sequence directional element for the No.1 stage
4 zero sequence overcurrent protection, see Section 3.5.3 for more details about the
directional element;
50/51G4.HmBlk denotes the status of the harmonic blocking element for the No.1 stage 4
zero sequence overcurrent protection, see Section 3.5.4 for more details about the harmonic
blocking element.
Directional forward
-90 < (angle(U0) - angle(I01) - ZS-RCA) < 90
Directional reverse
-90 > (angle(U0) - angle(I01) - ZS-RCA) > 90
The setting [50/51Gx.Opt_Dir] (x: 1~4) is used to select the directional mode for the stage x (x:
1~4) zero sequence overcurrent protection respectively.
3-19
3 Operation Theory
Setting Value
Directional Mode
Non-directional
Forward directional
Reverse directional
When the element is selected as directional, a VTS block option is available. When the relevant
setting is set as 1, operation of the voltage transformer supervision (VTS) will block the stage if
the relevant directional element is in service. When the relevant setting is set as 0, the stage will
revert to non-directional upon operation of the VTS.
The detailed logic diagram of the zero sequence directional element of the stage 1 zero sequence
overcurrent protection is shown as below.
Figure 3.5-4 Logic diagram of the directional element for the No.1 ROC1 protection
Where:
[50/51G1.Opt_Dir] is the setting which is used to select the directional mode (non-directional,
forward, reverse) of the directional element for the stage 1 ROC protection;
[VTS.En] is the logic setting of the protection voltage transformer supervision function;
[50/51G.En_VTS_Blk] is the logic setting of the function which blocks all the 1ROC protective
elements that relate to the voltage measurement when the voltage transformer is failed;
[VTS.Alm] is the alarm signal of the protection voltage transformer supervision.
Figure 3.5-5 Logic diagram of the No.1 ROC1 harmonic blocking element
3-20
3 Operation Theory
Where:
[50/51G1.En_Hm_Blk] is the logic setting of the harmonic blocking element;
[50/51G.K_Hm2] is the percent setting of the harmonic blocking element;
[50/51G.3I0_Rls_HmBlk] is the current setting for releasing the harmonic blocking element;
I01 is the No.1 zero sequence current;
I012 is the 2nd harmonic of the No.1 zero sequence current.
Menu text
50/51G.RCA
50/51G.En_VTS_Blk
Explanation
The relay characteristic angle for the No.1
directional zero sequence overcurrent protection
Range
Step
-180~179
0~1
0.05~1.00
0.001
0.05In~30In
0.001A
0.05In~30In
0.001A
0~100s
0.001s
0~2
0~1
0~1
50/51G.K_Hm2
50/51G.3I0_Rls_HmBlk
50/51G1.3I0_Set
50/51G1.t_Op
50/51G1.Opt_Dir
50/51G1.En_Hm_Blk
50/51G1.En
10
50/51G1.OutMap
11
50/51G2.3I0_Set
12
50/51G2.t_Op
13
50/51G2.Opt_Dir
14
50/51G2.En_Hm_Blk
0x00000000 ~
0x7FFFFFFF
0.05In~30In
0.001A
0~100s
0.001s
0~2
0~1
3-21
3 Operation Theory
15
50/51G2.En
16
50/51G2.OutMap
17
50/51G3.3I0_Set
18
50/51G3.t_Op
19
50/51G3.Opt_Dir
20
50/51G3.En_Hm_Blk
21
50/51G3.En
22
50/51G3.OutMap
23
50/51G4.3I0_Set
24
50/51G4.t_Op
25
50/51G4.Opt_Dir
26
50/51G4.En_Hm_Blk
27
50/51G4.En
28
50/51G4.OutMap
29
50/51G4.Opt_Curve
30
50/51G4.TMS
31
50/51G4.tmin
32
50/51G4.K
33
50/51G4.C
34
50/51G4.Alpha
0~1
0x00000000 ~
0x7FFFFFFF
0.05In~30In
0.001A
0~100s
0.001s
0~2
0~1
0~1
0x00000000 ~
0x7FFFFFFF
0.001A
0~100s
0.001s
0~2
0~1
0~1
0x00000000 ~
0x7FFFFFFF
0.05In~30In
0~13
0.05~100.0
0.001
0~100s
0.001s
0.001~120.0
0.0001
0.00~1.00
0.0001
0.01~3.00
0.0001
All the settings of the No.2 zero sequence overcurrent protection are listed in the following table.
3-22
3 Operation Theory
No.
1
Menu text
A.50/51G.RCA
Explanation
The relay characteristic angle for the No.2
directional zero sequence overcurrent protection
Range
Step
-180~179
0~1
0.05~1.00
0.001
0.05In~30In
0.001A
0.05In~30In
0.001A
0~100s
0.001s
0~2
0~1
0~1
A.50/51G.En_VTS_Blk
A.50/51G.K_Hm2
A.50/51G.3I0_Rls_HmBlk
A.50/51G1.3I0_Set
A.50/51G1.t_Op
A.50/51G1.Opt_Dir
A.50/51G1.En_Hm_Blk
A.50/51G1.En
10
A.50/51G1.OutMap
11
A.50/51G2.3I0_Set
12
A.50/51G2.t_Op
13
A.50/51G2.Opt_Dir
14
A.50/51G2.En_Hm_Blk
15
A.50/51G2.En
16
A.50/51G2.OutMap
17
A.50/51G3.3I0_Set
18
A.50/51G3.t_Op
19
A.50/51G3.Opt_Dir
20
A.50/51G3.En_Hm_Blk
21
A.50/51G3.En
0x00000000 ~
0x7FFFFFFF
0.05In~30In
0.001A
0~100s
0.001s
0~2
0~1
0~1
0x00000000 ~
0x7FFFFFFF
0.05In~30In
0.001A
0~100s
0.001s
0~2
0~1
0~1
3-23
3 Operation Theory
22
A.50/51G3.OutMap
23
A.50/51G4.3I0_Set
24
A.50/51G4.t_Op
25
A.50/51G4.Opt_Dir
26
A.50/51G4.En_Hm_Blk
27
A.50/51G4.En
28
A.50/51G4.OutMap
29
A.50/51G4.Opt_Curve
30
A.50/51G4.TMS
31
A.50/51G4.tmin
32
A.50/51G4.K
33
A.50/51G4.C
34
A.50/51G4.Alpha
0x00000000 ~
0x7FFFFFFF
0.05In~30In
0.001A
0~100s
0.001s
0~2
0~1
0~1
0x00000000 ~
0x7FFFFFFF
0~13
0.05~100.0
0.001
0~100s
0.001s
0.001~120.0
0.0001
0.00~1.00
0.0001
0.01~3.00
0.0001
3 Operation Theory
Figure 3.6-1 Logic diagram for the stage 1 sensitive earth fault protection
Where:
[50/51SEF1.3I0_Set] is the current setting of the stage 1 sensitive earth fault protection;
tSEF1 is the setting [50/51SEF1.t_Op], the time setting of the SEF1 protection;
[50/51SEF1.En] is the logic setting of the stage 1 sensitive earth fault protection;
[50/51SEF1.En1] is the binary signal for enabling the stage 1 sensitive earth fault protection;
[50/51SEF1.Blk] is the binary signal for blocking the stage 1 sensitive earth fault protection;
50/51SEF1.Dir denotes the status of the directional element for the stage 1 sensitive earth
fault protection, see Section 3.6.3 for more details about the directional element.
Figure 3.6-2 Logic diagram of the IDMT sensitive earth fault protection
Where:
[50/51SEF4.3I0_Set] is the current setting of the stage 4 sensitive earth fault protection;
[50/51SEF4.En] is the logic setting of the stage 4 sensitive earth fault protection;
[50/51SEF4.En1] is the binary signal for enabling the stage 4 sensitive earth fault protection;
[50/51SEF4.Blk] is the binary signal for blocking the stage 4 sensitive earth fault protection;
3-25
3 Operation Theory
[50/51SEF4.Opt_Curve] is the setting for selecting the inverse time characteristic curve;
50/51SEF4.Dir denotes the status of the directional element for the stage 4 sensitive earth
fault protection, see Section 3.6.3 for more details about the directional element.
The setting [50/51SEFx.Opt_Dir] (x: 1~4) is used to select the directional mode for the stage x (x:
1~4) sensitive earth fault protection respectively.
Setting Value
Directional Mode
Non-directional
Forward directional
Reverse directional
When the element is selected as directional, a VTS block option is available. When the relevant
setting is set as 1, operation of the voltage transformer supervision (VTS) will block the stage if
the relevant directional element is in service. When the relevant setting is set as 0, the stage will
revert to non-directional upon operation of the VTS.
The detailed logic diagram of the directional element of the stage 1 sensitive earth fault protection
is shown as below.
3-26
3 Operation Theory
Figure 3.6-4 Logic diagram of the directional element for the stage 1 SEF protection
Where:
[50/51SEF1.Opt_Dir] is the setting which is used to select the directional mode
(non-directional, forward, reverse) of the directional element for the stage 1 SEF protection;
[VTS.En] is the logic setting of the protection voltage transformer supervision function;
[50/51SEF.En_VTS_Blk] is the logic setting of the function which can block all the SEF
protection that relate to the voltage measurement when the voltage transformer is failed;
[VTS.Alm] is the alarm signal of the protection voltage transformer supervision.
Menu text
50/51SEF.RCA
Explanation
The relay characteristic angle for the directional
sensitive earth fault protection
Range
Step
-180~179
0~1
0.005~0.4A
0.001A
0~100s
0.001s
0~2
0~1
50/51SEF.En_VTS_Blk
50/51SEF1.3I0_Set
50/51SEF1.t_Op
50/51SEF1.Opt_Dir
50/51SEF1.En
50/51SEF1.OutMap
50/51SEF2.3I0_Set
50/51SEF2.t_Op
10
50/51SEF2.Opt_Dir
0x00000000 ~
0x7FFFFFFF
0.005~0.4A
0.001A
0~100s
0.001s
0~2
3-27
3 Operation Theory
11
50/51SEF2.En
12
50/51SEF2.OutMap
13
50/51SEF3.3I0_Set
14
50/51SEF3.t_Op
15
50/51SEF3.Opt_Dir
16
50/51SEF3.En
17
50/51SEF3.OutMap
18
50/51SEF4.3I0_Set
19
50/51SEF4.t_Op
20
50/51SEF4.Opt_Dir
21
50/51SEF4.En
22
50/51SEF4.OutMap
23
50/51SEF4.Opt_Curve
24
50/51SEF4.TMS
25
50/51SEF4.tmin
26
50/51SEF4.K
27
50/51SEF4.C
28
50/51SEF4.Alpha
0~1
0x00000000 ~
0x7FFFFFFF
0.005~0.4A
0.001A
0~100s
0.001s
0~2
0~1
0x00000000 ~
0x7FFFFFFF
0.001A
0~100s
0.001s
0~2
0~1
0x00000000 ~
0x7FFFFFFF
0.005~0.4A
0~13
0.05~100.0
0.001
0~100s
0.001s
0.001~120.0
0.0001
0.00~1.00
0.0001
0.01~3.00
0.0001
3 Operation Theory
overheating in rotor end zones and the slot wedges. This especially goes for motors which are
tripped via vacuum contactors with fuses connected in series. With single phasing due to
operation of a fuse, the motor only generates small and pulsing torques such that it soon is
thermally strained assuming that the torque required by the machine remains unchanged. In
addition, the unbalanced supply voltage introduces the risk of thermal overload. Due to the small
negative sequence reactance even small voltage asymmetries lead to large negative sequence
currents.
This relay provides a two-stage negative sequence overcurrent protection with definite time delay
characteristics. Each stage can be enabled or disabled by scheme logic settings independently.
The two stages have same protection logics if they are set with definite time characteristics.
The logic diagram for the stage 1 negative sequence overcurrent protection is shown as below.
The negative sequence overcurrent block is a level detector that detects whether the negative
sequence current magnitude is above the threshold.
Where:
[50/51Q1.I2_Set] is the current setting of the stage 1 negative sequence overcurrent
protection;
tNOC1 is the setting [50/51Q1.t_Op], the time setting of the stage 1 negative sequence
overcurrent protection;
[50/51Q1.En] is the logic setting of the stage 1 negative sequence overcurrent protection;
[50/51Q1.En1] is the binary signal for enabling the NOC1 protection;
[50/51Q1.Blk] is the binary signal for blocking the NOC1 protection.
3-29
3 Operation Theory
Figure 3.7-2 Logic diagram of the IDMT negative sequence overcurrent protection
Where:
[50/51Q2.I2_Set] is the current setting of the stage 2 negative sequence overcurrent
protection;
[50/51Q2.En] is the logic setting of the stage 2 negative sequence overcurrent protection;
[50/51Q2.Opt_Curve] is the setting for selecting the inverse time characteristic curve;
[50/51Q2.En1] is the binary signal for enabling the NOC2 protection;
[50/51Q2.Blk] is the binary signal for blocking the NOC2 protection.
Menu text
50/51Q1.I2_Set
50/51Q1.t_Op
50/51Q1.En
50/51Q1.OutMap
50/51Q2.I2_Set
50/51Q2.t_Op
50/51Q2.En
50/51Q2.OutMap
50/51Q2.Opt_Curve
10
50/51Q2.TMS
11
50/51Q2.tmin
Explanation
The current setting of the stage 1 negative
sequence overcurrent protection
The time setting of the stage 1 negative sequence
overcurrent protection
The logic setting of the stage 1 negative sequence
overcurrent protection
Range
Step
0.05In~4In
0.001A
0~100s
0.001s
0~1
0x00000000 ~
0x7FFFFFFF
0.05In~4In
0.001A
0~100s
0.001s
0~1
0x00000000 ~
0x7FFFFFFF
3-30
0~13
0.05~100.0
0.001
0~100s
0.001s
3 Operation Theory
12
50/51Q2.K
13
50/51Q2.C
14
50/51Q2.Alpha
0.001~120.0
0.0001
0.00~1.00
0.0001
0.01~3.00
0.0001
Where:
[50BC.I2/I1_Set] is the ratio setting of the broken conductor protection;
tBCP is the setting [50BC.t_Op], the time setting of the broken conductor protection;
[50BC.En] is the logic setting of the broken conductor protection;
[50BC.En1] is the binary signal for enabling the broken conductor protection;
[50BC.Blk] is the binary signal for blocking the broken conductor protection.
Menu text
50BC.I2/I1_Set
Explanation
The ratio setting for the broken conductor
protection
Range
0.10~1.00
Step
0.001
3-31
3 Operation Theory
2
50BC.t_Op
50BC.En
50BC.OutMap
0~200s
0.001s
0~1
0x00000000 ~
protection
0x7FFFFFFF
Only A
NOT([BI_52b])
Only B
A OR B
A AND B
3-32
3 Operation Theory
Ia > [50BF.I_Set]
Ib > [50BF.I_Set]
1 ONLY A
A
Ic > [50BF.I_Set]
[BI_52b]
3 A OR B
B
[50BF.Opt_LogicMode]
50BF.In_Init
2 ONLY B
[50BF.St]
4 A AND B
&
tBFP1
[50BF.Op]
tBFP2
[50BF.ReTrp]
[50BF.En]
[50BF.En1]
&
[50BF.Blk]
[50BF.En_ReTrp]
Where:
[50BF.I_Set] is the current setting of the breaker failure protection;
tBFP1 is the setting [50BF.t_Op], the time setting of the breaker failure protection;
tBFP2 is the setting [50BF.t_ReTrp] is the re-trip time setting of the breaker failure protection;
[50BF.En] is the logic setting of the breaker failure protection;
[50BF.En1] is the binary signal for enabling the breaker failure protection;
[50BF.Blk] is the binary signal for blocking the breaker failure protection;
[50BF.En_ReTrp] is the logic setting of re-trip function the breaker failure protection;
[50BF.Opt_LogicMode] is the setting for selecting the BFP criterion logic;
[BI_52b] is the binary input from the auxiliary normally closed contact of the circuit breaker;
50BF.In_Init is the initiation signal such as the external binary input trigger signal or the relay
tripping operation signal, and it can be configured through the PCS-Explorer configuration tool
auxiliary software.
The time setting of the breaker failure protection should be based on the maximum circuit breaker
operating time plus the dropout time of the current flow monitoring element plus a safety margin
which takes into consideration the tolerance of the time delay.
3 Operation Theory
No.
Menu text
50BF.I_Set
50BF.t_Op
50BF.t_ReTrp
50BF.Opt_LogicMode
50BF.En
50BF.En_ReTrp
50BF.OutMap
50BF.OutMap_ReTrp
Explanation
The current setting of the breaker failure
protection
The time setting of the breaker failure protection
The re-trip time setting of the breaker failure
protection
The setting for selecting the criteria logic of the
breaker failure protection
The logic setting of the breaker failure protection
The logic setting of the re-trip function of the
breaker failure protection
Range
Step
0.05In~5.0In
0.001A
0~100s
0.001s
0~100s
0.001s
1~4
0~1
0~1
0x00000000 ~
protection
0x7FFFFFFF
0x00000000 ~
0x7FFFFFFF
1
1
3-34
3 Operation Theory
Where:
[50PSOTF.I_Set] is the current setting of the SOTF overcurrent protection;
tSOTFOC is the setting [50PSOTF.t_Op], the time setting of the SOTF overcurrent protection;
[50PSOTF.En] is the logic setting of the SOTF overcurrent protection;
[50PSOTF.En1] is the binary signal for enabling the SOTF overcurrent protection;
[50PSOTF.Blk] is the binary signal for blocking the SOTF overcurrent protection;
[50GSOTF.3I0_Set] is the current setting of the zero sequence SOTF overcurrent protection;
tSOTFROC is the setting [50GSOTF.t_Op], the time setting of the zero sequence SOTF
overcurrent protection;
[50GSOTF.En] is the logic setting of the zero sequence SOTF overcurrent protection;
[50GSOTF.En1] is the binary signal for enabling the zero sequence SOTF overcurrent
protection;
[50GSOTF.Blk] is the binary signal for blocking the zero sequence SOTF overcurrent
protection;
[SOTF.Opt_Mode] is the setting for selecting the acceleration mode of the SOTF protection;
tEnSOTF is the setting [SOTF.t_En], the enabling time setting of the SOTF protection;
[79.Ready] is used to denote the auto-recloser is ready for operating;
[79.Close_3PSx] (x:1~4) means that the auto-recloser operates;
SOTF.ManClsCB denotes the circuit breaker is closed manually (local or remote), for
example, the circuit breaker is closed by the remote closing command from the SAS or
SCADA, or by pressing the closing button on the control panel.
3-35
3 Operation Theory
Menu text
SOTF.t_En
SOTF.Opt_Mode
50PSOTF.I_Set
50PSOTF.t_Op
50PSOTF.En
50PSOTF.OutMap
50GSOTF.3I0_Set
50GSOTF.t_Op
50GSOTF.En
10
50GSOTF.OutMap
Explanation
The enabling time setting of the SOTF protection
The setting for selecting the acceleration tripping
mode of the SOTF protection
The current setting of the SOTF overcurrent
protection
The time setting of the SOTF overcurrent
protection
The logic setting of the SOTF overcurrent
protection
Range
0~100s
0.001s
0~1
0.05In~30In
0.001A
0~100s
0.001s
0~1
0x00000000 ~
protection
0x7FFFFFFF
Step
0.05In~30In
0.001A
0~100s
0.001s
0~1
0x00000000 ~
0x7FFFFFFF
3 Operation Theory
CB auxiliary contact ([CLP.LogicMode] = 2). The signal [CLP.OnLoad] can be gotten from the
signal Prot.OnLoad through the PCS-Explorer.
If the CLP output CLP.St is 1, the CLP settings are enabled for the overcurrent protection and
the No.1 group of zero sequence overcurrent protection respectively. After the delay [CLP.t_Rst]
has elapsed, the normal protection settings are applied. And if a fast resetting signal is received,
the normal protection settings are applied after the delay [CLP.t_ShortRst].
[CLP.OnLoad]
[CLP.Opt_LogicMode] = 1
[BI_52b]
[CLP.Opt_LogicMode] = 2
[CLP.ShortRst]
&
tCold
S
R
&
tRst
&
tShortRst
Q
Q
&
&
[CLP.St_50/51]
[CLP.St]
[CLP.Init]
[CLP.En]
[CLP.Blk]
Where:
[CLP.OnLoad] is the signal denotes anyone of the phase currents is greater than 0.04In;
[CLP.LogicMode] is used for selecting the cold load condition mode;
[BI_52b] is the binary input for inputting the normally closed contact of the circuit breaker;
[CLP.ShortRst] is the binary signal of the short resetting function;
[CLP.St_50/51] is the binary signal which denotes anyone of the selected protective elements
picked up;
[CLP.Init] is the binary signal for initiating the cold load pickup logic function (for example, a
binary input signal from other relevant relay);
[CLP.En] is the logic setting of the cold load pickup logic function;
[CLP.Blk] is the binary signal for blocking the cold load pickup logic function;
tCold is the setting [CLP.t_Cold], the time setting for ensuring the cold load condition is met;
tRst is the setting [CLP.t_Rst], the time setting for resetting the cold load pickup logic function;
tShortRst is the setting [CLP.t_ShortRst], the time setting for fast resetting the cold load pickup
logic function.
3 Operation Theory
Menu text
CLP.Opt_LogicMode
CLP.t_Cold
CLP.t_Rst
CLP.t_ShortRst
CLP.En
50/51P1.CLP.IMult
50/51P1.CLP.t_Op
50/51P2.CLP.IMult
50/51P2.CLP.t_Op
10
50/51P3.CLP.IMult
11
50/51P3.CLP.t_Op
12
50/51P4.CLP.IMult
13
50/51P4.CLP.t_Op
14
50/51P4.CLP.TMS
15
50/51G1.CLP.IMult
16
50/51G1.CLP.t_Op
17
50/51G2.CLP.IMult
18
50/51G2.CLP.t_Op
19
50/51G3.CLP.IMult
20
50/51G3.CLP.t_Op
21
50/51G4.CLP.IMult
Explanation
The setting for selecting the cold load condition
The time setting for ensuring the cold load
condition is met
The time setting for resetting the cold load pickup
logic
The time setting for fast resetting the cold load
pickup logic
The logic setting of the cold load pickup logic
function
The multiple setting of the stage 1 overcurrent
protection when CLP is active
The time setting of the stage 1 overcurrent
protection when CLP is active
The multiple setting of the stage 2 overcurrent
protection when CLP is active
The time setting of the stage 2 overcurrent
protection when CLP is active
The multiple setting of the stage 3 overcurrent
protection when CLP is active
The time setting of the stage 3 overcurrent
protection when CLP is active
The multiple setting of the stage 4 overcurrent
protection when CLP is active
The time setting of the stage 4 overcurrent
protection when CLP is active
The time multiplier setting of the IDMT overcurrent
protection when CLP is active
The multiple setting of the stage 1 zero sequence
overcurrent protection when CLP is active
The time setting of the stage 1 zero sequence
overcurrent protection when CLP is active
The multiple setting of the stage 2 zero sequence
overcurrent protection when CLP is active
The time setting of the stage 2 zero sequence
overcurrent protection when CLP is active
The multiple setting of the stage 3 zero sequence
overcurrent protection when CLP is active
The time setting of the stage 3 zero sequence
overcurrent protection when CLP is active
The multiple setting of the stage 4 zero sequence
overcurrent protection when CLP is active
3-38
Range
Step
1~2
0~4000s
0.001s
0~4000s
0.001s
0~600s
0.001s
0~1
1.00~10.00
0.001
0~100s
0.001s
1.00~10.00
0.001
0~100s
0.001s
1.00~10.00
0.001
0~100s
0.001s
1.00~10.00
0.001
0~100s
0.001s
0.05~100.0
0.001
1.00~10.00
0.001
0~100s
0.001s
1.00~10.00
0.001
0~100s
0.001s
1.00~10.00
0.001
0~100s
0.001s
1.00~10.00
0.001
3 Operation Theory
22
50/51G4.CLP.t_Op
23
50/51G1.CLP.TMS
0~100s
0.001s
0.05~100.0
0.001
Figure 3.12-1 Logic diagram of the system lost voltage for the UV1 protection
The following figure shows the logic diagram of the stage 1 undervoltage protection.
3-39
3 Operation Theory
Where:
[27P1.U_Set] is the voltage setting of the stage 1 undervoltage protection;
tUV1 is the setting [27P1.t_Op], the time setting of the stage 1 undervoltage protection;
[27P.Opt_1P/3P] is the logic setting for selecting the undervoltage calculation method;
[27P.Opt_Up/Upp] is the logic setting for deciding the voltage input mode;
[27P1.En] is the logic setting of the stage 1 undervoltage protection;
[27P1.En1] is the binary signal for enabling the stage 1 undervoltage protection;
[27P1.Blk] is the binary signal for blocking the stage 1 undervoltage protection;
[BI_52b] is the binary input from the auxiliary normally closed contact of the circuit breaker;
27P1.LostVolt denotes whether the system voltage is lost.
Menu text
27P.Opt_1P/3P
27P.Opt_Up/Upp
27P1.U_Set
Explanation
The
setting
for
selecting
Range
the
undervoltage
3-40
Step
0~1
0~1
2~120V
0.001V
3 Operation Theory
4
27P1.t_Op
27P1.K_DropOut
27P1.En
27P1.OutMap
27P2.U_Set
27P2.t_Op
10
27P2.K_DropOut
11
27P2.En
12
27P2.OutMap
0~100s
0.001s
1.03~3.0
0.001
0~1
0x00000000 ~
undervoltage protection
0x7FFFFFFF
2~120V
0.001V
0~100s
0.001s
1.03~3.0
0.001
0~1
0x00000000 ~
undervoltage protection
0x7FFFFFFF
3 Operation Theory
The following figure shows the logic diagram of the stage 1 overvoltage protection.
Where:
[59P1.U_Set] is the voltage setting of the stage 1 overvoltage protection;
tOV1 is the setting [59P1.t_Op], the time setting of the stage 1 overvoltage protection;
[59P.Opt_1P/3P] is the logic setting for selecting the overvoltage calculation method;
[59P.Opt_Up/Upp] is the logic setting for deciding the voltage input mode;
[59P1.En] is the logic setting of the stage 1 overvoltage protection;
[59P1.En1] is the binary signal for enabling the stage 1 overvoltage protection;
[59P1.Blk] is the binary signal for blocking the stage 1 overvoltage protection.
Menu text
59P.Opt_1P/3P
59P.Opt_Up/Upp
59P1.U_Set
59P1.t_Op
59P1.K_DropOut
Explanation
The
setting
for
selecting
Range
the
overvoltage
3-42
Step
0~1
0~1
57.7~200V
0.001V
0~100s
0.001s
0.93~0.97
0.001
3 Operation Theory
6
59P1.En
59P1.OutMap
59P2.U_Set
59P2.t_Op
10
59P2.K_DropOut
11
59P2.En
12
59P2.OutMap
0~1
0x00000000 ~
overvoltage protection
0x7FFFFFFF
1
1
57.7~200V
0.001V
0~100s
0.001s
0.93~0.97
0.001
0~1
0x00000000 ~
overvoltage protection
0x7FFFFFFF
Where:
[59G1.3U0_Set] is the voltage setting of the stage 1 zero sequence overvoltage protection;
3-43
3 Operation Theory
tROV1 is the setting [59G1.t_Op], the time setting of the stage 1 zero sequence overvoltage
protection;
[59G1.En] is logic setting of the stage 1 zero sequence overvoltage protection.
[59G1.En1] is the binary signal for enabling the stage 1 zero sequence overvoltage protection;
[59G1.Blk] is the binary signal for blocking the stage 1 zero sequence overvoltage protection.
Menu text
59G1.3U0_Set
59G1.t_Op
59G1.En
59G1.OutMap
59G2.3U0_Set
59G2.t_Op
59G2.En
59G2.OutMap
Explanation
The voltage setting of the stage 1 zero sequence
overvoltage protection
The time setting of the stage 1 zero sequence
overvoltage protection
The logic setting of the stage 1 zero sequence
overvoltage protection
Range
2~160V
0.001V
0~100s
0.001s
0~1
0x00000000 ~
0x7FFFFFFF
Step
2~160V
0.001V
0~100s
0.001s
0~1
0x00000000 ~
0x7FFFFFFF
3-44
3 Operation Theory
Where:
[59Q.U2_Set] is the voltage setting of the negative sequence overvoltage protection;
tNOV is the setting [59Q.t_Op], the time setting of the negative sequence overvoltage
protection;
[59Q.En] is logic setting of the negative sequence overvoltage protection.
[59Q.En1] is the binary signal for enabling the negative sequence overvoltage protection;
[59Q.Blk] is the binary signal for blocking the negative sequence overvoltage protection.
Menu text
59Q.U2_Set
59Q.t_Op
59Q.En
59Q.OutMap
Explanation
The voltage setting of the negative sequence
overvoltage protection
The time setting of the negative sequence
overvoltage protection
The logic setting of the negative sequence
overvoltage protection
Range
Step
2~120V
0.001V
0~100s
0.001s
0~1
0x00000000 ~
0x7FFFFFFF
3 Operation Theory
removed from the system, or again when a malfunction occurs with a generator governor. This
entails risk of self-excitation for generators feeding long lines under no-load conditions.
The calculation of the frequency is based on the voltage sampled values. Four cycles of the
voltage sampled values are fixedly adopted for the frequency calculation.
Where:
[81U1.f_Set] is the frequency setting of the stage 1 under-frequency protection;
tUF1 is the setting [81U1.t_Op], the time setting of the stage 1 under-frequency protection;
[81.Upp_VCE] is the under voltage blocking setting of the frequency protection;
[81U1.En] is the logic setting of the stage 1 under-frequency protection;
[81U1.En1] is the binary signal for enabling the stage 1 under-frequency protection;
[81U1.Blk] is the binary signal for blocking the stage 1 under-frequency protection.
3 Operation Theory
Where:
[81O1.f_Set] is the frequency setting of the stage 1 over-frequency protection;
tOF1 is the setting [81O1.t_Op], the time setting of the stage 1 over-frequency protection;
[81.Upp_VCE] is the under voltage blocking setting of the frequency protection;
[81O1.En] is the logic setting of the stage 1 over-frequency protection;
[81O1.En1] is the binary signal for enabling the stage 1 over-frequency protection;
[81O1.Blk] is the binary signal for blocking the stage 1 over-frequency protection.
Where:
[81R1.df/dt_Set] is the setting of the stage 1 frequency rate-of-change protection;
3-47
3 Operation Theory
tFRCP1 is the setting [81R1.t_Op], the time setting of the stage 1 frequency rate-of-change
protection;
[81R1.f_Pkp] is the pickup frequency setting of the stage 1 frequency rate-of-change
protection;
[81R1.En] is the logic setting of the stage 1 frequency rate-of-change protection;
[81R1.En1] is the binary signal for enabling the stage 1 frequency rate-of-change protection;
[81R1.Blk] is the binary signal for blocking the stage 1 frequency rate-of-change protection.
The calculation of the rate-of-change of frequency is based on the calculated frequency values.
Four cycles of the calculated frequency values are fixedly adopted for the calculation of the
rate-of-change of frequency in this relay.
Menu text
81.Upp_VCE
81U1.f_Set
81U1.t_Op
81U1.En
81U1.OutMap
81U2.f_Set
81U2.t_Op
81U2.En
81U2.OutMap
10
81U3.f_Set
11
81U3.t_Op
12
81U3.En
13
81U3.OutMap
Explanation
Range
frequency
setting
of
the
stage
under-frequency protection
The time setting of the stage 1 under-frequency
protection
The logic setting of the stage 1 under-frequency
protection
10~120V
0.001V
45~60Hz
0.001Hz
0~100s
0.001s
0~1
0x00000000 ~
under-frequency protection
0x7FFFFFFF
The
frequency
setting
of
the
stage
under-frequency protection
The time setting of the stage 2 under-frequency
protection
The logic setting of the stage 2 under-frequency
protection
0.001Hz
0~100s
0.001s
0~1
0x00000000 ~
under-frequency protection
0x7FFFFFFF
frequency
setting
of
the
stage
under-frequency protection
The time setting of the stage 3 under-frequency
protection
The logic setting of the stage 3 under-frequency
protection
45~60Hz
0.001Hz
0~100s
0.001s
0~1
0x00000000 ~
under-frequency protection
0x7FFFFFFF
3-48
45~60Hz
Step
3 Operation Theory
14
81U4.f_Set
15
81U4.t_Op
16
81U4.En
17
81U4.OutMap
18
81O1.f_Set
19
81O1.t_Op
20
81O1.En
21
81O1.OutMap
22
81O2.f_Set
23
81O2.t_Op
24
81O2.En
25
81O2.OutMap
26
81O3.f_Set
27
81O3.t_Op
28
81O3.En
29
81O3.OutMap
30
81O4.f_Set
31
81O4.t_Op
32
81O4.En
33
81O4.OutMap
34
81R1.df/dt_Set
35
81R1.f_Pkp
The
frequency
setting
of
the
stage
under-frequency protection
The time setting of the stage 4 under-frequency
protection
The logic setting of the stage 4 under-frequency
protection
45~60Hz
0.001Hz
0~100s
0.001s
0~1
0x00000000 ~
under-frequency protection
0x7FFFFFFF
The
frequency
setting
of
the
stage
over-frequency protection
The time setting of the stage 1 over-frequency
protection
The logic setting of the stage 1 over-frequency
protection
50~65Hz
0.001Hz
0~100s
0.001s
0~1
0x00000000 ~
over-frequency protection
0x7FFFFFFF
The
frequency
setting
of
the
stage
over-frequency protection
The time setting of the stage 2 over-frequency
protection
The logic setting of the stage 2 over-frequency
protection
0.001Hz
0~100s
0.001s
0~1
0x00000000 ~
over-frequency protection
0x7FFFFFFF
frequency
setting
of
the
stage
over-frequency protection
The time setting of the stage 3 over-frequency
protection
The logic setting of the stage 3 over-frequency
protection
0.001Hz
0~100s
0.001s
0~1
0x00000000 ~
over-frequency protection
0x7FFFFFFF
frequency
setting
of
the
stage
over-frequency protection
The time setting of the stage 4 over-frequency
protection
The logic setting of the stage 4 over-frequency
protection
0.001Hz
0~100s
0.001s
0~1
0x00000000 ~
over-frequency protection
0x7FFFFFFF
setting
of
the
stage
frequency
rate-of-change protection
The pickup frequency setting of the stage 1
frequency rate-of-change protection
50~65Hz
50~65Hz
50~65Hz
-10~10Hz/s
45~65Hz
1
0.001
Hz/s
0.001Hz
3-49
3 Operation Theory
36
81R1.t_Op
37
81R1.En
38
81R1.OutMap
39
81R2.df/dt_Set
40
81R2.f_Pkp
41
81R2.t_Op
42
81R2.En
43
81R2.OutMap
44
81R3.df/dt_Set
45
81R3.f_Pkp
46
81R3.t_Op
47
81R3.En
48
81R3.OutMap
49
81R4.df/dt_Set
50
81R4.f_Pkp
51
81R4.t_Op
52
81R4.En
53
81R4.OutMap
0~100s
0.001s
0~1
0x00000000 ~
rate-of-change protection
0x7FFFFFFF
The
setting
of
the
stage
frequency
rate-of-change protection
The pickup frequency setting of the stage 2
frequency rate-of-change protection
The time setting of the stage 2 frequency
rate-of-change protection
The logic setting of the stage 2 frequency
rate-of-change protection
-10~10Hz/s
0~100s
0.001s
0~1
rate-of-change protection
0x7FFFFFFF
of
the
stage
frequency
rate-of-change protection
The pickup frequency setting of the stage 3
frequency rate-of-change protection
The time setting of the stage 3 frequency
rate-of-change protection
The logic setting of the stage 3 frequency
rate-of-change protection
-10~10Hz/s
0.001s
0~1
0x7FFFFFFF
the
stage
frequency
rate-of-change protection
The pickup frequency setting of the stage 4
frequency rate-of-change protection
The time setting of the stage 4 frequency
rate-of-change protection
The logic setting of the stage 4 frequency
rate-of-change protection
Hz/s
0~100s
rate-of-change protection
of
0.001
0.001Hz
0x00000000 ~
setting
45~65Hz
Hz/s
0.001Hz
0x00000000 ~
setting
0.001
45~65Hz
-10~10Hz/s
1
0.001
Hz/s
45~65Hz
0.001Hz
0~100s
0.001s
0~1
0x00000000 ~
rate-of-change protection
0x7FFFFFFF
3.17 Auto-recloser
3.17.1 Auto-recloser Theory
This relay can support up to 4-shot auto-recloser. This relay will initiate the auto-recloser for fault
clearance by the phase overcurrent protection, the earth fault protection etc. (which can be
configured through PCS-Explorer). An auto-reclosing cycle can be internally initiated by operation
3-50
3 Operation Theory
of a protection element or externally by a separate protection device, provided the circuit breaker
(CB) is closed until the instant of protection operation. At the end of the dead time of each shot, if
all the auto-reclosing conditions are satisfied, a circuit breaker close signal is given. The
auto-reclosing output time pulse width is configurable through the setting [79.t_DDO_AR].
The system conditions to be met for closing are that the system voltages are in synchronism or
dead line/live busbar or live line/dead busbar conditions exist, indicated by the internal check
synchronism element and that the circuit breaker closing spring, or other energy source, is fully
charged indicated from the binary input [BI_LowPres_Cls]. The CB close signal is cut-off when the
circuit breaker is closed.
If the CB position check function is enabled (the setting [79.En_FailChk] is set as 1), the
auto-recloser detects the CB position in the period [79.t_Fail] after the auto-reclosing command is
issued. If the CB closed position condition is not met in the period [79.t_Fail], the auto-recloser can
not operate successfully, and the signal [79.Fail] will be issued.
When the auto-reclosing command is issued, the reclaim timer starts. If the circuit breaker does
not trip again, the auto-recloser resets at the end of the reclaim time. If the protection operates
during the reclaim time delay [79.t_Reclaim], this relay either advances to the next shot in the
programmed auto-reclosing cycle, or it goes to lockout if all programmed reclose attempts have
been made. The reclaim time should be set long enough to allow this relay to operate when the
circuit breaker is automatically closed onto a fault.
If any blocking condition is met in the process of the auto-recloser, the auto-recloser will be
blocked at once. And if any shot of the auto-recloser can not operate successfully, the signal
[79.Fail] will be issued.
z
Single-shot Reclosing
When a trip signal is programmed to initiate the automatic reclosing system, the appropriate
automatic reclosing program will be executed. Once the circuit breaker has opened, a dead
time interval in accordance with the type of fault is started. Once the dead time interval has
elapsed, a closing signal is issued to reclose the circuit breaker.
If the fault is cleared, the reclaim time expires and the automatic reclosing is reset in
anticipation of a future fault. The fault is cleared.
If the fault is not cleared, then a final tripping signal is initiated by one or more protective
elements.
Multi-shot Reclosing
This relay permits up to 4 shots of reclosing. The shot number of reclosing can be set. The
first reclose cycle is, in principle, the same as the single-shot auto-reclosing. If the first
reclosing attempt is unsuccessful, this does not result in a final trip, but in a reset of the
reclaim time interval and start of the next reclose cycle with the next dead time. This can be
repeated until the shot number of reclosing has been reached.
If one of the reclosing attempts is successful, i.e. the fault disappeared after reclosing, the
reclaim time expires and the automatic reclosing system is reset. The fault is terminated.
3-51
3 Operation Theory
If none of the reclosing attempts is successful, then a final circuit breaker trip will take place
after the last allowable reclosing attempt has been performed by the protection function. All
reclosing attempts were unsuccessful.
After the final circuit breaker trip, the automatic reclosing system is dynamically blocked.
An example of a timing diagram for a successful second reclosing is shown as below.
3-52
3 Operation Theory
[79.En]
[79.En1]
[79.Ready]
[79.Blk]
[79.Inprog]
25A.Ok_SynChk
&
[79.En_SynChk]
25A.Ok_DdChk
[79.En_DdChk]
[79.OnLoad]
[79.Init]
[79.N_Rcls] = 1
[79.N_Rcls] = 2
[79.N_Rcls] = 3
[79.N_Rcls] = 4
&
&
tAR1
[79.Close_3PS1]
&
tAR2
[79.Close_3PS2]
&
tAR3
[79.Close_3PS3]
&
tAR4
[79.Close_3PS4]
Where:
tARX (x: 1~4) is the setting [79.t_3PSx] (x: 1~4), the time setting of the auto-recloser;
[79.En] is the logic setting of the auto-recloser;
[79.N_Rcls] is the shot number of the auto-recloser;
[79.Ready] denotes that the auto-recloser is ready for operation;
[79.En1] is the binary signal for enabling the auto-recloser;
[79.Blk] is the binary signal for blocking the auto-recloser;
[79.En_SynChk] is the logic setting of the synchronism check mode of the auto-recloser;
[79.En_DdChk] is the logic setting of the dead check mode of the auto-recloser;
25A.Ok_SynChk is the result of the synchronism check of the auto-recloser;
25A.Ok_DdChk is the result of the dead check of the auto-recloser;
[79.OnLoad] denotes that anyone of the phase currents is greater than 0.04In, which can be
gotten the signal Prot.OnLoad through the PCS-Explorer;
[79.Init] is the auto-recloser initiation signal which can be configured through PCS-Explorer.
The CB is closed manually (local or remote) and the CB normally closed contact (BI_52b) is
3-53
3 Operation Theory
0.
2.
Any protection element is not in startup status; i.e. the fault detector does not operate: when
the CB is closed, if the fault detector is operated, it means that the CB is closed onto an
abnormal system or a fault system.
3.
4.
The binary input of the operation circuit status of the CB (BI_LowPres_Cls) is 0; i.e. the CB
is ready for reclosing.
If the auto-recloser is ready, there is a full charged battery sign on the right bottom of LCD.
The logic diagram of the auto-recloser ready conditions is shown as below.
[BI_52b]
tCBCls 100ms
&
[FD.Pkp]
[BI_LowPres_Cls]
[79.Blk]
tCBRdy
0
0
tPWBlk
&
79.Ready
&
[79.En]
[79.En1]
Where:
[79.En] is the logic setting of the auto-recloser;
[79.En1] is the binary signal for enabling the auto-recloser;
[BI_52b] is the binary input for inputting the normally closed contact of the circuit breaker;
[FD.Pkp] means that the fault detector is operated;
[BI_LowPres_Cls] is the binary input for inputting the CB closing low pressure signal;
[79.Blk] is the binary signal for blocking the auto-recloser;
tCBCls is the setting [79.t_CBClsd] of the minimum time delay for ensuring the CB is closed;
tCBRdy is the setting [79.t_CBReady] of the time delay for ensuring the CB is ready;
tPWBlk is the setting [79.t_DDO_BlkAR] of the pulse width for ensuring the AR blocking signal.
3 Operation Theory
startup element from undesired operation, this relay takes the currents into account (the signal
[79.OnLoad]). Only when the circuit breaker has tripped completely, the auto-recloser will be put
into service.
2.
3.
The voltage difference between the protection voltage and the synchro-check voltage
(U = |UProt - USyn [25.U_Comp]|) is less than the setting [25A.U_Diff];
4.
The frequency of protection voltage and the frequency of synchro-check voltage are in
the range fn 5Hz (fn: the rated system frequency);
5.
The frequency difference between the protection voltage and the synchro-check voltage
(f = |fProt - fSyn|) is less than the setting [25A.f_Diff];
6.
The phase angle difference between the protection voltage and the synchro-check
voltage ( = |Prot (Syn + [25.phi_Comp])|) is less than the setting [25A.phi_Diff].
For the details about the settings [25.U_Comp] and [25.phi_Comp], see Section 7.4.1.
If the above conditions are satisfied at the same time for longer than [25A.t_SynChk], the
signal of the synchronism check of the auto-recloser 25A.Ok_SynChk is issued.
When the reclosing operation is executed, this relay checks the synchronism check closing
conditions in the period of the setting [25A.t_Wait]. If the synchro check closing conditions are
satisfied, this relay will issue the reclosing command.
The logic diagram of the synchronism check element for the auto-recloser is shown as below.
Where:
UProt is the protection voltage value;
USyn is the synchro-check voltage;
U is the voltage difference of the protection voltage and the synchro-check voltage;
3-55
3 Operation Theory
f is the frequency difference of the protection voltage and the synchro-check voltage;
is the angle difference of the protection voltage and the synchro-check voltage;
[25.U_Lv] is the voltage setting of the live voltage;
[25A.U_Diff] is the voltage difference setting of the synchronism check function for the
auto-recloser;
[25A.f_Diff] is the frequency difference setting of the synchronism check function for the
auto-recloser;
[25A.phi_Diff] is the phase angle difference setting of the synchronism check function for
the auto-recloser;
tARSynChk is the setting [25A.t_SynChk], the time setting of the synchronism check
function for the auto-recloser.
z
The logic diagram of the dead check element for the auto-recloser is shown as below.
Where:
UProt is the protection voltage value;
3-56
3 Operation Theory
Non-check mode
In non-check mode case, the reclosing is permitted without taking the value, phase angle and
frequency of the two voltages into account. After the reclosing delay time, this relay will issue
a reclosing signal, if all the other reclosing conditions are ready.
If the two settings [79.En_SynChk] and [79.En_DdChk] are set as 0, the non-check mode will be
in service. If one of the two settings [79.En_SynChk] and [79.En_DdChk] is set as 1, the relevant
reclosing check mode will be in service. If the two settings [79.En_SynChk] and [79.En_DdChk]
are set as 1 together, the two reclosing check modes will be in service; and if anyone of the
reclosing check modes is met, the corresponding check output is for the auto-reclosing.
2.
3.
The VT failure occurs and it is detected by the relay ([VTS.Alm_SynVT] = 1 or [VTS.Alm] = 1),
if the reclosing check mode is dead check mode.
4.
The blocking signal of the auto-recloser 79.Blk is 1; that is at least one of the blocking
auto-recloser conditions is met. The blocking auto-recloser conditions can be configured for
blocking the auto-recloser through the PCS-Explorer configuration tool auxiliary software.
5.
The binary input of the closing operation circuit status of the CB (BI_LowPres_Cls) is 1; i.e.
the CB is not ready for reclosing ([BI_LowPres_Cls] = 1).
6.
If the auto-recloser is blocked, there is an empty battery sign on the right bottom of LCD.
3-57
3 Operation Theory
No.
Menu text
79.t_CBClsd
79.t_DDO_BlkAR
79.t_CBReady
79.t_Fail
79.t_3PS1
6
7
79.t_3PS2
79.t_3PS3
Explanation
The time setting of the minimum time delay for
ensuring the CB is closed
The time pulse width for ensuring the AR blocking
signal
The time setting of the time delay for ensuring the
CB is ready
The time setting of the time delay for checking the
CB position
The time setting of the 1st shot auto-recloser
nd
Range
Step
0.01~600s
0.001s
0.01~600s
0.001s
0.01~600s
0.001s
0.01~600s
0.001s
0~600s
0.001s
shot auto-recloser
0~600s
0.001s
rd
0~600s
0.001s
th
79.t_3PS4
0~600s
0.001s
79.t_Reclaim
0~600s
0.001s
10
79.t_DDO_AR
0-4.00s
0.001s
11
79.N_Rcls
1~4
12
79.En_SynChk
0~1
13
79.En_DdChk
0~1
14
79.En_FailChk
0~1
15
79.En
0~1
16
79.OutMap
0x00000000 ~
0x7FFFFFFF
The settings about the check function of the auto-recloser are listed in the following table. For the
information about the common explanation of the settings, see Section 7.4.
No.
Menu text
Explanation
Range
Step
25.U_Dd
2~120V
0.001V
25.U_Lv
2~120V
0.001V
25.U_Comp
0.2~5.0
0.001
25.phi_Comp
0~360
25.Opt_Usyn
0~5
25.t_ClsCB
0.02~1.00s
0.001s
25A.U_Diff
2~120V
0.001V
25A.f_Diff
0~2Hz
0.001Hz
frequency
difference
setting
3-58
of
the
3 Operation Theory
9
25A.phi_Diff
10
25A.t_Wait
11
25A.Opt_DdChk
12
25A.t_DdChk
13
25A.t_SynChk
0~60
0.01~60s
0.001s
1~7
0.01~25s
0.001s
0.01~25s
0.001s
Where:
ManCls_Cmd is the manual closing command;
25M.Ok_SynChk is the result of the synchronism check of the manual closing function;
25M.Ok_DdChk is the result of the dead check of the manual closing function;
25M.BI_EnSynChk is the binary input for enabling the synchronism check mode, and it can
be configured through the PCS-Explorer configuration tool auxiliary software;
25M.BI_EnDdChk is the binary input for enabling the dead check mode, and it can be
configured through the PCS-Explorer configuration tool auxiliary software;
[25M.En_SynChk] is the logic setting of the synchronism check of the manual closing;
[25M.En_DdChk] is the logic setting of the dead check of the manual closing.
3-59
3 Operation Theory
2.
3.
The voltage difference between the protection voltage and the synchro-check voltage
(U = |UProt - USyn [25.U_Comp]|) is less than the setting [25M.U_Diff];
4.
The frequency of protection voltage and the frequency of synchro-check voltage are in
the range fn 5Hz (fn: the rated system frequency);
5.
The frequency difference between the protection voltage and the synchro-check voltage
(f = |fProt - fSyn|) is less than the setting [25M.f_Diff];
6.
The rate-of-change of the frequency difference (df/dt) is less than the setting [25M.df/dt]
to decrease the disturbance to the power system when the CB is closed;
7.
The phase angle difference between the protection voltage and the synchro-check
voltage ( = |Prot (Syn + [25.phi_Comp])|) is less than the setting [25M.phi_Diff].
For the details about the settings [25.U_Comp] and [25.phi_Comp], see Section 7.4.1.
If the above conditions are satisfied at the same time, the signal of the synchronism check of
the manual closing 25M.Ok_SynChk is issued.
When the manual closing operation is executed, this relay checks synchronism check closing
conditions in the period of the setting [25M.t_Wait]. If the synchro check closing conditions are
satisfied, this relay will issue the closing command.
The logic diagram of the manual closing synchronism check element is shown as below.
Figure 3.18-2 Logic diagram of the synchronism check element for manual closing
Where:
UProt is the protection voltage value;
USyn is the synchro-check voltage value;
3-60
3 Operation Theory
U is the voltage difference of the protection voltage and the synchro-check voltage;
f is the frequency difference of the protection voltage and the synchro-check voltage;
df/dt is the rate-of-change of the frequency difference;
is the angle difference of the protection voltage and the synchro-check voltage;
[25.U_Lv] is the voltage setting of the live voltage;
[25M.U_Diff] is the voltage difference setting of the synchronism check function for the
manual closing;
[25M.f_Diff] is the frequency difference setting of the synchronism check function for the
manual closing;
[25M.df/dt] is the frequency rate-of-change setting of the synchro check closing function
for the manual closing;
[25M.phi_Diff] is the phase angle difference setting of the synchronism check function for
the manual closing.
z
The logic diagram of the manual closing dead check element is shown as below.
Figure 3.18-3 Logic diagram of the dead check element for manual closing
Where:
3-61
3 Operation Theory
Non-check mode
In non-check mode case, the manual closing is permitted without taking the value, phase
angle and frequency of the two voltages into account. If all the other manual closing
conditions are ready, this relay will issue a manual closing signal.
If the two settings [25M.En_SynChk] and [25M.En_DdChk] are set as 0, and the two binary
inputs 25M.BI_EnSynChk and 25M.BI_EnDdChk are not energized, the non-check mode will
be in service. If the setting [25M.En_SynChk] is set as 1 or the binary input 25M.BI_EnSynChk
is energized, the synchronism check mode will be in service; and if the setting [25M.En_DdChk] is
set as 1 or the binary input 25M.BI_EnDdChk is energized, the dead check mode will be in
service. If the synchronism check mode and the dead check mode are in service at the same time;
and if anyone of the manual closing check modes is met, the corresponding check output is for the
manual closing.
Menu text
Explanation
Range
Step
25.U_Dd
2~120V
0.001V
25.U_Lv
2~120V
0.001V
25.U_Comp
0.2~5.0
0.001
25.phi_Comp
0~360
25.Opt_Usyn
0~5
25.t_ClsCB
0.02~1.00s
0.001s
25M.U_Diff
2~120V
0.001V
25M.f_Diff
0~2Hz
0.001Hz
25M.df/dt
10
25M.phi_Diff
3-62
0~3Hz/s
0~60
0.001
Hz/s
1
3 Operation Theory
The waiting time setting of the manual closing
11
25M.t_Wait
12
25M.Opt_DdChk
13
25M.En_SynChk
14
25M.En_DdChk
0.01~30s
0.001s
1~7
0~1
0~1
Where:
[MR1.Input] is the mechanical protection input signal which can be from a binary input;
tMR1 is the setting [MR1.t_Op], the time setting of the No.1 mechanical protection;
[MR1.En] is the logic setting of the No.1 mechanical protection;
[MR1.En1] is the binary signal for enabling the No.1 mechanical protection;
[MR1.Blk] is the binary signal for blocking the No.1 mechanical protection.
Menu text
MR1.t_Op
MR1.En
Explanation
The
time
setting
of
the
Range
No.1
mechanical
protection
The logic setting of the No.1 mechanical
protection
Step
0~4000s
0.001s
0~1
3-63
3 Operation Theory
3
MR1.OutMap
MR2.t_Op
MR2.En
MR2.OutMap
MR3.t_Op
MR3.En
MR3.OutMap
10
MR4.t_Op
11
MR4.En
12
MR4.OutMap
0x00000000 ~
protection
0x7FFFFFFF
The
time
setting
of
the
No.2
mechanical
protection
The logic setting of the No.2 mechanical
protection
0~4000s
0.001s
0~1
0x00000000 ~
protection
0x7FFFFFFF
The
time
setting
of
the
No.3
mechanical
protection
The logic setting of the No.3 mechanical
protection
0.001s
0~1
0x00000000 ~
protection
0x7FFFFFFF
time
setting
of
the
No.4
mechanical
protection
The logic setting of the No.4 mechanical
protection
0~4000s
0~4000s
0.001s
0~1
0x00000000 ~
protection
0x7FFFFFFF
Where:
3-64
3 Operation Theory
Menu text
Explanation
Range
Step
50DZ.I_Set
0.1In~5.0In
0.001A
50DZ.t_Op
0~100s
0.001s
50DZ.En
0~1
50DZ.OutMap
0x00000000 ~
protection
0x7FFFFFFF
Where:
[37.I_Set] is the current setting of the undercurrent protection;
[BI_52b] is the binary input from the auxiliary normally closed contact of the circuit breaker;
tUC is the setting [37.t_Op], the time setting of the undercurrent protection;
3-65
3 Operation Theory
Menu text
Explanation
Range
Step
37.I_Set
0.1In~1.0In
0.001A
37.t_Op
0~100s
0.001s
37.En
0~1
37.OutMap
0x00000000 ~
protection
0x7FFFFFFF
3-66
4 Supervision
4 Supervision
Table of Contents
4.1 Overview ...........................................................................................................4-1
4.2 Supervision Functions.....................................................................................4-1
4.2.1 Device Hardware Supervision............................................................................................ 4-1
4.2.2 Board Configuration Error Supervision .............................................................................. 4-1
4.2.3 Setting Supervision ............................................................................................................ 4-1
4.2.4 Program Version Supervision ............................................................................................ 4-2
4.2.5 Tripped Position Contact Supervision ................................................................................ 4-2
4.2.6 Low Pressure Binary Input Supervision ............................................................................. 4-2
4.2.7 VT Circuit Supervision ....................................................................................................... 4-2
4.2.8 CT Circuit Supervision ....................................................................................................... 4-4
4.2.9 Thermal Overload Supervision .......................................................................................... 4-5
4.2.10 Time Synchronization Supervision................................................................................... 4-5
4.2.11 Auxiliary Communication Testing Supervision .................................................................. 4-5
4.2.12 Device Maintenance Supervision..................................................................................... 4-5
4.2.13 Reserved Programmable Alarm Supervision ................................................................... 4-5
4.2.14 Tripping Circuit Supervision ............................................................................................. 4-5
4.2.15 A/D Sampling Supervision ............................................................................................... 4-6
List of Figures
Figure 4.2-1 Logic diagram of the 52b contact supervision element ................................... 4-2
Figure 4.2-2 Logic diagram of the protection VTS element................................................... 4-3
Figure 4.2-3 Logic diagram of the synchro-check VTS element........................................... 4-4
Figure 4.2-4 Logic diagram of the CTS element..................................................................... 4-4
Figure 4.2-5 Principle of the TCS function with two binary inputs ....................................... 4-6
4-a
4 Supervision
4-b
4 Supervision
4.1 Overview
Though the protection system is in non-operating state under normal conditions, it is waiting for a
power system fault to occur at any time and must operate for the fault without fail.
When the equipment is in energizing process before the LED HEALTHY is on, the equipment
needs to be checked to ensure there are no errors. Therefore, the automatic supervision function,
which checks the health of the protection system during startup and normal operation procedure,
plays an important role.
The numerical relay based on the microprocessor operations has the capability for implementing
this automatic supervision function of the protection system.
In case a fatal fault is detected during automatic supervision, the equipment will be blocked out. It
means that this relay is out of service. Therefore you must re-energize the relay or even replace a
module to make this relay back into service.
4-1
4 Supervision
the current settings of the main CPU module, the alarm signal [Alm_Setting_MON] will be issued.
The LED indicator ALARM will be on at the same time.
Prot.OnLoad
Ib > 0.04In
Ic > 0.04In
Prot.OnLoad
&
10s
[Alm_52b]
[BI_52b]
Protection VT supervision
If this relay detects any one of the following two conditions is satisfied, it means that the
4-2
4 Supervision
Where:
Prot.OnLoad is the signal for denoting the system is on load state;
[VTS.En] is the logic setting of the protection VTS function;
[VTS.I_Set] is the phase current setting of the protection VTS function;
[VTS.I2_Set] is the negative sequence current setting of the protection VTS function;
[Sig_MCB_VTS] is the VT supervision input from VTs miniature circuit breaker (MCB)
auxiliary contact which shows the MCB whether is opened.
U1 is the positive sequence voltage;
U2 is the negative sequence voltage.
z
Synchro-check VT supervision
This function is used to supervise the synchro-check voltage transformer circuit. When the
setting [VTS.En_SynVT] is set as 1, if the difference between the measured synchro-check
4-3
4 Supervision
voltage (Ux) and the setting [Syn.U2n] is greater than 15V for longer than 10s, the alarm
signals [Alm_Device] and [VTS.Alm_SynVT] will be issued, and the LED ALARM will be on
at the same time. When the status of the synchro-check VT returns to normal condition, the
alarm will restore automatically 1.25s later.
[79.En_SynChk]
[79.En_DdChk]
|Ux [Syn.U2n]| > 15V
&
10s
[VTS.Alm_SynVT]
[VTS.En_SynVT]
Where:
[VTS.En_SynVT] is the logic setting of the synchro-check VTS function;
[79.En_SynChk] is the logic setting of the synchronism check mode of the auto-recloser;
[79.En_DdChk] is the logic setting of the dead check mode of the auto-recloser.
The calculated zero sequence current is greater than the setting [CTS.3I0_Set];
2.
The calculated zero sequence voltage is less than the setting [CTS.3U0_Set].
If a CT circuit failure is detected, the alarm signals [Alm_Device] and [CTS.Alm] will be issued, and
the LED indicator ALARM will be on at the same time.
If the fast CT circuit failure is detected, the internal signal [CTS.InstAlm] will be 1 without any time
delay.
The logic diagram of the CTS element is shown as below.
Where:
[CTS.3I0_Set] is the threshold current setting of the CTS element;
[CTS.3U0_Set] is the threshold voltage setting of the CTS element;
4-4
4 Supervision
4-5
4 Supervision
Figure 4.2-5 Principle of the TCS function with two binary inputs
Where:
BTJ is the protection tripping output contact;
TC is the tripping coil of the circuit breaker;
[B07.BI_01] is the binary input which is parallel connected with BTJ;
[B07.BI_02] is the binary input which is serial connected with the 52b contact.
4-6
5 Management Function
5 Management Function
Table of Contents
5.1 Overview ...........................................................................................................5-1
5.2 Measurement ....................................................................................................5-1
5.2.1 Protection Sampling........................................................................................................... 5-1
5.2.2 Metering............................................................................................................................. 5-1
List of Figures
Figure 5.3-1 Demonstration diagram of the control function................................................ 5-2
5-a
5 Management Function
5-b
5 Management Function
5.1 Overview
The relay provides some management functions, such as protection sampling, metering, remote
control, signaling, event recording and fault & disturbance recording etc. All these functions can
ensure this relay meets the requirements of a modern power grid.
5.2 Measurement
This relay produces a variety of both directly and calculated power system quantities. Two kinds of
measurements are supported in this relay: protection sampling and metering. All these
measurands also can be transmitted to the SAS or RTU through communication. See Chapter 10
for more information about the communication and protocols.
5.2.2 Metering
This relay samples the metering values with 48-point sampling rate per cycle. These metering
values are being undated per 0.5s and can be viewed in the submenu Measurement2 of this
relay or via relay communication. See Section 8.2.3 for more details about the metering values.
5 Management Function
5.4 Signaling
This relay has some programmable binary inputs which are used to monitor the contact positions
of the corresponding bay, or be used in protection logics or for releasing or blocking the relevant
protective element, or be used in supervision logics calculation for supervision alarm elements.
The binary inputs can be configured according to the engineering demands through the
PCS-Explorer configuration tool auxiliary software.
The binary input state change confirmation time of each binary input is configurable according to
practical application through the PCS-Explorer configuration tool auxiliary software, and the
default binary input state change confirmation time of the binary inputs is 10ms.
See Section 8.2.4 for more details about the binary inputs.
5-2
5 Management Function
Each waveform includes the wave recording data both before and after the fault. Each trigger
element operation will extend the wave recording time, until the appointed time delay is over after
the trigger element restores, or until the maximum number of wave recording points is reached.
5-3
5 Management Function
5-4
6 Hardware
6 Hardware
Table of Contents
6.1 Overview ...........................................................................................................6-1
6.2 Basic Enclosure ...............................................................................................6-3
6.3 Human Machine Interface Module (NR4856) ..................................................6-4
6.4 Power Supply Module (NR4304/NR4305)........................................................6-4
6.5 Main CPU Module (NR4106).............................................................................6-6
6.6 Analog Input Module (NR4412)........................................................................6-8
6.6.1 Connection Examples ...................................................................................................... 6-10
6.6.2 Current Transformer Requirements ..................................................................................6-11
List of Figures
Figure 6.1-1 Hardware structure of the this relay .................................................................. 6-1
Figure 6.1-2 Front panel of the this relay without control buttons ....................................... 6-2
Figure 6.1-3 Front panel of the this relay with control buttons............................................. 6-2
Figure 6.1-4 Rear panel of the this relay ................................................................................. 6-3
Figure 6.2-1 Rack, back plane and slot allocation of this relay ............................................ 6-4
Figure 6.4-1 View of the power supply module ...................................................................... 6-5
Figure 6.5-1 View of the main CPU module ............................................................................ 6-7
Figure 6.6-1 View of the analog input module........................................................................ 6-8
Figure 6.6-2 Current connection examples .......................................................................... 6-10
Figure 6.6-3 Voltage connection examples............................................................................6-11
Figure 6.7-1 View of the binary output module .................................................................... 6-13
Figure 6.8-1 View of the binary input module....................................................................... 6-16
6-a
6 Hardware
6-b
6 Hardware
6.1 Overview
The modular design of this relay allows the relay to be easily upgraded or repaired by a qualified
service person. The faceplate is hinged to allow easy access to the configurable modules, and
back-plugging structure design makes it easy to repair or replace any module.
There are several types of hardware modules in this relay; each module takes a different part in
this relay. The relevant modules can be selected according to the practical engineering demands.
These modules which are supported in this relay and their module codes are listed as below.
No.
Module Description
Module Code
Configuration
NR4856
Mandatory
NR4304/NR4305
Mandatory
NR4106
Mandatory
NR4412
Optional
NR4521
Optional
NR4502/NR4503/ NR4504
Optional
NR4138/NR4126
Optional
NR4202
Optional
These modules can be freely equipped in the basic enclosure of this relay (see Section 6.2), and
the relationship between the module and the slot number is listed as below.
Module Description
Slot Number
Any slot if the slot is not occupied, default is the No.6 slot.
Any slot if the slot is not occupied, default is the No.7 slot.
6-1
6 Hardware
ESC
GR
P
The following figures show the front panel and the rear panel of this device.
ESC
GR
P
Figure 6.1-2 Front panel of the this relay without control buttons
Figure 6.1-3 Front panel of the this relay with control buttons
6-2
6 Hardware
NOTE! The hardware module configuration in above figure is only a demonstration for
explaining how the hardware module is configured. The hardware module configuration
can be different according to the different engineering demands, and the hardware
module configuration of a practical engineering should be taken as final and binding.
NOTE! The No.8 slot is reserved for some special demands, if the present hardware
configuration can not meet the special demands.
6-3
NR4304/NR4305
NR4202
NR4503/4502/4504
NR4521
NR4412
NR4138/NR4126
Slot:
NR4106
6 Hardware
Figure 6.2-1 Rack, back plane and slot allocation of this relay
6-4
6 Hardware
NR4304
NR4305
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20 PWR+
21 PWR22 GND
NR4304A
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20 PWR+
21 PWR22 GND
NR4305A
A 22-pin connector is fixed on the front side of this module. The terminal definition of the connector
is described as below.
Pin connections on the 22-pin connector of the power supply modules NR4304A and NR4305A:
Pin No.
Sign
Description
01
SIG_COM
02
BO_Fail_Device
03
BO_Alm_Device
04
05
06
07
08
BO_01
BO_02
BO_03
BO_04
BO_05
BO_06
BO_07
BO_08
20
PSW+
21
PSW-
22
GND
Grounded terminal
09
10
11
12
13
14
15
16
17
18
19
6-5
6 Hardware
Protection calculations
The main CPU module can calculate protective elements (such as overcurrent element, zero
sequence overcurrent etc.) on the basis of the analog sampled values (voltages and currents)
and binary inputs, and then decides whether the device needs to trip or close.
Communication management
The main CPU module can effectively manage all communication procedures, and reliably
send out some useful information through its various communication interfaces. These
interfaces are used to communicate with a SAS or a RTU. It also can communicate with the
human machine interface module. If an event occurs (such as SOE, protective tripping event
etc.), this module will send out the relevant event information through these interfaces, and
make it be easily observed by the user.
Auxiliary calculations
Based on the voltage and current inputs, the main CPU module also can calculate out the
metering values, such as active power, reactive power and power factor etc. All these values
can be sent to a SAS or a RTU through the communication interfaces.
Time Synchronization
This module has a local clock chip and an interface to receive time synchronized signals from
external clock source. These signals include PPS (pulse per second) signal and IRIG-B signal.
Basing on the timing message (from SAS or RTU) and the PPS signal, or basing on the
IRIG-B signal, this module can synchronize local clock with the standard clock.
There are three types of main CPU modules, and the view of the main CPU module is shown in
Figure 6.5-1.
6-6
6 Hardware
NR4106
NR4106
NR4106
TX
RX
TX
RX
NR4106AA
NR4106AB
NR4106AC
A 16-pin or 7-pin connector is fixed on the front side of the module. The terminal definition of the
connector is described as below.
Pin connections on the connector of the main CPU module NR4106AA and NR4106AC:
Pin No.
Sign
01
Description
Not used
02
03
04
SGND
The No.1 EIA RS-485 standardized interface for connecting with a SAS or a
05
RTU.
Not used.
06
07
08
SGND
The No.2 EIA RS-485 standardized interface for connecting with a SAS or a
09
RTU.
Not used.
10
SYN+
11
SYN-
12
SGND
13
The EIA RS-485 standardized interface for time synchronization, PPS and
IRIG-B signals are permitted.
Not used.
14
RTS
15
TXD
16
SGND
The interface for connecting with a printer, the EPSON LQ-300K printer is
recommended.
Sign
01
SYN+
02
SYN-
03
SGND
04
Description
The EIA RS-485 standardized interface for time synchronization, PPS and
IRIG-B signals are permitted.
Not used.
6-7
6 Hardware
05
RTS
06
TXD
07
SGND
The interface for connecting with a printer, the EPSON LQ-300K printer is
recommended.
NR4412
NR4412
01
02
01
02
03
04
03
04
05
06
05
06
07
08
07
08
09
10
09
10
11
12
11
12
13
14
13
14
15
16
15
16
17
18
17
18
19
20
19
20
21
22
21
22
23
24
23
24
25
26
26-pin
24-pin
6-8
6 Hardware
A 26-pin or 24-pin connector is fixed on the front side of this module. The terminal definition of the
connector is described as below.
Pin connections on the connector of the analog input module NR4412 with 26 pins:
Pin No.
Sign
Description
01
Ua
02
Ub
The three voltage inputs with inner star connection (Y) for protection and
03
Uc
metering.
04
Un
05
Ux
06
Uxn
07
U0
08
U0n
09
I02
10
I02n
11
Ia
12
Ian
13
Ib
14
Ibn
15
Ic
16
Icn
17
I01
18
I01n
19
I0s
20
I0sn
21
Iam
22
Iamn
23
Ibm
24
Ibmn
25
Icm
26
Icmn
Pin connections on the connector of the analog input module NR4412 with 24 pins:
Pin No.
Sign
Description
01
Ua
02
Ub
The three voltage inputs with inner star connection (Y) for protection and
03
Uc
metering.
04
Un
05
Ux
06
Uxn
07
U0
08
U0n
6-9
6 Hardware
09
I02
10
I02n
11
Ia
12
Ian
13
Ib
14
Ibn
15
Ic
16
Icn
17
I01
18
I01n
19
I0s
20
I0sn
21
Not used
22
Not used
23
Not used
24
Not used
6-10
6 Hardware
Where:
(1) Current connections to three current transformers with a star-point connection for ground
current (zero sequence current or residual current).
(2) Current connections to three current transformers with a separate ground current
transformer (summation current transformer or core balance current transformer).
(3) Current connections to two current transformers with a separate ground current
transformer (summation current transformer or core balance current transformer), only
for ungrounded or compensated networks.
(4) Current connection to a core balance neutral current transformer for sensitive ground
fault detection, only for ungrounded or compensated networks.
(5) Current connection to a separate ground current transformer (summation current
transformer or core balance current transformer) for the No.2 zero sequence current
input of this relay.
2.
52
52
52
52
52
52
05
Ux
06
Uxn
Ua
01
Ua
Ub
02
Ub
03
Uc
03
Uc
04
Un
04
Un
07
U0
07
U0
08
U0n
08
U0n
05
Ux
06
Uxn
01
02
(1)
(2)
Where:
(1) Voltage connections to three star-connected voltage transformers with open-delta
windings and additionally to any phase voltage (for synchronism check).
(2) Voltage connections to three star-connected voltage transformers with open-delta
windings and additionally to any phase-to-phase voltage (for synchronism check).
CT Requirements
--
6-11
6 Hardware
--
Rated short-time thermal current Ith and rated dynamic current Idyn:
According to the maximum fault current
--
--
Ipn
Icth
Ith
Idyn
Isn
Kalf
Ipal
Performance Verification
Esl > Esl
Esl
Esl
Kalf
Stability factor: k = 2
Ipal
Ipcf
Ipn
Isn
Rct
Rbn
Sbn
Rb
Rc
RL
Rr
Example
Kalf = 30.00,
Isn = 5A,
Rct = 1.00,
Sbn = 60VA
6-12
6 Hardware
Esl = kalf Isn (Rct + Rbn) = kalf Isn (Rct + Sbn / Isn2)
So, Esl = 30 5 (1 + 60 / 52) = 510V
Ipcf = 40000A,
RL = 0.50,
Rr = 0.10,
Rc = 0.10,
Ipn = 2000A
Esl = k Ipcf Isn (Rct + Rb) / Ipn = k Ipcf Isn (Rct + (Rr + 2RL + Rc)) / Ipn
So, Esl = 2 40000 5 (1 + (0.1 + 2 0.5 + 0.1)) / 2000 = 440V
It can meet the requirement: Esl > Esl.
A 22-pin connector is fixed on the front side of this module. The terminal definition of the connector
is described as below.
Pin connections on the 22-pin connector of the binary output module NR4521A:
Pin No.
01
02
03
04
Sign
Description
BO_01
BO_02
6-13
6 Hardware
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
BO_03
BO_04
BO_05
BO_06
BO_07
BO_08
BO_09
BO_10
BO_11
Pin connections on the 22-pin connector of the binary output module NR4521C:
Pin No.
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
Sign
Description
BO_01
BO_02
BO_03
BO_04
BO_05
BO_06
BO_07
BO_08
BO_09
BO_10
BO_11
6-14
6 Hardware
Pin connections on the 22-pin connector of the binary output module NR4521D:
Pin No.
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
Sign
Description
BO_01
BO_02
BO_03
BO_04
BO_05
BO_06
BO_07
BO_08
BO_09
BO_10
BO_11
6-15
6 Hardware
A 22-pin connector is fixed on the front side of this module. The terminal definition of the connector
is described as below.
Pin connections on the 22-pin connector of the binary input module NR4502:
Pin No.
Sign
01
BI_01+
02
BI_01-
03
BI_02+
04
BI_02-
05
BI_03+
06
BI_03-
07
BI_04+
08
BI_04-
09
BI_05+
10
BI_05-
11
BI_06+
12
BI_06-
13
BI_07+
14
BI_07-
15
BI_08+
16
BI_08-
17
BI_09+
18
BI_09-
19
BI_10+
20
BI_10-
21
BI_11+
22
BI_11-
Description
The No.1 programmable binary input
The No.2 programmable binary input
The No.3 programmable binary input
The No.4 programmable binary input
The No.5 programmable binary input
The No.6 programmable binary input
The No.7 programmable binary input
The No.8 programmable binary input
The No.9 programmable binary input
The No.10 programmable binary input
The No.11 programmable binary input
Pin connections on the 22-pin connector of the binary input module NR4503:
6-16
6 Hardware
Pin No.
Sign
Description
01
BI_01+
02
BI_01-
03
BI_02+
04
BI_02-
05
BI_03
06
BI_04
07
BI_05
08
BI_06
09
BI_07
10
BI_08
11
BI_09
12
BI_10
13
BI_11
14
BI_12
15
BI_13
16
BI_14
17
BI_15
18
BI_16
19
BI_17
20
BI_18
21
BI_19
22
BI_Opto-
Pin connections on the 22-pin connector of the binary input module NR4504:
Pin No.
Sign
Description
01
BI_01
02
BI_02
03
BI_Opto1-
04
BI_03
05
BI_04
06
BI_Opto2-
07
BI_05
08
BI_06
09
BI_Opto3-
10
BI_07
11
BI_08
12
BI_Opto4-
13
BI_09
14
BI_10
15
BI_Opto5-
16
BI_11
17
BI_12
6-17
6 Hardware
18
BI_Opto6-
19
BI_13
20
BI_14
21
BI_Opto7-
22
Not used
6-18
6 Hardware
6-19
6 Hardware
6-20
7 Settings
7 Settings
Table of Contents
7.1 Overview ...........................................................................................................7-1
7.2 System Settings ...............................................................................................7-1
7.3 Protection Settings ..........................................................................................7-2
7.3.1 Overcurrent Protection Settings......................................................................................... 7-3
7.3.2 Zero Sequence Overcurrent Protection Settings ............................................................... 7-6
7.3.3 Negative Sequence Overcurrent Protection Settings......................................................... 7-9
7.3.4 Sensitive Earth Fault Protection Settings......................................................................... 7-10
7.3.5 Breaker Failure Protection Settings ................................................................................. 7-12
7.3.6 Broken Conductor Protection Settings ............................................................................. 7-13
7.3.7 Cold Load Pickup Settings............................................................................................... 7-13
7.3.8 SOTF Protection Settings ................................................................................................ 7-14
7.3.9 Thermal Overload Protection Settings ............................................................................. 7-15
7.3.10 Overvoltage and Undervoltage Protection Settings ....................................................... 7-16
7.3.11 Negative Sequence Overvoltage Protection Settings..................................................... 7-17
7.3.12 Zero Sequence Overvoltage Protection Settings ........................................................... 7-17
7.3.13 Frequency Protection Settings....................................................................................... 7-18
7.3.14 Auto-recloser Settings.................................................................................................... 7-20
7.3.15 Mechanical Protection Settings...................................................................................... 7-21
7.3.16 Dead Zone Protection Settings ...................................................................................... 7-22
7.3.17 Undercurrent Protection Settings................................................................................... 7-22
7.3.18 Supervision Element Settings ........................................................................................ 7-23
7.3.19 Binary Output Matrix Settings ........................................................................................ 7-23
7 Settings
7-b
7 Settings
7.1 Overview
The settings are used to determine the characteristic of each protective element and operation
mode of the relay. It is necessary to configure the settings of this relay according to engineering
demands before putting this relay into service. If the settings are not configured correctly, this relay
maybe works abnormally (such as communication interruption, printing out unexpected codes
etc.), it also can lead to much more serious accident (such as unwanted operation, missing
operation) sometimes.
The settings of this relay include system settings, protection settings, communication settings and
miscellaneous settings. The user can configure these settings or parameters manually (see
Section 8.2.6.2). Remote modification is also supported (IEC61850, IEC60870-5-103 or DNP3.0
interface, see Chapter 10 for the details about these protocols).
NOTE! If a CPU module is replaced, it is necessary to configure all the settings again
according to the configuration of the CPU module which is replaced.
Menu text
Explanation
Range
Step
Active_Grp
1 ~ 10
Opt_SysFreq
0~1
PrimaryEquip_Name
1~7 characters
Prot.I1n
0~20000A
1A
Prot.I2n
1/5A
4A
Measmt.I1n
0~20000A
1A
Measmt.I2n
1/5A
4A
Neu1.I1n
0~20000A
1A
Neu1.I2n
1/5A
4A
10
Neu2.I1n
0~20000A
1A
11
Neu2.I2n
1/5A
4A
12
SEF.I1n
0~20000A
1A
13
SEF.I2n
1/5A
4A
14
Prot.U1n
0.1~500.0kV
0.001kV
15
Prot.U2n
100~200V
0.001V
16
Syn.U1n
0.1~500.0kV
0.001kV
17
Syn.U2n
10~200V
0.001V
18
Delt.U1n
0.1~500.0kV
0.001kV
7-1
7 Settings
19
Delt.U2n
20
Opt_3I0
21
Opt_3U0
22
Opt_PwrDir
10~200V
0.001V
0~1
0~1
0~3
NOTE!
1.
The system settings are related to the protection activities, thus it is necessary to configure
theses settings according to actual conditions.
2.
The setting [Opt_3I0] is used to select the No.1 zero sequence current source. Setting the
value of [Opt_3I0] as 1 means that the No.1 zero sequence current is self-calculated, and
setting the value as 0 means that the No.1 zero sequence current is derived from specific
zero sequence CT. The default value is 0 when the equipment is delivered.
3.
The setting [Opt_3U0] is used to select the zero sequence voltage source. Setting the value
of [Opt_3U0] as 1 means that zero sequence voltage is self-calculated, and setting the value
as 0 means that zero sequence voltage is derived from specific broken delta VT.
4.
Active Power
To line
To busbar
To line
To busbar
+W
-W
+Var
-Var
-W
+W
+Var
-Var
+W
-W
-Var
+Var
-W
+W
-Var
+Var
Before configuring the settings, the setting group must be configured firstly.
2.
3.
In general, for switch onto fault protection and accelerated protection, it is necessary to set a
time delay from decades to 100ms. Thanks to there is no 100ms time delay in the numerical
7-2
7 Settings
protection equipment as there in the traditional protection equipment in the past, thus it can
not avoid surge current when CB is closing if the time is set as 0.00s. For residual overcurrent
when switch onto fault and residual accelerate protection, there is zero sequence surge
current when CB is closing.
4.
To a certain protection element, only when the logic setting and the state of enabling input
signal are 1, and the state of the blocking input signal is 0 at the same time, then the
corresponding protection element is enabled, otherwise it is disabled.
5.
The setting [XXXX.OutMap] is used to select the binary outputs of the module NR4304 and
the module NR4521 to send the related protection tripping or closing signal to the circuit
breaker. Each bit can control one output, and if it is set as 1, the related protection tripping or
closing signal can be sent to the circuit breaker through the selected binary output.
Bit No.
10
11
12
13
14
15
16
17
18
19
Some of the protective elements have a setting (just like [XXXX.OutMap], XXXX is the
abbreviation of a protective element, such as 50/51P1, 50/51G1, 59P1 etc.) to configure the
outputs, and they have the same meanings described here. Please refer the content here for
the output matrix setting of each protective element.
7 Settings
No.
Menu text
50/51P.U2_VCE
50/51P.Upp_VCE
50/51P.RCA
Explanation
The voltage setting of the negative sequence
voltage blocking element (phase voltage)
The voltage setting of the low voltage blocking
element (phase-to-phase voltage)
The relay characteristic angle for the directional
overcurrent protection
Range
Step
2~70V
0.001V
2~120V
0.001V
-180~179
0~1
0.05~1.00
0.001
0.05In~30In
0.001A
1~3
0.05In~30In
0.001A
0~100s
0.001s
0~1
0~2
0~1
0~1
50/51P.En_VTS_Blk
50/51P.K_Hm2
50/51P.I_Rls_HmBlk
50/51P.Opt_Hm_Blk
50/51P1.I_Set
50/51P1.t_Op
10
50/51P1.En_VCE
11
50/51P1.Opt_Dir
12
50/51P1.En_Hm_Blk
13
50/51P1.En
14
50/51P1.OutMap
15
50/51P2.I_Set
16
50/51P2.t_Op
17
50/51P2.En_VCE
0x00000000 ~
overcurrent protection
0x7FFFFFFF
0.05In~30In
0.001A
0~100s
0.001s
0~1
0~2
0~1
0~1
50/51P2.Opt_Dir
19
50/51P2.En_Hm_Blk
20
50/51P2.En
7-4
7 Settings
21
50/51P2.OutMap
22
50/51P3.I_Set
23
50/51P3.t_Op
24
50/51P3.En_VCE
0x00000000 ~
overcurrent protection
0x7FFFFFFF
0.05In~30In
0.001A
0~100s
0.001s
0~1
0~2
0~1
0~1
50/51P3.Opt_Dir
26
50/51P3.En_Hm_Blk
27
50/51P3.En
28
50/51P3.OutMap
29
50/51P4.I_Set
30
50/51P4.t_Op
31
50/51P4.En_VCE
0x00000000 ~
overcurrent protection
0x7FFFFFFF
0.05In~30In
0.001A
0~100s
0.001s
0~1
0~2
0~1
0~1
50/51P4.Opt_Dir
33
50/51P4.En_Hm_Blk
34
50/51P4.En
35
50/51P4.OutMap
36
50/51P4.Opt_Curve
37
50/51P4.TMS
38
50/51P4.tmin
39
50/51P4.K
40
50/51P4.C
41
50/51P4.Alpha
0x00000000 ~
overcurrent protection
0x7FFFFFFF
0~13
0.05~100.0
0.001
0~100s
0.001s
0.001~120.0
0.0001
0.00~1.00
0.0001
0.01~3.00
0.0001
7-5
7 Settings
NOTE!
1.
The setting [50/51Px.Opt_Dir] (x: 1~4) is used to select the directional mode for the stage x (x:
1~4) overcurrent protection respectively. 0 is the non-directional mode; 1 is the forward
directional mode; and 2 is the reverse directional mode.
Menu text
50/51G.RCA
50/51G.En_VTS_Blk
Explanation
The relay characteristic angle for the No.1
directional zero sequence overcurrent protection
Range
Step
-180~179
0~1
0.05~1.00
0.001
0.05In~30In
0.001A
0.05In~30In
0.001A
0~100s
0.001s
0~2
0~1
0~1
50/51G.K_Hm2
50/51G.3I0_Rls_HmBlk
50/51G1.3I0_Set
50/51G1.t_Op
50/51G1.Opt_Dir
50/51G1.En_Hm_Blk
50/51G1.En
10
50/51G1.OutMap
11
50/51G2.3I0_Set
12
50/51G2.t_Op
13
50/51G2.Opt_Dir
14
50/51G2.En_Hm_Blk
0x00000000 ~
0x7FFFFFFF
7-6
0.05In~30In
0.001A
0~100s
0.001s
0~2
0~1
7 Settings
15
50/51G2.En
16
50/51G2.OutMap
17
50/51G3.3I0_Set
18
50/51G3.t_Op
19
50/51G3.Opt_Dir
20
50/51G3.En_Hm_Blk
21
50/51G3.En
22
50/51G3.OutMap
23
50/51G4.3I0_Set
24
50/51G4.t_Op
25
50/51G4.Opt_Dir
26
50/51G4.En_Hm_Blk
27
50/51G4.En
28
50/51G4.OutMap
29
50/51G4.Opt_Curve
30
50/51G4.TMS
31
50/51G4.tmin
32
50/51G4.K
33
50/51G4.C
34
50/51G4.Alpha
0~1
0x00000000 ~
0x7FFFFFFF
0.001A
0~100s
0.001s
0~2
0~1
0~1
0x00000000 ~
0x7FFFFFFF
0.001A
0~100s
0.001s
0~2
0~1
0~1
0x00000000 ~
0x7FFFFFFF
0.05In~30In
0.05In~30In
0~13
0.05~100.0
0.001
0~100s
0.001s
0.001~120.0
0.0001
0.00~1.00
0.0001
0.01~3.00
0.0001
NOTE!
1.
The setting [50/51Gx.Opt_Dir] (x: 1~4) is used to select the directional mode for the No.1
7-7
7 Settings
stage x (x: 1~4) zero sequence overcurrent protection respectively. 0 is the non-directional
mode; 1 is the forward directional mode; and 2 is the reverse directional mode.
All the settings of the No.2 zero sequence overcurrent protection are listed in the following table.
No.
1
Menu text
A.50/51G.RCA
Explanation
The relay characteristic angle for the No.2
directional zero sequence overcurrent protection
Range
Step
-180~179
0~1
0.05~1.00
0.001
0.05In~30In
0.001A
0.05In~30In
0.001A
0~100s
0.001s
0~2
0~1
0~1
A.50/51G.En_VTS_Blk
A.50/51G.K_Hm2
A.50/51G.3I0_Rls_HmBlk
A.50/51G1.3I0_Set
A.50/51G1.t_Op
A.50/51G1.Opt_Dir
A.50/51G1.En_Hm_Blk
A.50/51G1.En
10
A.50/51G1.OutMap
11
A.50/51G2.3I0_Set
12
A.50/51G2.t_Op
13
A.50/51G2.Opt_Dir
14
A.50/51G2.En_Hm_Blk
15
A.50/51G2.En
16
A.50/51G2.OutMap
17
A.50/51G3.3I0_Set
18
A.50/51G3.t_Op
19
A.50/51G3.Opt_Dir
0x00000000 ~
0x7FFFFFFF
0.05In~30In
0.001A
0~100s
0.001s
0~2
0~1
0~1
0x00000000 ~
0x7FFFFFFF
7-8
0.05In~30In
0.001A
0~100s
0.001s
0~2
7 Settings
20
A.50/51G3.En_Hm_Blk
21
A.50/51G3.En
22
A.50/51G3.OutMap
23
A.50/51G4.3I0_Set
24
A.50/51G4.t_Op
25
A.50/51G4.Opt_Dir
26
A.50/51G4.En_Hm_Blk
27
A.50/51G4.En
28
A.50/51G4.OutMap
29
A.50/51G4.Opt_Curve
30
A.50/51G4.TMS
31
A.50/51G4.tmin
32
A.50/51G4.K
33
A.50/51G4.C
34
A.50/51G4.Alpha
0~1
0~1
0x00000000 ~
0x7FFFFFFF
0.05In~30In
0.001A
0~100s
0.001s
0~2
0~1
0~1
0x00000000 ~
0x7FFFFFFF
0~13
0.05~100.0
0.001
0~100s
0.001s
0.001~120.0
0.0001
0.00~1.00
0.0001
0.01~3.00
0.0001
NOTE!
1.
The setting [A.50/51Gx.Opt_Dir] (x: 1~4) is used to select the directional mode for the No.2
stage x (x: 1~4) zero sequence overcurrent protection respectively. 0 is the non-directional
mode; 1 is the forward directional mode; and 2 is the reverse directional mode.
7-9
7 Settings
No.
Menu text
50/51Q1.I2_Set
50/51Q1.t_Op
50/51Q1.En
50/51Q1.OutMap
50/51Q2.I2_Set
50/51Q2.t_Op
50/51Q2.En
50/51Q2.OutMap
50/51Q2.Opt_Curve
10
50/51Q2.TMS
11
50/51Q2.tmin
12
50/51Q2.K
13
50/51Q2.C
14
50/51Q2.Alpha
Explanation
The current setting of the stage 1 negative
sequence overcurrent protection
The time setting of the stage 1 negative sequence
overcurrent protection
The logic setting of the stage 1 negative sequence
overcurrent protection
Range
Step
0.05In~4In
0.001A
0~100s
0.001s
0~1
0x00000000 ~
0x7FFFFFFF
0.05In~4In
0.001A
0~100s
0.001s
0~1
0x00000000 ~
0x7FFFFFFF
0~13
0.05~100.0
0.001
0~100s
0.001s
0.001~120.0
0.0001
0.00~1.00
0.0001
0.01~3.00
0.0001
Menu text
50/51SEF.RCA
Explanation
The relay characteristic angle for the directional
sensitive earth fault protection
Range
Step
-180~179
0~1
0.005~0.4A
0.001A
50/51SEF.En_VTS_Blk
50/51SEF1.3I0_Set
7-10
7 Settings
4
50/51SEF1.t_Op
50/51SEF1.Opt_Dir
50/51SEF1.En
50/51SEF1.OutMap
50/51SEF2.3I0_Set
50/51SEF2.t_Op
10
50/51SEF2.Opt_Dir
11
50/51SEF2.En
12
50/51SEF2.OutMap
13
50/51SEF3.3I0_Set
14
50/51SEF3.t_Op
15
50/51SEF3.Opt_Dir
16
50/51SEF3.En
17
50/51SEF3.OutMap
18
50/51SEF4.3I0_Set
19
50/51SEF4.t_Op
20
50/51SEF4.Opt_Dir
21
50/51SEF4.En
22
50/51SEF4.OutMap
23
50/51SEF4.Opt_Curve
24
50/51SEF4.TMS
25
50/51SEF4.tmin
0~100s
0.001s
0~2
0~1
0x00000000 ~
0x7FFFFFFF
0.005~0.4A
0.001A
0~100s
0.001s
0~2
0~1
0x00000000 ~
0x7FFFFFFF
0.001A
0~100s
0.001s
0~2
0~1
0x00000000 ~
0x7FFFFFFF
fault protection
The time setting of the stage 4 sensitive earth
fault protection
The setting is used to select the directional mode
for the stage 4 SEF protection, see Section 3.6.3
The logic setting of the stage 4 sensitive earth
fault protection
0.001A
0~100s
0.001s
0~2
0~1
0x00000000 ~
0x7FFFFFFF
0.005~0.4A
0.005~0.4A
0~13
0.05~100.0
0.001
0~100s
0.001s
7-11
7 Settings
26
50/51SEF4.K
27
50/51SEF4.C
28
50/51SEF4.Alpha
0.001~120.0
0.0001
0.00~1.00
0.0001
0.01~3.00
0.0001
NOTE!
1.
The setting [50/51SEFx.Opt_Dir] (x: 1~4) is used to select the directional mode for the stage x
(x: 1~4) sensitive earth fault protection respectively. 0 is the non-directional mode; 1 is the
forward directional mode; and 2 is the reverse directional mode.
Menu text
50BF.I_Set
50BF.t_Op
50BF.t_ReTrp
50BF.Opt_LogicMode
50BF.En
50BF.En_ReTrp
50BF.OutMap
50BF.OutMap_ReTrp
Explanation
The current setting of the breaker failure
protection
The time setting of the breaker failure protection
The re-trip time setting of the breaker failure
protection
The setting for selecting the criteria logic of the
breaker failure protection
The logic setting of the breaker failure protection
The logic setting of the re-trip function of the
breaker failure protection
Range
Step
0.05In~5.0In
0.001A
0~100s
0.001s
0~100s
0.001s
1~4
0~1
0~1
0x00000000 ~
protection
0x7FFFFFFF
0x00000000 ~
0x7FFFFFFF
1
1
NOTE!
1.
The setting [50BF.Opt_LogicMode] is used to select the criteria logic of the breaker failure
protection. Four criteria logics based on the phase currents and the circuit breaker state
(based on the binary input [BI_52b]) are supported in this relay.
The two criteria conditions are list as below:
(A) The maximum phase current is greater than the setting [50BF.I_Set].
(B) The circuit breaker is still closed ([BI_52b] = 0).
7-12
7 Settings
Setting Value
Only A
NOT([BI_52b])
Only B
A OR B
A AND B
Menu text
50BC.I2/I1_Set
50BC.t_Op
50BC.En
50BC.OutMap
Explanation
The ratio setting for the broken conductor
protection
The time setting for the broken conductor
protection
The logic setting for the broken conductor
protection
Range
Step
0.10~1.00
0.001
0~200s
0.001s
0~1
0x00000000 ~
protection
0x7FFFFFFF
Menu text
CLP.Opt_LogicMode
CLP.t_Cold
CLP.t_Rst
CLP.t_ShortRst
CLP.En
50/51P1.CLP.IMult
50/51P1.CLP.t_Op
50/51P2.CLP.IMult
Explanation
The setting for selecting the cold load condition
The time setting for ensuring the cold load
condition is met
The time setting for resetting the cold load pickup
logic
The time setting for fast resetting the cold load
pickup logic
The logic setting of the cold load pickup logic
function
The multiple setting of the stage 1 overcurrent
protection when CLP is active
The time setting of the stage 1 overcurrent
protection when CLP is active
The multiple setting of the stage 2 overcurrent
protection when CLP is active
Range
Step
1~2
0~4000s
0.001s
0~4000s
0.001s
0~600s
0.001s
0~1
1.00~10.00
0.001
0~100s
0.001s
1.00~10.00
0.001
7-13
7 Settings
9
50/51P2.CLP.t_Op
10
50/51P3.CLP.IMult
11
50/51P3.CLP.t_Op
12
50/51P4.CLP.IMult
13
50/51P4.CLP.t_Op
14
50/51P4.CLP.TMS
15
50/51G1.CLP.IMult
16
50/51G1.CLP.t_Op
17
50/51G2.CLP.IMult
18
50/51G2.CLP.t_Op
19
50/51G3.CLP.IMult
20
50/51G3.CLP.t_Op
21
50/51G4.CLP.IMult
22
50/51G4.CLP.t_Op
23
50/51G1.CLP.TMS
0~100s
0.001s
1.00~10.00
0.001
0~100s
0.001s
1.00~10.00
0.001
0~100s
0.001s
0.05~100.0
0.001
1.00~10.00
0.001
0~100s
0.001s
1.00~10.00
0.001
0~100s
0.001s
1.00~10.00
0.001
0~100s
0.001s
1.00~10.00
0.001
0~100s
0.001s
0.05~100.0
0.001
Menu text
SOTF.t_En
SOTF.Opt_Mode
50PSOTF.I_Set
Explanation
The enabling time setting of the SOTF protection
The setting for selecting the acceleration tripping
mode of the SOTF protection
The current setting of the SOTF overcurrent
protection
7-14
Range
Step
0~100s
0.001s
0~1
0.05In~30In
0.001A
7 Settings
4
50PSOTF.t_Op
50PSOTF.En
50PSOTF.OutMap
50GSOTF.3I0_Set
50GSOTF.t_Op
50GSOTF.En
10
50GSOTF.OutMap
0~100s
0.001s
0~1
0x00000000 ~
protection
0x7FFFFFFF
0.05In~30In
0.001A
0~100s
0.001s
0~1
0x00000000 ~
0x7FFFFFFF
NOTE!
1.
The setting [SOTF.t_En] is used to enable the SOTF protection for the appointed time delay,
when the enabling conditions are satisfied (See Section 3.10).
2.
The setting [SOTF.Opt_Mode] is used for selecting the acceleration tripping mode of the
SOTF protection. Setting as 1 means accelerated tripping before auto-reclosing; and setting
as 0 means accelerated tripping after auto-reclosing.
Menu text
49.Ib_Set
49.Tau
Explanation
The reference current setting of the thermal
overload protection
The time constant setting of the IDMT overload
protection
Range
Step
0.05In~3.0In
0.001A
10~6000s
0.001s
1.0~3.0
0.001
1.0~3.0
0.001
0~1
0~1
49.K_Trp
49.K_Alm
49.En_Trp
49.En_Alm
7-15
7 Settings
7
49.OutMap
0x00000000 ~
protection
0x7FFFFFFF
Menu text
27P.Opt_1P/3P
27P.Opt_Up/Upp
27P1.U_Set
27P1.t_Op
27P1.K_DropOut
27P1.En
27P1.OutMap
27P2.U_Set
27P2.t_Op
10
27P2.K_DropOut
11
27P2.En
12
27P2.OutMap
13
59P.Opt_1P/3P
14
59P.Opt_Up/Upp
15
59P1.U_Set
16
59P1.t_Op
17
59P1.K_DropOut
Explanation
The
setting
for
selecting
Range
the
undervoltage
0~1
0~1
2~120V
0.001V
0~100s
0.001s
1.03~3.0
0.001
0~1
0x00000000 ~
undervoltage protection
0x7FFFFFFF
0.001V
0~100s
0.001s
1.03~3.0
0.001
0~1
0x00000000 ~
undervoltage protection
0x7FFFFFFF
setting
for
selecting
the
overvoltage
7-16
2~120V
Step
0~1
0~1
57.7~200V
0.001V
0~100s
0.001s
0.93~0.97
0.001
7 Settings
18
59P1.En
19
59P1.OutMap
20
59P2.U_Set
21
59P2.t_Op
22
59P2.K_DropOut
23
59P2.En
24
59P2.OutMap
0~1
0x00000000 ~
overvoltage protection
0x7FFFFFFF
57.7~200V
0.001V
0~100s
0.001s
0.93~0.97
0.001
0~1
0x00000000 ~
overvoltage protection
0x7FFFFFFF
NOTE!
1.
See Section 3.12 and Section 3.13 for more details about the settings [27P.Opt_1P/3P],
[27P.Opt_Up/Upp], [59P.Opt_1P/3P] and [59P.Opt_Up/Upp].
Menu text
59Q.U2_Set
59Q.t_Op
59Q.En
59Q.OutMap
Explanation
The voltage setting of the negative sequence
overvoltage protection
The time setting of the negative sequence
overvoltage protection
The logic setting of the negative sequence
overvoltage protection
Range
Step
2~120V
0.001V
0~100s
0.001s
0~1
0x00000000 ~
0x7FFFFFFF
Menu text
59G1.3U0_Set
Explanation
The voltage setting of the stage 1 zero sequence
overvoltage protection
Range
2~160V
Step
0.001V
7-17
7 Settings
2
59G1.t_Op
59G1.En
59G1.OutMap
59G2.3U0_Set
59G2.t_Op
59G2.En
59G2.OutMap
0~100s
0.001s
0~1
0x00000000 ~
0x7FFFFFFF
2~160V
0.001V
0~100s
0.001s
0~1
0x00000000 ~
0x7FFFFFFF
Menu text
81.Upp_VCE
81U1.f_Set
81U1.t_Op
81U1.En
81U1.OutMap
81U2.f_Set
81U2.t_Op
81U2.En
81U2.OutMap
10
81U3.f_Set
11
81U3.t_Op
Explanation
Range
frequency
setting
of
the
stage
under-frequency protection
The time setting of the stage 1 under-frequency
protection
The logic setting of the stage 1 under-frequency
protection
10~120V
0.001V
45~60Hz
0.001Hz
0~100s
0.001s
0~1
0x00000000 ~
under-frequency protection
0x7FFFFFFF
The
frequency
setting
of
the
stage
under-frequency protection
The time setting of the stage 2 under-frequency
protection
The logic setting of the stage 2 under-frequency
protection
0.001Hz
0~100s
0.001s
0~1
0x00000000 ~
under-frequency protection
0x7FFFFFFF
frequency
setting
of
the
stage
under-frequency protection
The time setting of the stage 3 under-frequency
protection
7-18
45~60Hz
Step
45~60Hz
0.001Hz
0~100s
0.001s
7 Settings
12
81U3.En
13
81U3.OutMap
14
81U4.f_Set
15
81U4.t_Op
16
81U4.En
17
81U4.OutMap
18
81O1.f_Set
19
81O1.t_Op
20
81O1.En
21
81O1.OutMap
22
81O2.f_Set
23
81O2.t_Op
24
81O2.En
25
81O2.OutMap
26
81O3.f_Set
27
81O3.t_Op
28
81O3.En
29
81O3.OutMap
30
81O4.f_Set
31
81O4.t_Op
32
81O4.En
33
81O4.OutMap
0~1
0x00000000 ~
under-frequency protection
0x7FFFFFFF
The
frequency
setting
of
the
stage
under-frequency protection
The time setting of the stage 4 under-frequency
protection
The logic setting of the stage 4 under-frequency
protection
0.001Hz
0~100s
0.001s
0~1
0x00000000 ~
under-frequency protection
0x7FFFFFFF
frequency
setting
of
the
stage
over-frequency protection
The time setting of the stage 1 over-frequency
protection
The logic setting of the stage 1 over-frequency
protection
0.001Hz
0~100s
0.001s
0~1
0x00000000 ~
over-frequency protection
0x7FFFFFFF
frequency
setting
of
the
stage
over-frequency protection
The time setting of the stage 2 over-frequency
protection
The logic setting of the stage 2 over-frequency
protection
0.001Hz
0~100s
0.001s
0~1
0x00000000 ~
over-frequency protection
0x7FFFFFFF
frequency
setting
of
the
stage
over-frequency protection
The time setting of the stage 3 over-frequency
protection
The logic setting of the stage 3 over-frequency
protection
0.001Hz
0~100s
0.001s
0~1
0x00000000 ~
over-frequency protection
0x7FFFFFFF
frequency
setting
of
the
stage
over-frequency protection
The time setting of the stage 4 over-frequency
protection
The logic setting of the stage 4 over-frequency
protection
50~65Hz
50~65Hz
50~65Hz
45~60Hz
50~65Hz
0.001Hz
0~100s
0.001s
0~1
0x00000000 ~
over-frequency protection
0x7FFFFFFF
7-19
7 Settings
34
81R1.df/dt_Set
35
81R1.f_Pkp
36
81R1.t_Op
37
81R1.En
38
81R1.OutMap
39
81R2.df/dt_Set
40
81R2.f_Pkp
41
81R2.t_Op
42
81R2.En
43
81R2.OutMap
44
81R3.df/dt_Set
45
81R3.f_Pkp
46
81R3.t_Op
47
81R3.En
48
81R3.OutMap
49
81R4.df/dt_Set
50
81R4.f_Pkp
51
81R4.t_Op
52
81R4.En
53
81R4.OutMap
The
setting
of
the
stage
frequency
rate-of-change protection
The pickup frequency setting of the stage 1
frequency rate-of-change protection
The time setting of the stage 1 frequency
rate-of-change protection
The logic setting of the stage 1 frequency
rate-of-change protection
-10~10Hz/s
0.001Hz
0~100s
0.001s
0~1
0x00000000 ~
rate-of-change protection
0x7FFFFFFF
setting
of
the
stage
frequency
rate-of-change protection
The pickup frequency setting of the stage 2
frequency rate-of-change protection
The time setting of the stage 2 frequency
rate-of-change protection
The logic setting of the stage 2 frequency
rate-of-change protection
-10~10Hz/s
0.001s
0~1
0x7FFFFFFF
the
stage
frequency
rate-of-change protection
The pickup frequency setting of the stage 3
frequency rate-of-change protection
The time setting of the stage 3 frequency
rate-of-change protection
The logic setting of the stage 3 frequency
rate-of-change protection
-10~10Hz/s
0.001s
0~1
0x7FFFFFFF
the
stage
frequency
rate-of-change protection
The pickup frequency setting of the stage 4
frequency rate-of-change protection
The time setting of the stage 4 frequency
rate-of-change protection
The logic setting of the stage 4 frequency
rate-of-change protection
Hz/s
0~100s
rate-of-change protection
of
0.001
0.001Hz
0x00000000 ~
setting
45~65Hz
Hz/s
0~100s
rate-of-change protection
of
0.001
0.001Hz
0x00000000 ~
setting
45~65Hz
Hz/s
45~65Hz
0.001
-10~10Hz/s
1
0.001
Hz/s
45~65Hz
0.001Hz
0~100s
0.001s
0~1
0x00000000 ~
rate-of-change protection
0x7FFFFFFF
7 Settings
All the settings of the auto-recloser are listed in the following table.
No.
Menu text
79.t_CBClsd
79.t_DDO_BlkAR
79.t_CBReady
79.t_Fail
79.t_3PS1
6
7
79.t_3PS2
79.t_3PS3
Explanation
The time setting of the minimum time delay for
ensuring the CB is closed
The time pulse width for ensuring the AR blocking
signal
The time setting of the time delay for ensuring the
CB is ready
The time setting of the time delay for checking the
CB position
The time setting of the 1st shot auto-recloser
nd
Range
Step
0.01~600s
0.001s
0.01~600s
0.001s
0.01~600s
0.001s
0.01~600s
0.001s
0~600s
0.001s
shot auto-recloser
0~600s
0.001s
rd
0~600s
0.001s
th
79.t_3PS4
0~600s
0.001s
79.t_Reclaim
0~600s
0.001s
10
79.t_DDO_AR
0-4.00s
0.001s
11
79.N_Rcls
1~4
12
79.En_SynChk
0~1
13
79.En_DdChk
0~1
14
79.En_FailChk
0~1
15
79.En
0~1
16
79.OutMap
0x00000000 ~
0x7FFFFFFF
NOTE!
1.
If the settings [79.En_SynChk] and [79.En_DdChk] are both set as 0, it means that the
non-check mode is applied in the auto-reclosing logic.
Menu text
MR1.t_Op
MR1.En
Explanation
The
time
setting
of
the
Range
No.1
mechanical
protection
The logic setting of the No.1 mechanical
protection
Step
0~4000s
0.001s
0~1
7-21
7 Settings
3
MR1.OutMap
MR2.t_Op
MR2.En
MR2.OutMap
MR3.t_Op
MR3.En
MR3.OutMap
10
MR4.t_Op
11
MR4.En
12
MR4.OutMap
0x00000000 ~
protection
0x7FFFFFFF
The
time
setting
of
the
No.2
mechanical
protection
The logic setting of the No.2 mechanical
protection
0~4000s
0.001s
0~1
0x00000000 ~
protection
0x7FFFFFFF
The
time
setting
of
the
No.3
mechanical
protection
The logic setting of the No.3 mechanical
protection
0.001s
0~1
0x00000000 ~
protection
0x7FFFFFFF
time
setting
of
the
No.4
mechanical
protection
The logic setting of the No.4 mechanical
protection
0~4000s
0~4000s
0.001s
0~1
0x00000000 ~
protection
0x7FFFFFFF
Menu text
Explanation
Range
Step
50DZ.I_Set
0.1In~5.0In
0.001A
50DZ.t_Op
0~100s
0.001s
50DZ.En
0~1
50DZ.OutMap
0x00000000 ~
protection
0x7FFFFFFF
Menu text
Explanation
Range
Step
37.I_Set
0.1In~1.0In
0.001A
37.t_Op
0~100s
0.001s
37.En
0~1
7-22
7 Settings
4
37.OutMap
0x00000000 ~
protection
0x7FFFFFFF
Menu text
Explanation
Range
Step
CTS.3I0_Set
0.05In~30In
0.001A
CTS.3U0_Set
0.01~120V
0.001V
CTS.En
0~1
VTS.I_Set
0.05In~30In
0.001A
VTS.I2_Set
0.05In~30In
0.001A
VTS.En
0~1
VTS.En_SynVT
0~1
Menu text
Explanation
Range
Step
B09.BO_03.t_Dwell
0~100s
0.001s
B09.BO_04.t_Dwell
0~100s
0.001s
B09.BO_05.t_Dwell
0~100s
0.001s
B09.BO_06.t_Dwell
0~100s
0.001s
B09.BO_07.t_Dwell
0~100s
0.001s
B09.BO_08.t_Dwell
0~100s
0.001s
B06.BO_01.t_Dwell
0~100s
0.001s
B06.BO_02.t_Dwell
0~100s
0.001s
B06.BO_03.t_Dwell
0~100s
0.001s
10
B06.BO_04.t_Dwell
0~100s
0.001s
11
B06.BO_05.t_Dwell
0~100s
0.001s
12
B06.BO_06.t_Dwell
0~100s
0.001s
NOTE!
1.
The setting [Bxx.BO_xx.t_Dwell] (x: a number; 1, 2 etc.) is used to set the dwell time of the
relevant binary output in module NR4304 and NR4521.
7-23
7 Settings
Menu text
Explanation
Range
Step
25.U_Dd
2~120V
0.001V
25.U_Lv
2~120V
0.001V
25.U_Comp
0.2~5.0
0.001
25.phi_Comp
0~360
25.Opt_Usyn
0~5
25.t_ClsCB
0.02~1.00s
0.001s
25M.U_Diff
2~120V
0.001V
25M.f_Diff
0~2Hz
0.001Hz
25M.df/dt
10
25M.phi_Diff
11
25M.t_Wait
12
25M.Opt_DdChk
13
25M.En_SynChk
14
25M.En_DdChk
15
25A.U_Diff
16
25A.f_Diff
17
25A.phi_Diff
frequency
difference
setting
of
the
7-24
0~3Hz/s
0.001
Hz/s
0~60
0.01~30s
0.001s
1~7
0~1
0~1
2~120V
0.001V
0~2Hz
0.001Hz
0~60
7 Settings
18
25A.t_Wait
19
25A.Opt_DdChk
20
25A.t_DdChk
21
25A.t_SynChk
0.01~60s
0.001s
1~7
0.01~25s
0.001s
0.01~25s
0.001s
NOTE!
1.
The settings [25.U_Comp] and [25.phi_Comp] are used to compensate the synchro-check
voltage, and make the compensated synchro-check voltage is equal to the corresponding
protection voltage in normal operation situation.
The settings [25.U_Comp] and [25.phi_Comp] can be set according to following formula.
The synchro-check VT supplies 110V secondary rated voltage while the protection VT
supplies 100V secondary rated voltage. Therefore, this difference must be balanced:
[25.U_Comp] = 100V / 110V = 0.91
The transformer vector group is defined from the high voltage side to the low voltage side. In
this example, the synchro-check voltage is one of the voltages of the high voltage side, i.e. the
compensation angle setting is 30 (according to the vector group):
[25.phi_Comp] = 30
2.
The setting [25.Opt_Usyn] is used to select the synchro-check voltage source of the
synchronism check element, and this relay can use the corresponding protection voltage for
the synchronism check element.
Setting Value
Voltage Type
Ua
Ub
Uc
Uab
Ubc
Uca
7-25
7 Settings
Menu text
Ctrl1.t_PW_Opn
Ctrl1.t_PW_Cls
Ctrl1.OutMap_Opn
Ctrl1.OutMap_Cls
Ctrl2.t_PW_Opn
Ctrl2.t_PW_Cls
Ctrl2.OutMap_Opn
Ctrl2.OutMap_Cls
Ctrl3.t_PW_Opn
10
Ctrl3.t_PW_Cls
11
Ctrl3.OutMap_Opn
12
Ctrl3.OutMap_Cls
13
Ctrl4.t_PW_Opn
14
Ctrl4.t_PW_Cls
15
Ctrl4.OutMap_Opn
16
Ctrl4.OutMap_Cls
17
Ctrl5.t_PW_Opn
18
Ctrl5.t_PW_Cls
Explanation
The output pulse width of the No.1 manual
tripping element
The output pulse width of the No.1 manual closing
element
Range
0.1~99.0s
0.001s
0.1~99.0s
0.001s
0x00000000 ~
tripping element
0x7FFFFFFF
0x00000000 ~
closing element
0x7FFFFFFF
0.1~99.0s
0.001s
tripping element
0x7FFFFFFF
0x00000000 ~
closing element
0x7FFFFFFF
0.1~99.0s
0.001s
tripping element
0x7FFFFFFF
0x00000000 ~
closing element
0x7FFFFFFF
0.1~99.0s
0.001s
tripping element
0x7FFFFFFF
0x00000000 ~
closing element
0x7FFFFFFF
7-26
1
0.001s
0x00000000 ~
tripping element
0.1~99.0s
1
0.001s
0x00000000 ~
tripping element
0.1~99.0s
1
0.001s
0x00000000 ~
tripping element
0.1~99.0s
Step
1
1
0.1~99.0s
0.001s
0.1~99.0s
0.001s
7 Settings
19
Ctrl5.OutMap_Opn
20
Ctrl5.OutMap_Cls
0x00000000 ~
tripping element
0x7FFFFFFF
0x00000000 ~
closing element
0x7FFFFFFF
1
1
Menu text
Interlock1.En_BlkOpn
Interlock1.En_BlkCls
Interlock2.En_BlkOpn
Interlock2.En_BlkCls
Interlock3.En_BlkOpn
Interlock3.En_BlkCls
Interlock4.En_BlkOpn
Interlock4.En_BlkCls
Interlock5.En_BlkOpn
10
Interlock5.En_BlkCls
Explanation
The logic setting of the interlock check of the No.1
manual tripping element
The logic setting of the interlock check of the No.1
manual closing element
The logic setting of the interlock check of the No.2
manual tripping element
The logic setting of the interlock check of the No.2
manual closing element
The logic setting of the interlock check of the No.3
manual tripping element
The logic setting of the interlock check of the No.3
manual closing element
The logic setting of the interlock check of the No.4
manual tripping element
The logic setting of the interlock check of the No.4
manual closing element
The logic setting of the interlock check of the No.5
manual tripping element
The logic setting of the interlock check of the No.5
manual closing element
Range
Step
0~1
0~1
0~1
0~1
0~1
0~1
0~1
0~1
0~1
0~1
NOTE!
1.
The interlock check function can be programmed through the PCS-Explorer configuration tool
auxiliary software.
7-27
7 Settings
Menu text
HDR_EncodeMode
Opt_Caption_103
B07.Un_BinaryInput
Opt_CT_Measmt
Explanation
The encoding type of the HDR waveform file, it is
Range
Step
0~1
0~2
0~5
0~1
NOTE!
1.
The setting [Opt_Caption_103] is used for selecting the language of the group caption when
the IEC60870-5-103 protocol is adopted. If it is set as 1, the group caption language is
Chinese; if it is set as 2, the group caption language is English; and if it is set as 0, the
group caption language is the language which is selected through the submenu Language.
2.
The setting [B07.Un_BinaryInput] is used for selecting the rated voltage of the binary input.
7-28
7 Settings
3.
Setting Value
Rated Voltage
24V
48V
110V
220V
30V
125V
The setting [Opt_CT_Measmt] is used for selecting the source of the metering current values.
If it is set as 1, the calculation of the metering current values is based on the sampled data
from the dedicated metering current transformers of this relay; and if it is set as 0, the
calculation of the metering current values is based on the sampled data from the protection
current transformers of this relay.
Menu text
Explanation
Range
IP_LAN1
000.000.000.000
Mask_LAN1
~255.255.255.255
IP_LAN2
000.000.000.000
Mask_LAN2
~255.255.255.255
En_LAN2
0~1
IP_LAN3
000.000.000.000
Mask_LAN3
~255.255.255.255
En_LAN3
0~1
IP_LAN4
000.000.000.000
10
Mask_LAN4
~255.255.255.255
11
En_LAN4
0~1
12
Gateway
000.000.000.000
device
~255.255.255.255
13
En_Broadcast
14
Addr_RS485A
0 ~ 255
15
Baud_RS485A
0~5
16
Protocol_RS485A
0~2
17
Addr_RS485B
0 ~ 255
18
Baud_RS485B
0~5
19
Protocol_RS485B
0~2
20
Threshold_Measmt
21
Period_Measmt
22
Format_Measmt
23
Baud_Printer
0~5
24
En_AutoPrint
0~1
0~1
0 ~ 100 (%)
0 ~ 65535s
0~1
7-29
7 Settings
25
Opt_TimeSyn
0~3
26
IP_Server_SNTP
27
OffsetHour_UTC
-12 ~ 12
28
OffsetMinute_UTC
0 ~ 60
29
En_DaulNet_GOOSE
000.000.000.000
~255.255.255.255
0~1
function
NOTE!
1.
Above table listed all the communication settings, the device delivered to the user maybe only
show some settings of them according to the communication interface configuration. If only
the Ethernet ports are applied, the settings about the serial ports (port A and port B) are not
listed in this submenu. And the settings about the Ethernet ports only listed in this submenu
according to the actual number of Ethernet ports.
2.
The standard arrangement of the Ethernet port is two, at most four (predetermined when
ordering). Set the IP address according to actual arrangement of Ethernet numbers and the
unused port/ports need not to be configured. If the PCS-Explorer configuration tool auxiliary
software is connected with this device through the Ethernet, the IP address of the
PCS-Explorer must be set as one of the available IP address of this device.
3.
The setting [En_Broadcast] is used to enable or disable this relay to transmit the UDP
broadcast messages when the IEC60870-5-103 protocol is adopted. If it is set as 0, this
relay does not transmit any UDP broadcast message; and if it is set as 1, this relay can
transmit UDP broadcast messages.
4.
The setting [Addr_RS485A] and [Addr_RS485B] are used to set the communication address
of the serial ports (port A and port B); if a protocol over serial communication is adopted.
5.
6.
Setting Value
Baudrate (bsp)
4800
9600
19200
38400
57600
115200
The settings [Protocol_RS485A] and [Protocol_RS485B] are respectively used to set the
communication protocol of each serial port (port A and port B).
Setting Value
Protocol
Setting Value
IEC60870-5-103
Modbus
1
Other
Protocol
Reserved
Not available
7.
The setting [Threshold_Measmt] is used to decide whether the present metering value is
sends forward. Only the change percent of a metering value is greater than this setting, the
relevant metering value can be sent forward.
8.
The circle time for sending telemetering [Period_Measmt]: It represents the time period when
7-30
7 Settings
this device sends metering data forward. When this setting is set as 0, it means that the
equipment will not send metering data forward at a fixed time (the inquiry issued by SCADA
still can be responded during this period). This setting may be set according to actual field
condition and can be set as 0 when the communication function is not used. The default
value is 0 when the equipment is delivered.
9.
The setting [Format_Measmt] is used to select the metering data format in the GDD (Generic
Data Description) message when the IEC60870-5-103 protocol is adopted. If it is set as 0,
the metering data format type is 12 (Measurand with Quality Descriptor); and if it is set as 1,
the metering data format type is 7 (R32.23, IEEE 754).
10. The setting [Opt_TimeSyn] is used to select the external time synchronization source.
Setting Value
0
1
2
3
If this setting is set as 1, if this device does not receive time synchronization message or
receives error time synchronization message, it will alarm; and if this setting is set as 0 or 2,
if this device does not receive the time synchronization signal, it will alarm and switch to
message time synchronization mode automatically.
11. The setting [IP_Server_SNTP] is used to set the IP address of the SNTP server, if this relay
adopts the SNTP time synchronization. If the SNTP time synchronization is not adopted, it is
recommended to set as 000.000.000.000.
12. If the IEC61850 protocol is adopted in substations, the time tags of communication messages
are required according to UTC (Universal Time Coordinated) time.
The setting [OffsetHour_UTC] is used to set the hour offset of the current time zone to the
GMT (Greenwich Mean Time) zone; for example, if a relay is applied in China, the time zone
of China is east 8th time zone, so this setting is set as 8. The setting [OffsetMinute_UTC] is
used to set the minute offset of the current time zone to the GMT zone.
Time zone
Setting
Time zone
Setting
Time zone
Setting
Time zone
Setting
GMT zone
East 1st
East 2nd
East 3rd
East 4th
East 5th
th
th
East 6
East 7
7
th
East 8
8
st
East/West 12
West 1
-12/12
-1
th
th
East 9
9
nd
West 2
-2
th
th
rd
West 3
-3
th
th
East 10
East 11th
10
11
th
West 4
-4
th
West 5th
-5
th
West 6
West 7
West 8
West 9
West 10
West 11th
-6
-7
-8
-9
-10
-11
7-31
7 Settings
13. The setting [En_DualNet_GOOSE] is used to enable or disable the dual-network GOOSE
function if the GOOSE function is supported in this relay. If it is set as 1, the dual-network
GOOSE function is adopted; otherwise, the single-network GOOSE function is adopted.
7-32
List of Figures
Figure 8.1-1 Keypad on the front panel................................................................................... 8-2
8-a
8-b
8.1 Overview
Human machine interface (HMI) is an important component of the equipment. It is a convenient
facility to access the relay from the front local control panel of this relay to view desired information,
such as measurement quantity or binary inputs state or program version etc. or modify some
system settings or protection settings. This function is very helpful during commissioning before
putting the equipment into service.
Furthermore, all above functions can be realized in a remote terminal with special software
through a communication bus via a RS-485 port or an Ethernet port.
This chapter will describe human machine interface (HMI), menu tree and LCD display of the
equipment. In addition, how to input settings using keypad is described in detail.
8.1.1 Design
The human machine interface consists of a human machine interface (HMI) module which allows
the communication as simple as possible for the user. The HMI module includes:
z
A 240128-dot matrix backlight LCD visible in dim lighting conditions for monitoring status,
fault diagnostics and setting etc.
Twenty LED indicators on the front panel of this relay for denoting the operation status of this
device, the color and trigger condition of each LED can be configured through PCS-Explorer.
A 9-key keypad on the front panel of the device for full access to the device.
An Ethernet interface special for the PCS-Explorer configuration tool; for more details, see the
PCS-Explorer online help brochure or the PCS-Explorer configuration tool instruction manual.
Three buttons, a remote/local control switch and three LED indicators for controlling circuit
breaker and releasing the interlock check logics, if the front panel with control buttons is
selected.
The front panel of the device is shown in Figure 6.1-2 and Figure 6.1-3.
8.1.2 Functionality
z
The HMI module helps to draw your attention to something that has occurred which may
activate a LED or a report display on the LCD.
You as the operator may have own interest to view a certain data.
Use menus navigate through menu commands and to locate the data of interest.
8-1
Description
, , ,
+,
ENT
GRP
ESC
Exit the present level menu to main menu, or cancel present operation.
ESC
GR
P
ALARM
TRIP
RECLOSE
CB OPEN
Display
Off
Remarks
When this relay is not energized or any hardware defect is detected
during self-supervision.
Steady Green
Off
Steady Yellow
Off
Steady Red
Off
Steady Red
Off
Steady Red
8-2
Off
Steady Green
NOTE!
z
The HEALTHY LED can only be turned on by supplying power to this device again or
rebooting this device.
The ALARM LED is turned on as long as alarm exists. When alarm signals disappear, it will
be turned off.
The TRIP LED is turned on once any protection element operates and keeps being on even
after the trip command goes off.
The RECLOSE LED is turned on once auto-recloser operates and remains keeps being on
even after the auto-reclosing command goes off.
The CB OPEN LED is turned on once when the circuit breaker is in open position.
The CB CLOSE LED is turned on once when the circuit breaker is in closing position.
The TRIP and RECLOSE LEDs and relevant latched binary outputs can be reset by pressing
the key ENT+ESC, by energizing the binary input [BI_RstTarg] or by executing the
submenu Reset Target.
R
L
Remarks
The button is used to close the circuit breaker if the local control mode is selected. Press
it down for longer than 3s, this device will output a CB closing signal.
The button is used to open the circuit breaker if the local control mode is selected. Press
it down for longer than 3s, this device will output a CB opening signal.
The button is used to release the interlock check logics. Press it down for longer than 3s,
the LED state is changed. If the LED is on, the interlock check logics are released.
8-3
The first line shows the time synchronization state and the current time of this relay. The sign S
on left-top side means this relay receive the clock synchronization signal correctly; if there has
nothing on left-top side, it means the time synchronization is not correct. The current time format of
this relay is yyyy-mm-dd hh:mm:ss.
The middle part of the LCD shows the measurement for the protection.
The last line shows the last section of the IP address and the setting group number. The battery
sign on the left-bottom is used to indicate the ready state of the auto-recloser. When the battery
sign is solid ( ), it means that the auto-recloser is ready; when the battery sign is empty ( ), it
means that the auto-recloser is blocked; and when the battery sign is half solid ( ), it means that
the auto-recloser is in reclaiming procedure.
When the default screen is being shown, press key to enter the main menu of this relay.
The following figure shows the menu tree structure of this device.
Press key , , or to select a submenu and the press key ENT to show the details.
NOTE! This manual introduces all the submenus and their functions which maybe can be
supplied by this relay. Some submenus are not configured if the relevant functions are
not supported in this relay. So the practical submenus of this relay should be taken as
final and binding.
8-5
Item
Description
Measurements1
Measurements2
Item
Description
Primary Values
Secondary Values
Item
Description
Primary Values
Secondary Values
Primary Power
Secondary Power
Synchrocheck
Press key to enter the main menu in the default displaying situation.
2.
Press key or to locate the cursor on the submenu Measurements and press key
ENT to enter this submenu.
3.
Press key or to locate the cursor on the submenu Measurements1 and press key
ENT to enter this submenu.
4.
Press key or to locate the cursor on the submenu Secondary Values and press
key ENT to enter this submenu.
5.
The following tables show all the measurement values of this relay.
8-6
Symbol
Description
Ia
Ib
Ic
I1
I2
3I0_Cal
3I0_Ext1
3I0_Ext2
3I0_SEF
10
Ua
11
Ub
12
Uc
13
Uab
14
Ubc
15
Uca
16
U1
17
U2
18
3U0_Cal
19
3U0_Ext
20
Ux
21
22
Ang(Ia-Ib)
23
Ang(Ib-Ic)
24
Ang(Ic-Ia)
25
Ang(Ua-Ia)
26
Ang(Ub-Ib)
27
Ang(Uc-Ic)
28
Ang(Ua-Ub)
29
Ang(Ub-Uc)
30
Ang(Uc-Ua)
31
Ang(Uab-Ux)
32
Ang(3U0-3I0_Cal)
Symbol
Description
Ia
Ib
Ic
3I0_Ext1
Ua
8-7
Ub
Uc
Uab
Ubc
10
Uca
11
12
Ang(Ia-Ib)
13
Ang(Ib-Ic)
14
Ang(Ic-Ia)
15
Ang(Ua-Ia)
16
Ang(Ub-Ib)
17
Ang(Uc-Ic)
18
Ang(Ua-Ub)
19
Ang(Ub-Uc)
20
Ang(Uc-Ua)
Symbol
Description
Active power
Reactive power
COS
Power factor
PHr+
QHr+
PHr-
QHr-
Symbol
Description
25M.U_Diff
25M.f_Diff
25M.phi_Diff
25A.U_Diff
25A.f_Diff
25A.phi_Diff
Item
Description
Inputs
Outputs
Superv State
Item
Description
Contact Inputs
GOOSE Inputs
Prot Inputs
Interlock Status
Item
Description
Contact Outputs
GOOSE Outputs
Item
Description
Prot Superv
GOOSE Superv
Press key to enter the main menu in the default displaying situation.
2.
Press key or to locate the cursor on the submenu Status and press key ENT to
enter this submenu.
3.
Press key or to locate the cursor on the submenu Inputs and press key ENT to
enter this submenu.
4.
Press key or to locate the cursor on the submenu Contact Inputs and press key
ENT to enter this submenu.
5.
8-9
Figure 8.2-5 LCD display of the status of the general binary inputs
The following tables show all the binary signal status of this relay.
General binary input status
No.
Symbol
Description
B07.BI_01
B07.BI_02
B07.BI_03
B07.BI_04
B07.BI_05
B07.BI_06
B07.BI_07
B07.BI_08
B07.BI_09
10
B07.BI_10
11
B07.BI_11
12
B07.BI_12
13
B07.BI_13
14
B07.BI_14
15
B07.BI_15
16
B07.BI_16
17
B07.BI_17
18
B07.BI_18
19
B07.BI_19
20
The signal symbol of a binary input is B0x.BI_yy; x is the sequence number of the binary input
module location in the rack of this relay, and yy is the sequence number of the binary input at the
binary input module. For the details about the binary inputs, see Section 6.8.
GOOSE binary input status
No.
Symbol
Description
GBI_001
GBI_002
8-10
See the GOOSE related instruction manual for the more information and details.
z
Symbol
BI_52b
The binary input of the state of the CB normally closed contact signal
BI_52a
The binary input of the state of the CB normally opened contact signal
Ctrl.Sig_EnCtrl
Ctrl.Sig_Unblock
Ctrl1. Sig_ManSynChk
The binary input of the enabling synchronism check for manual closing
Ctrl1. Sig_ManDdChk
The binary input of the enabling dead check for manual closing
79.Blk
79.Ready
BI_LowPres_Trp
10
BI_LowPres_Cls
11
BI_TrigDFR
12
BI_RstTarg
Description
Symbol
Description
Interlock1.Sig_Opn
Interlock1.Sig_Cls
Interlock2.Sig_Opn
Interlock2.Sig_Cls
Interlock3.Sig_Opn
Interlock3.Sig_Cls
Interlock4.Sig_Opn
Interlock4.Sig_Cls
Interlock5.Sig_Opn
10
Interlock5.Sig_Cls
Symbol
Description
B09.BO_01
B09.BO_02
B09.BO_03
B09.BO_04
B09.BO_05
B09.BO_06
B09.BO_07
B09.BO_08
The signal symbol of a binary output is B0x.BO_yy; x is the sequence number of the binary
output module location in the rack of this relay, and yy is the sequence number of the binary
8-11
output at the binary output module. For the details about the binary outputs, see Section 6.4 and
Section 6.7.
GOOSE binary output status
No.
Symbol
Description
GBO_Act01
GBO_Act02
GBO_01
GBO_02
See the GOOSE related instruction manual for the more information and details.
Supervision alarm element status
No.
Symbol
Description
Fail_Device
Fail_BoardConfig
Fail_Setting
Fail_Setting_OvRange
Fail_SettingItem_Chgd
Alm_Device
Alm_Setting_MON
Alm_Version
Alm_52b
10
VTS.Alm_SynVT
11
VTS.Alm
12
CTS.Alm
13
49.Alm
14
Alm_CommTest
15
Alm_TimeSync
16
Alm_Maintenance
17
Alm_LowPres_Trp
18
Alm_LowPres_Cls
19
Alm_SpareX
The status of the alarm signal Alm_SpareX (X: a number; 01, 02 etc.)
20
Alm_Sample
For the details about the supervision alarm element, see Section 4.2.
GOOSE alarm element status
No.
Symbol
Description
GAlm_AStorm_PL
GAlm_AStorm_PL
GAlm_CfgFile_PL
8-12
GAlm_ADisc_PL_01
GAlm_BDisc_PL_01
See the GOOSE related instruction manual for the more information and details.
Item
Description
Disturb Records
Superv Events
IO Events
Device Logs
Control Logs
NOTE! Press the key +, -, +, - and ENT in sequence to enter the submenu for
clearing the history reports.
8.2.5.1 View History Fault Report
The history fault report stores the trip elements, trip time and waveform of a selected trip report.
Operating steps:
1.
Press key to enter the main menu in the default displaying situation.
2.
Press key or to locate the cursor on the submenu Records and press key ENT to
enter this submenu.
3.
Press key or to locate the cursor on the submenu Disturb Records and press key
ENT to enter this submenu. If there is no report in the selected submenu, it will show No
Report! on the LCD.
4.
8-13
The first line shows the report title and the sequence number of the history trip report, and the
second line shows the operation time of the history trip report. Other lines show the protection
elements and fault information one by one according to the relative time sequence. The fault
information includes fault phase, maximum fault value and minimum fault value. For more
information about the protection elements and fault information, see Section 8.3.1.
8.2.5.2 View History Alarm Report
The history alarm report stores the alarm elements and alarm time.
Operating steps:
1.
Press key to enter the main menu in the default displaying situation.
2.
Press key or to locate the cursor on the submenu Records and press key ENT to
enter this submenu.
3.
Press key or to locate the cursor on the submenu Superv Events and press key
ENT to enter this submenu. If there is no report in the selected submenu, it will show No
Report! on the LCD.
4.
The first line shows the report title and the sequence number of the history alarm report, and the
second line shows the alarm time of the history alarm report. Other lines show the alarm elements
and state change information one by one. For more information about the alarm elements, see
Section 8.3.2.
8-14
Press key to enter the main menu in the default displaying situation.
2.
Press key or to locate the cursor on the submenu Records and press key ENT to
enter this submenu.
3.
Press key or to locate the cursor on the submenu IO Events and press key ENT
to enter this submenu. If there is no report in the selected submenu, it will show No Report!
on the LCD.
4.
Press key + or - to view the expected history binary state change report.
The first line shows the report title and the sequence number of the history binary input state
change report, and the second line shows the binary state change time of the history binary state
change report. Other lines show the binary state change information one by one. For more
information about the binary signals, see Section 8.2.4.
8.2.5.4 View History User Operation Report
The history user operation report stores the user operation information and user operation time.
Operating steps:
1.
Press key to enter the main menu in the default displaying situation.
2.
Press key or to locate the cursor on the submenu Records and press key ENT to
enter this submenu.
3.
Press key or to locate the cursor on the submenu Device Logs and press key
ENT to enter this submenu.
4.
8-15
The first line shows the report title and the sequence number of the history user operation report,
and the second line shows the user operation time of the history user operation report. Other lines
show the user operation information.
8.2.5.5 View History Control Report
The history control report stores the control information and control time.
Operating steps:
1.
Press key to enter the main menu in the default displaying situation.
2.
Press key or to locate the cursor on the submenu Records and press key ENT to
enter this submenu.
3.
Press key or to locate the cursor on the submenu Control Logs and press key
ENT to enter this submenu.
4.
The first line shows the report title and the sequence number of the history control report, and the
second line shows the control time of the history control report. Other lines show the control
information.
8-16
Access approach:
Move cursor to the item Settings and press key ENT to enter its submenu after entering the
main menu of this device.
The submenu Settings has following submenus.
No.
Item
Description
System Settings
Prot Settings
Mon/Ctrl Settings
Logic Links
Device Setup
Copy Settings
Item
Description
OC Settings
NegOC Settings
EF1 Settings
EF2 Settings
SEF Settings
BFP Settings
BrknCond Settings
SOTF Settings
ThOvLd Settings
10
Voltage Settings
11
NegOV Settings
12
ROV Settings
13
FreqProt Settings
14
AR Settings
15
CLP Settings
To view and modify the settings of the cold load pickup logic
16
MR Prot Settings
17
DZ Settings
18
UC Settings
19
Superv Settings
20
CfgBO Settings
Item
Description
Syn Settings
Control Settings
Interlock Settings
AC Calbr Settings
8-17
Item
Description
Function Links
GOOSE Links
SV Links
Spare Links
Item
Description
Device Settings
Comm Settings
Press key to enter the main menu in the default displaying situation.
2.
Press key or to locate the cursor on the submenu Settings and press key ENT to
enter this submenu.
3.
Press key or to locate the cursor on the submenu Prot Settings and press key
ENT to enter this submenu.
4.
Press key or to locate the cursor on the submenu OC Settings and press key
ENT to enter the selecting interface of the setting group number.
5.
Press key + or - to select the expected setting group number and then press key ENT to
show the settings of the selected group.
6.
8-18
Refer the Section 8.2.6.1 to locate the cursor on the expected setting, and then press key
ENT to enter the setting modification state.
2.
Press key + or - to modify a selected setting, and press key ENT to return to the setting
interface (see Figure 8.2-12) after the selected setting modification is finished.
3.
4.
After finishing the setting modification, press key ESC to prompt the user whether to save
the settings. Select Yes to confirm to save the modified settings. Then the password input
interface is shown on the LCD. Input the correct password and press key ENT to confirm the
modification. If the modification is given up, press key ESC to exit the modification operation.
5.
After confirming the setting modification, it will show Saving Settings on the LCD. Then the
device will restart, and the new settings will be in service.
NOTE! It is necessary to certify whether the modified settings are correct absolutely
before confirming the setting modification.
Press key to enter the main menu in the default displaying situation.
2.
Press key or to locate the cursor on the submenu Settings and press key ENT to
enter this submenu.
3.
Press key or to locate the cursor on the submenu Copy Settings and press key
ENT to enter the interface for copying settings.
4.
Press key + or - to select the expected setting group number and then press key ENT to
show the password input interface.
8-19
5.
Input the correct password and then press key ENT to copy the settings of the active group
to the selected group.
Press key GRP to enter the setting group switch interface in the default displaying situation.
2.
Press key + or - to select the expected setting group number and then press key ENT to
show the password input interface.
3.
Input the correct password and then press key ENT to copy the settings of the active group
to the selected group.
Item
Description
Device Info
Settings
Disturb Records
Superv Events
IO Events
Device Status
Waveforms
8-20
IEC103 Info
Cancel Print
Item
Description
System Settings
Prot Settings
Mon/Ctrl Settings
Logic Links
Device Setup
All Settings
Latest Modified
Press key to enter the main menu in the default displaying situation.
2.
Press key or to locate the cursor on the submenu Print and press key ENT to
enter this submenu.
3.
Press key or to locate the cursor on the submenu Settings and press key ENT to
enter this submenu.
4.
Press key or to locate the cursor on the submenu Prot Settings and press key
ENT to enter this submenu.
5.
Press key or to locate the cursor on the submenu OC Settings and press key
ENT to enter the selecting interface of the setting group number.
6.
Press key + or - to select the expected setting group number and then press key ENT to
print the settings of the selected group.
Press key to enter the main menu in the default displaying situation.
2.
Press key or to locate the cursor on the submenu Print and press key ENT to
enter this submenu.
3.
Press key or to locate the cursor on the submenu Cancel Print and press key
ENT to cancel the present printing content. The information Canceling Print is shown on
the LCD.
8-21
Item
Description
Reset Target
Trig Oscillograph
Download
Clear Counter
Control
Press key to enter the main menu in the default displaying situation.
2.
Press key or to locate the cursor on the submenu Local Cmd and press key ENT
to enter this submenu.
3.
Press key or to locate the cursor on the submenu Reset Target and press key
ENT to restore all the signals and relevant outputs of this relay.
Press key to enter the main menu in the default displaying situation.
2.
Press key or to locate the cursor on the submenu Local Cmd and press key ENT
to enter this submenu.
3.
Press key or to locate the cursor on the submenu Trig Oscillogram and press key
ENT to trigger an oscillogram.
8-22
Press key to enter the main menu in the default displaying situation.
2.
Press key or to locate the cursor on the submenu Local Cmd and press key ENT
to enter this submenu.
3.
Press key or to locate the cursor on the submenu Clear Counter and press key
ENT to clear the statistic information. The information Clear Statistic Data is shown on
the LCD.
The operation steps of the submenu Clear Interlock File and Clear Energy Counter are
similar with the operation steps of the submenu Clear Counter.
8.2.8.4 Control CB through Local HMI
The submenu Control is used to control the circuit breaker through the local HMI of this relay.
There are 5 groups of control elements in this relay. Anyone of them can be used to control
(tripping or closing) a circuit breaker or a disconnector.
Operating steps:
1.
Press key to enter the main menu in the default displaying situation.
2.
Press key or to locate the cursor on the submenu Local Cmd and press key ENT
to enter this submenu.
3.
Press key or to locate the cursor on the submenu Control and press key ENT to
show the password input interface.
4.
Input correct password and then press key ENT to show the control item selection interface.
5.
Press key or to select an expected control element and then press key ENT to show
the password input interface.
6.
Press key +, -, and to enter the correct password and then enter the control object
selection interface, and then press key or to select a control object.
7.
Press key ENT to enter control command selection interface, and then press key or
to select a control command.
8.
Press key ENT to enter control check condition selection interface, and then press key
or to select a control check condition.
9.
Press key ENT to enter control interlock selection interface, and then press key or
to select a control interlock condition.
10. Press key ENT to enter control type selection interface, and then press key or to
8-23
Figure 8.2-16 Control type selection interface and execution result interface
All the items about the control function are listed as below.
Select the control group number
Ctrl1
Ctrl2
Ctrl3
Ctrl4
Ctrl5
close(Raise)
(stop)
8-24
SynchroCheck
DeadCheck
LoopCheck
EF Line Selection
Select the grounding trip check mode, not supported in this relay.
InterlockNotChk
control selection
Execute
control execution
Cancel
control cancellation
Item
Description
Version Info
Board Info
Press key to enter the main menu in the default displaying situation.
2.
Press key or to locate the cursor on the submenu Information and press key ENT
to enter this submenu.
3.
Press key or to locate the cursor on the submenu Version Info and press key
ENT to show the program version information.
4.
Press key or to show all the version information of the main program and the HMI
program.
8-25
The first line shows the title of this interface, other lines show the information of the board
information, including the manufacturer abbreviation name, the device name, the device code, the
program version, the program CRC code and the program creation time.
NOTE! It is only an example for explaining the software version menu. The practical
software version of this relay should be taken as final and binding.
8.2.9.2 View Board Information
All the module information can be known through this menu.
1.
Press key to enter the main menu in the default displaying situation.
2.
Press key or to locate the cursor on the submenu Information and press key ENT
to enter this submenu.
3.
Press key or to locate the cursor on the submenu Board Info and press key ENT
to show the board information.
The first line shows the title of this interface, other lines show the information of the board
information, including the slot sequence number, the module type, the module operation state and
the module configuration state. In normal operation situation, the module configuration state
should be same with the module operation state.
This menu is used to test particular functions of the device, such as testing binary signals, testing
binary outputs and testing telemetering etc. It can provide convenience for the communication test
and the operation electrical circuit.
Access approach:
Move cursor to the item Test and press key ENT to enter its submenu after entering the main
menu of this device.
Submenu structure tree:
The submenu Test maybe has following submenus.
No.
Item
Description
AR Counter
Device Test
Internal Signal
AC Auto Calbr
CptRuntime
Item
Description
Prot Elements
Superv Events
IO Events
Measurements
Contact Outputs
The submenu Prot Elements, Superv Events and IO Events have following submenus.
No.
Item
Description
All Test
Select Test
Press key to enter the main menu in the default displaying situation.
2.
Press key or to locate the cursor on the submenu Test and press key ENT to
enter this submenu.
3.
Press key or to locate the cursor on the submenu Device Test and press key ENT
8-27
Press key or to locate the cursor on the submenu Prot Elements and press key
ENT to enter this submenu.
5.
Press key or to locate the cursor on the submenu Select Test and press key ENT
to show all the protective elements.
6.
Press key or to locate the cursor on a selected protective element and then press key
ENT to create a binary signal.
NOTE! The submenu All Test is used to test all the binary signals automatically.
Press key to enter the main menu in the default displaying situation.
2.
Press key or to locate the cursor on the submenu Test and press key ENT to
enter this submenu.
3.
Press key or to locate the cursor on the submenu Device Test and press key ENT
to enter this submenu.
4.
Press key or to locate the cursor on the submenu Measurements and press key
ENT to all the metering measurements.
5.
Press key or to locate the cursor on a selected metering measurements and press
key + or - to modify the selected metering value.
6.
After finishing the modification, press key ENT to transmit the metering values.
Press key to enter the main menu in the default displaying situation.
2.
Press key or to locate the cursor on the submenu Clock and press key ENT to
enter the clock modification interface.
8-28
3.
Press key or to locate the cursor on a selected item and press key + or - to modify
the selected item.
4.
After finishing the clock modification, press key ENT to confirm the modification.
Press key to enter the main menu in the default displaying situation.
2.
Press key or to locate the cursor on the submenu Language and press key ENT
to enter the language modification interface.
3.
4.
After finishing the language modification, press key ENT to confirm the modification.
8-29
The first line shows the report title and the sequence number of the history trip report, and the
second line shows the operation time of the history trip report. Other lines show the protection
elements and fault information one by one according to the relative time sequence. The fault
information includes fault phase, maximum fault value and minimum fault value.
NOTE! In case more than one protection element has operated, the relevant report will
be displayed alternatively one by one according to time sequence on the LCD. And the
fault information is listed after all the protection elements.
The trip report will keep being displayed on LCD until an acknowledgement is received by pressing
the key ENT+ESC, by energizing the binary input [BI_RstTarg] or by executing the submenu
Reset Target. The default display then appears on LCD and LED TRIP is turned off.
Protection elements listed below may be displayed.
No.
Protection Element
Description
FD.Pkp
Op_Prot
50/51P1.St
50/51P1.Op
50/51P2.St
50/51P2.Op
50/51P3.St
50/51P3.Op
50/51P4.St
10
50/51P4.Op
11
50/51G1.St
8-30
50/51G1.Op
13
50/51G2.St
14
50/51G2.Op
15
50/51G3.St
16
50/51G3.Op
17
50/51G4.St
18
50/51G4.Op
19
A.50/51G1.St
20
A.50/51G1.Op
21
A.50/51G2.St
22
A.50/51G2.Op
23
A.50/51G3.St
24
A.50/51G3.Op
25
A.50/51G4.St
26
A.50/51G4.Op
27
50/51Q1.St
28
50/51Q1.Op
29
50/51Q2.St
30
50/51Q2.Op
31
50/51SEF1.St
32
50/51SEF1.Op
33
50/51SEF2.St
34
50/51SEF2.Op
35
50/51SEF3.St
36
50/51SEF3.Op
37
50/51SEF4.St
38
50/51SEF4.Op
39
50PSOTF.St
40
50PSOTF.Op
41
50GSOTF.St
42
50GSOTF.Op
43
50BC.St
44
50BC.Op
45
49.St
46
49.Op
47
50BF.St
48
50BF.Op
49
50BF.ReTrp
50
27P1.St
51
27P1.Op
52
27P2.St
53
27P2.Op
54
59P1.St
59P1.Op
56
59P2.St
57
59P2.Op
58
59Q.St
59
59Q.Op
60
59G1.St
61
59G1.Op
62
59G2.St
63
59G2.Op
64
81U1.St
65
81U1.Op
66
81U2.St
67
81U2.Op
68
81U3.St
69
81U3.Op
70
81U4.St
71
81U4.Op
72
81O1.St
73
81O1.Op
74
81O2.St
75
81O2.Op
76
81O3.St
77
81O3.Op
78
81O4.St
79
81O4.Op
80
81R1.St
81
81R1.Op
82
81R2.St
83
81R2.Op
84
81R3.St
85
81R3.Op
86
81R4.St
87
81R4.Op
88
79.InProg
89
79.Close_3PS1
90
79.Close_3PS2
91
79.Close_3PS3
92
79.Close_3PS4
93
MR1.St
94
MR1.Op
95
MR2.St
96
MR2.Op
97
MR3.St
8-32
MR3.Op
99
MR4.St
100
MR4.Op
101
50DZ.St
102
50DZ.Op
103
37.St
104
37.Op
Fault Information
Description
Ip_Max
3I0Cal_Max
3I0Ext1_Max
3I0Ext2_Max
3I0SEF_Max
I2/I1_Max
Upp_Min
Upp_Max
Up_Min
10
Up_Max
11
U2_Max
12
Ux_Max
13
Ux_Min
14
f_Max
15
f_Min
See Chapter 3 for more details about the protection operation theory.
8-33
The first line shows the alarm report title, and then shows the alarm elements one by one
according to the time sequence.
The alarm report will keep being displayed on LCD until the relevant alarm situation is restored to
normal state. It means that this relay does not detect any alarm situation. The default display then
appears on LCD and LED ALARM is off. The LED ALARM will not be on if either of the alarm
signals [Fail_Device] and [Fail_Setting] is issued.
Alarm elements listed below may be displayed. See Section 4.2 for more details about the alarm
element operation theory.
No.
Alarm Element
Description
HEALTHY
ALARM
Fail_Device
Off
Fail_BoardConfig
Off
Fail_Setting
Off
Fail_Setting_OvRange
Off
Fail_SettingItem_Chgd
Off
Alm_Device
On
Alm_Setting_MON
On
Alm_Version
On
Alm_52b
On
10
VTS.Alm_SynVT
On
11
VTS.Alm
On
12
CTS.Alm
On
13
49.Alm
On
14
Alm_CommTest
On
15
Alm_TimeSync
On
16
Alm_Maintenance
On
17
Alm_LowPres_Trp
On
18
Alm_LowPres_Cls
On
19
Alm_SpareX
On
20
Alm_Sample
On
Here, On means the LED is on, Off means the LED is off, and means having no influence.
NOTE! When this relay is energized, in the startup process, the LED HEALTHY is off
and the LED ALARM is on.
The handling suggestions of the alarm events are listed as below.
No.
Alarm Element
Handing Suggestion
Fail_Device
Fail_BoardConfig
Please check whether the board configuration complies with the software.
Fail_Setting
8-34
Fail_Setting_OvRange
Fail_SettingItem_Chgd
Alm_Device
Alm_Setting_MON
Alm_Version
Alm_52b
Please check the auxiliary open position contact of the circuit breaker.
10
VTS.Alm_SynVT
11
VTS.Alm
12
CTS.Alm
13
49.Alm
14
Alm_CommTest
15
Alm_TimeSync
16
Alm_Maintenance
Please check whether the binary input for denoting maintenance is energized.
17
Alm_LowPres_Trp
18
Alm_LowPres_Cls
19
Alm_SpareX
Please check whether the relevant alarm issuing conditions are satisfied.
20
Alm_Sample
Please replace the main CPU board or inform the manufacturer to deal with it.
correct, the relevant operation can be done; otherwise, it will show the input interface on the LCD
to prompt the user to input the password again.
The password for control operation is fixed, and it is 111; and the password for modifying the
device settings, and it is 114.
The following figure shows the password input interface for control operation and device setting
modification.
Figure 8.4-1 Password input interface for control operation and device setting modification
The password for modifying settings (except the device settings) is fixed, and it is press key +,
, and - in sequence.
The following figure shows the password input interface for modifying settings.
8-36
9 Configurable Function
9 Configurable Function
Table of Contents
9.1 General Description .........................................................................................9-1
9.2 Introduction of PCS-Explorer Software ..........................................................9-1
9.3 Configurable Information.................................................................................9-2
9.3.1 Configurable Input Signals................................................................................................. 9-2
9.3.2 Configurable Output Signals .............................................................................................. 9-7
9.3.3 Configurable LED Indicators .............................................................................................9-11
9.3.4 Configurable Binary Inputs................................................................................................9-11
9.3.5 Configurable Binary Outputs............................................................................................ 9-12
9-a
9 Configurable Function
9-b
9 Configurable Function
For more details about how to do a logic graph configuration, see the PCS-Explorer online help
brochure or the instruction manual of PCS-Explorer configuration tool auxiliary software.
9-1
9 Configurable Function
Input Signal
Description
Default
The binary input of the auxiliary normally closed contact of the circuit
B07.BI_08
BI_52b
BI_52a
Sig_MCB_VTS
Ctrl.In_EnCtrl
Ctrl.In_Unblock
Ctrl1.In_ManOpn
Ctrl1.In_ManCls
Ctrl1.In_ManSynChk
Ctrl1.In_ManDdChk
10
BI_LowPres_Trp
11
BI_LowPres_Cls
12
50BF.In_Init
13
BI_RstTarg
B07.BI_04
14
Alm_Maintenance
B07.BI_06
15
BI_TrigDFR
16
27P1.OnLoad
17
27P2.OnLoad
18
50/51P1.En1
19
50/51P1.Blk
20
50/51P2.En1
21
50/51P2.Blk
22
50/51P3.En1
23
50/51P3.Blk
24
50/51P4.En1
25
50/51P4.Blk
26
50/51Q1.En1
27
50/51Q1.Blk
28
50/51Q2.En1
breaker
The binary input of the auxiliary normally opened contact of the circuit
breaker
B07.BI_09
The binary signal for inputting the state of the VTs miniature circuit
breaker
B07.BI_03
B07.BI_07
The binary signal for inputting the system on load state of the stage 1
undervoltage protection
The binary signal for inputting the system on load state of the stage 2
undervoltage protection
9-2
9 Configurable Function
29
50/51Q2.Blk
30
50/51G1.En1
31
50/51G1.Blk
32
50/51G2.En1
33
50/51G2.Blk
34
50/51G3.En1
35
50/51G3.Blk
36
50/51G4.En1
37
50/51G4.Blk
38
A.50/51G1.En1
39
A.50/51G1.Blk
40
A.50/51G2.En1
41
A.50/51G2.Blk
42
A.50/51G3.En1
43
A.50/51G3.Blk
44
A.50/51G4.En1
45
A.50/51G4.Blk
46
50/51SEF1.En1
47
50/51SEF1.Blk
48
50/51SEF2.En1
49
50/51SEF2.Blk
50
50/51SEF3.En1
9 Configurable Function
The binary signal for blocking the stage 3 sensitive earth fault
51
50/51SEF3.Blk
52
50/51SEF4.En1
53
50/51SEF4.Blk
54
50BC.En1
55
50BC.Blk
56
50BF.En1
57
50BF.Blk
58
50PSOTF.En1
59
50PSOTF.Blk
60
50GSOTF.En1
61
50GSOTF.Blk
62
49.En1
63
49.Blk
64
49.Clr
The binary signal for clearing the heat of thermal overload protection
65
59P1.En1
66
59P1.Blk
67
59P2.En1
68
59P2.Blk
69
27P1.En1
70
27P1.Blk
71
27P2.En1
72
27P2.Blk
73
59Q.En1
74
59Q.Blk
75
59G1.En1
76
59G1.Blk
77
59G2.En1
78
59G2.Blk
79
81U1.En1
80
81U1.Blk
81
81U2.En1
82
81U2.Blk
protection
The binary signal for enabling the stage 4 sensitive earth fault
protection
The binary signal for blocking the stage 4 sensitive earth fault
protection
The binary signal for enabling the zero sequence SOTF overcurrent
protection
The binary signal for blocking the zero sequence SOTF overcurrent
protection
9-4
9 Configurable Function
83
81U3.En1
84
81U3.Blk
85
81U4.En1
86
81U4.Blk
87
81O1.En1
88
81O1.Blk
89
81O2.En1
90
81O2.Blk
91
81O3.En1
92
81O3.Blk
93
81O4.En1
94
81O4.Blk
95
81R1.En1
96
81R1.Blk
97
81R2.En1
98
81R2.Blk
99
81R3.En1
100
81R3.Blk
101
81R4.En1
102
81R4.Blk
103
79.En1
104
79.Blk
105
CLP.En1
The binary signal for enabling the cold load pickup function
106
CLP.Blk
The binary signal for blocking the cold load pickup function
107
CLP.ShortRst
108
CLP.Init
109
MR1.En1
110
MR1.Blk
111
MR2.En1
112
MR2.Blk
113
MR3.En1
114
MR3.Blk
115
MR4.En1
116
MR4.Blk
117
50DZ.En1
9-5
9 Configurable Function
118
50DZ.Blk
119
37.En1
120
37.Blk
121
Sig_Spare01
122
Sig_Spare02
123
Sig_Spare03
124
Sig_Spare04
125
Sig_Spare05
126
Sig_Spare06
127
Sig_Spare07
128
Sig_Spare08
129
Alm_Spare01
130
Alm_Spare02
131
Alm_Spare03
132
Alm_Spare04
133
Alm_Spare05
134
Alm_Spare06
135
Alm_Spare07
136
Alm_Spare08
137
Switch1.in_52b
138
Switch1.in_52a
139
Switch2.in_52b
140
Switch2.in_52a
141
Switch3.in_52b
142
Switch3.in_52a
143
Switch4.in_52b
144
Switch4.in_52a
145
Interlock1.In_Opn
146
Interlock1.In_Cls
147
Interlock2.In_Opn
148
Interlock2.In_Cls
149
Interlock3.In_Opn
150
Interlock3.In_Cls
151
Interlock4.In_Opn
152
Interlock4.In_Cls
153
Interlock5.In_Opn
154
Interlock5.In_Cls
155
BI_ChgSGin_sg1
156
BI_ChgSGin_sg2
157
BI_ChgSGin_sg3
158
BI_ChgSGin_sg4
9-6
9 Configurable Function
Output Signal
Description
FD.Pkp
50/51P1.St
50/51P1.Op
50/51P2.St
50/51P2.Op
50/51P3.St
50/51P3.Op
50/51P4.St
50/51P4.Op
10
50/51Q1.St
11
50/51Q1.Op
12
50/51Q2.St
13
50/51Q2.Op
14
50/51G1.St
15
50/51G1.Op
16
50/51G2.St
17
50/51G2.Op
18
50/51G3.St
19
50/51G3.Op
20
50/51G4.St
21
50/51G4.Op
22
A.50/51G1.St
23
A.50/51G1.Op
24
A.50/51G2.St
25
A.50/51G2.Op
26
A.50/51G3.St
27
A.50/51G3.Op
28
A.50/51G4.St
29
A.50/51G4.Op
30
50/51SEF1.St
31
50/51SEF1.Op
32
50/51SEF2.St
33
50/51SEF2.Op
34
50/51SEF3.St
35
50/51SEF3.Op
36
50/51SEF4.St
37
50/51SEF4.Op
38
50BF.St
39
50BF.ReTrp
9-7
9 Configurable Function
40
50BF.Op
41
50BC.St
42
50BC.Op
43
50PSOTF.St
44
50PSOTF.Op
45
50GSOTF.St
46
50GSOTF.Op
47
49.St
48
49.Op
49
27P1.St
50
27P1.Op
51
27P2.St
52
27P2.Op
53
59P1.St
54
59P1.Op
55
59P2.St
56
59P2.Op
57
59Q.St
58
59Q.Op
59
59G1.St
60
59G1.Op
61
59G2.St
62
59G2.Op
63
81U1.St
64
81U1.Op
65
81U2.St
66
81U2.Op
67
81U3.St
68
81U3.Op
69
81U4.St
70
81U4.Op
71
81O1.St
72
81O1.Op
73
81O2.St
74
81O2.Op
75
81O3.St
76
81O3.Op
77
81O4.St
78
81O4.Op
79
81R1.St
80
81R1.Op
81
81R2.St
82
81R2.Op
9-8
9 Configurable Function
83
81R3.St
84
81R3.Op
85
81R4.St
86
81R4.Op
87
79.InProg
88
79.Close
89
79.Close_3PS1
90
79.Close_3PS2
91
79.Close_3PS3
92
79.Close_3PS4
93
79.Active
94
79.Ready
95
79.Fail
96
79.Reset
97
MR1.St
98
MR1.Op
99
MR2.St
100
MR2.Op
101
MR3.St
102
MR3.Op
103
MR4.St
104
MR4.Op
105
50DZ.St
106
50DZ.Op
107
37.St
108
37.Op
109
Ctrl1.Opn
110
Ctrl1.Cls
111
Ctrl2.Opn
112
Ctrl2.Cls
113
Ctrl3.Opn
114
Ctrl3.Cls
115
Ctrl4.Opn
116
Ctrl4.Cls
117
Ctrl5.Opn
118
Ctrl5.Cls
119
Alm_Device
120
Alm_52b
121
VTS.Alm_SynVT
122
VTS.Alm
123
CTS.Alm
124
49.Alm
125
Alm_CommTest
9 Configurable Function
126
Alm_TimeSync
127
Alm_Maintenance
128
Alm_LowPres_Trp
129
Alm_LowPres_Cls
130
B07.BI_01
131
B07.BI_02
132
B07.BI_03
133
B07.BI_04
134
B07.BI_05
135
B07.BI_06
136
B07.BI_07
137
B07.BI_08
138
B07.BI_09
139
B07.BI_10
140
B07.BI_11
141
B07.BI_12
142
B07.BI_13
143
B07.BI_14
144
B07.BI_15
145
B07.BI_16
146
B07.BI_17
147
B07.BI_18
148
B07.BI_19
149
CLP.St
150
25M.Ok_SynChk
151
25M.Ok_DdChk
152
25A.Ok_SynChk
153
25A.Ok_DdChk
154
VTS.InstAlm
155
CTS.InstAlm
156
Prot.OnLoad
157
Breaker.Dpos
158
Switch1.Dpos
159
Switch2.Dpos
160
Switch3.Dpos
161
Switch4.Dpos
Description
Open state: 0
9-10
Close state: 0
9 Configurable Function
0x40
Open state: 1
Close state: 0
0x80
Open state: 0
Close state: 1
0xC0
Open state: 1
Close state: 1
LED
Description
Default
LED_01
HEALTHY
LED_02
ALARM
LED_03
TRIP
LED_04
RECLOSE
LED_05
CB OPEN
LED_06
CB CLOSE
LED_07
Alm_Maintenance
LED_08
Alm_Maintenance
LED_09
Alm_Maintenance
10
LED_10
Alm_Maintenance
11
LED_11
Alm_Maintenance
12
LED_12
Alm_Maintenance
13
LED_13
Alm_Maintenance
14
LED_14
Alm_Maintenance
15
LED_15
Alm_Maintenance
16
LED_16
Alm_Maintenance
17
LED_17
Alm_Maintenance
18
LED_18
Alm_Maintenance
19
LED_19
Alm_Maintenance
20
LED_20
Alm_Maintenance
Binary Input
Description
Default
B07.BI_01
B07.BI_02
B07.BI_03
Ctrl.In_EnCtrl
B07.BI_04
BI_RstTarg
B07.BI_05
79.Blk
B07.BI_06
Alm_Maintenance
B07.BI_07
BI_LowPres_Cls
B07.BI_08
BI_52b
B07.BI_09
BI_52a
10
B07.BI_10
11
B07.BI_11
9 Configurable Function
12
B07.BI_12
13
B07.BI_13
14
B07.BI_14
15
B07.BI_15
16
B07.BI_16
17
B07.BI_17
18
B07.BI_18
19
B07.BI_19
Binary Output
Description
Default
B06.BO_07
Alm_Maintenance
B06.BO_08
Alm_Maintenance
B06.BO_09
Alm_Maintenance
B06.BO_10
Alm_Maintenance
B06.BO_11
Alm_Maintenance
NOTE! Other configurable binary outputs which are not listed in above table only can be
configured through the setting [XXXX.OutMap] (XXXX is the abbreviation of a protective
element, such as 50/51P1, 50/51G1, 59P1 etc.) of each function element. For more
details about these settings, please see Chapter 7.
9-12
10 Communication
10 Communication
Table of Contents
10.1 General ..........................................................................................................10-1
10.2 Rear Communication Port Information.......................................................10-1
10.2.1 RS-485 Interface............................................................................................................ 10-1
10.2.2 Ethernet Interface .......................................................................................................... 10-3
10.2.3 IEC60870-5-103 Communication................................................................................... 10-4
10.2.4 IEC61850 Communication ............................................................................................. 10-4
10.2.5 DNP3.0 Communication ................................................................................................ 10-4
10 Communication
List of Figures
Figure 10.2-1 EIA RS-485 bus connection arrangements ....................................................10-2
Figure 10.2-2 Format of IP and submask address ................................................................10-3
Figure 10.2-3 Ethernet communication cable .......................................................................10-3
Figure 10.2-4 Ethernet communication structure .................................................................10-4
10-b
10 Communication
10.1 General
This section outlines the remote data communication interfaces of this relay. The relay can support
several protocols: IEC60870-5-103, IEC61850 and DNP3.0. Setting the relevant communication
parameter can select the expected protocol (see Section 7.6).
The EIA RS-485 standardized interfaces are isolated, as well as the Ethernet interfaces, and are
suitable for permanent connection whichever protocol is selected. The advantage of this type of
connection is that up to 32 relays can be daisy chained together using a simple twisted pair
electrical connection.
It should be noted that the descriptions contained within this section do not aim to fully detail the
protocol itself. The relevant documentation for the protocol should be referred to for this
information. This section serves to describe the specific implementation of the protocol in the relay.
10-1
EIA RS-485
10 Communication
10-2
10 Communication
It is extremely important that the 120 termination resistors are fitted. Failure to do so will
result in an excessive bias voltage that may damage the devices connected to the bus.
As the field voltage is much higher than that required, NR can not assume responsibility for
any damage that may occur to a device connected to the network as a result of incorrect
application of this voltage.
Ensure that the field voltage is not being used for other purposes (i.e. powering logic inputs)
as this may cause noise to be passed to the communication network.
Where:
z
The network communication address for IEC60087-5-103 has above relationship described as an
equation with section 3 and section 4 of the IP address.
10.2.2.2 Ethernet Standardized Communication Cable
It is recommended to use 4-pair screened twisted category 5E cable as the communication cable.
A picture is shown below.
10 Communication
10-4
10 Communication
10.3.2 Initialization
Whenever the relay has been powered up, or if the communication parameters have been
changed, a reset command is required to initialize the communications. The relay will respond to
either of the two reset commands (Reset CU or Reset FCB), the difference is that the Reset CU
will clear any unsent messages in the relays transmit buffer.
The relay will respond to the reset command with an identification message ASDU 5, the COT
(Cause Of Transmission) of this response will be either Reset CU or Reset FCB depending on the
nature of the reset command.
In addition to the above identification message, if the relay has been powered up it will also
produce a power up event.
ASDU 1, time-tagged message: alarm messages, special purpose binary input state change
messages.
10-5
10 Communication
ASDU 2, time-tagged message with relative time: tripping messages and fault detector pickup
messages.
ASDU 40, single point information: general binary input state change messages.
ASDU 41, single point information with time-tagged: sequence of event (SOE) messages.
FUN
INF
DCC
Function
ASDU 64
48
0x81
ASDU 64
48
0x82
ASDU 64
48
0x01
ASDU 64
48
0x02
ASDU 64
48
0xC1
ASDU 64
48
0xC2
If the relay receives one of the command messages correctly, it will respond with an ACK message,
and then send a message which has the same ASDU data with the control direction message in
the next communication turn.
10-6
10 Communication
Semantics
240
241
243
244
245
248
Write entry
249
250
251
Semantics
240
241
243
244
245
249
250
251
IEC61850-2:
Glossary
IEC61850-3:
General requirements
10-7
10 Communication
IEC61850-4:
IEC61850-5:
IEC61850-6:
IEC61850-7-1:
Basic communication structure for substation and feeder equipment Principles and models
IEC61850-7-2:
IEC61850-7-3:
IEC61850-7-4:
IEC61850-8-1:
IEC61850-9-1:
IEC61850-9-2:
IEC61850-10:
Conformance testing
These documents can be obtained from the IEC (http://www.iec.ch). It is strongly recommended
that all those involved with any IEC61850 implementation obtain this document set.
10 Communication
10-9
10 Communication
MMXU.MX.TotW:
MMXU.MX.TotVAr:
MMXU.MX.TotPF:
MMXU.MX.Hz:
frequency
MMXU.MX.PPV.phsAB:
MMXU.MX.PPV.phsBC:
MMXU.MX.PPV.phsCA:
MMXU.MX.PhV.phsA:
MMXU.MX.PhV.phsB:
MMXU.MX.PhV.phsC:
MMXU.MX.A.phsA:
MMXU.MX.A.phsB:
MMXU.MX.A.phsC:
MMXU.MX.A.neut:
PTUV:
PTUF:
PTOV:
RBRF:
RREC:
The protection elements listed above contain start (pickup) and operate flags, instead of any
element has its own start (pickup) flag separately, all the elements share a common start (pickup)
flags PTRC.ST.Str.general in a PCS-9600 series relay. The operate flag for PTOC1 is
PTOC1.ST.Op.general. For the PCS-9600 series relay protection elements, these flags take their
values from related module for the corresponding element. Similar to digital status values, the
protection trip information is reported via BRCB, and it also locates in LLN0.
10.4.3.4 LLN0 and Other Logical Nodes
Logical node LLN0 is essential for an IEC61850 based IED. This LN shall be used to address
common issues for Logical Devices. In PCS-9600 series relays, most of the public services, the
10-10
10 Communication
common settings, control values and some device oriented data objects are available here. The
public services may be BRCB, URCB and GSE control blocks and similar global defines for the
whole device; the common settings (the logic nodes LPHDPTRC also contain some related
common settings) include all the setting items of communication settings. System settings and
some of the protection setting items, which can be configured to two or more protection elements
(logical nodes). In LLN0, the item Loc is a device control object, this Do item indicates the local
operation for complete logical device, when it is true, all the remote control commands to the IED
will be blocked and those commands make effective until the item Loc is changed to false. Besides
the logical nodes we describe above, there are some other logical nodes below in the IEDs:
MMUX:
LPHD:
PTRC:
RDRE:
GAPC:
CSWI:
XCBR:
This LN shall be used to acquire values from CTs and VTs and calculate measurands
such as RMS values for current and voltage or power flows out of the acquired voltage
and current samples. These values are normally used for operational purposes such as
power flow supervision and management, screen displays, state estimation, etc. The
requested accuracy for these functions has to be provided.
Physical device information, the logical node to model common issues for physical
device.
Protection trip conditioning, it shall be used to connect the operate outputs of one or
more protection functions to a common trip to be transmitted to XCBR. In addition or
alternatively, any combination of operate outputs of protection functions may be
combined to a new operate of PTRC.
Disturbance recorder function. It triggers the fault wave recorder and its output refers to
the IEEE Standard Format for Transient Data Exchange (COMTRADE) for Power
System (IEC60255-24). All enabled channels are included in the recording,
independently of the trigger mode.
Generic automatic process control, it is used to model in a generic way the
processing/automation of functions, for example the sequence control functions for
PCS-9600 series relays.
Switch controller. This class is used to control all switching conditions of XCBR and
XSWI. A remote switching command (for example select-before-operate) arrives here
firstly.
Breaker control. The XCBR logical node is directly associated with the breaker control
feature.
XCBR1.ST.Pos:
This is the position of the breaker. If the breaker control logic
indicates that the breaker, or any single pole of the breaker, is
closed, then the breaker position state is on. If the breaker
control logic indicates that the breaker is open, then the breaker
position state is off.
XCBR1.ST.BlkOpn: This is the state of the block open command logic. When true,
breaker open commands from IEC61850 clients will be rejected.
XCBR1.ST.BlkCls: This is the state of the block close command logic. When true,
breaker close commands from IEC61850 clients will be rejected.
XCBR1.CO.Pos:
This is where IEC61850 clients can issue open or close
commands to the breaker. SBO control with normal enhanced
security is the only supported IEC61850 control model.
10-11
10 Communication
10 Communication
2.
3.
2.
3.
10-13
10 Communication
Services
Client
Server
PCS-9600 Series
C1
C1
Client-Server Roles
B11
B12
Server
side
(of
Two-party
Application-Association)
Client
side
(of
Two-party
Application-Association)
SCSMS Supported
B21
B22
B23
B24
SCSM: other
Publisher side
B32
Subscriber side
Publisher side
B42
Subscriber side
NOTE!
C1: Shall be M if support for LOGICAL-DEVICE model has been declared
O: Optional
M: Mandatory
Y: Supported by PCS-9600 series relays
N: Currently not supported by PCS-9600 series relays
10.4.5.2 ACSI Models Conformance Statement
Services
Client
Server
PCS-9600 Series
M1
Logical device
C2
C2
M2
Logical node
C3
C3
M3
Data
C4
C4
M4
Data set
C5
C5
M5
Substitution
M6
Reporting
M7
M7-1
sequence-number
M7-2
report-time-stamp
M7-3
reason-for-inclusion
M7-4
data-set-name
M7-5
data-reference
M7-6
buffer-overflow
M7-7
entryID
10-14
10 Communication
M7-8
BufTm
M7-9
IntgPd
M7-10
GI
M8
M8-1
sequence-number
M8-2
report-time-stamp
M8-3
reason-for-inclusion
M8-4
data-set-name
M8-5
data-reference
M8-6
BufTm
M8-7
IntgPd
Log control
IntgPd
Log
M12
GOOSE
M13
GSSE
M14
Multicast SVC
M15
Unicast SVC
M16
Time
M17
File transfer
Logging
M9
M9-1
M10
GSE
NOTE!
C2: Shall be M if support for LOGICAL-NODE model has been declared
C3: Shall be M if support for DATA model has been declared
C4: Shall be M if support for DATA-SET, Substitution, Report, Log Control, or Time models
has been declared
C5: Shall be M if support for Report, GSE, or SMV models has been declared
M: Mandatory
Y: Supported by PCS-9600 series relays
N: Currently not supported by PCS-9600 series relays
10.4.5.3 ACSI Services Conformance Statement
Services
Server/Publisher
PCS-9600 Series
Server
S1
ServerDirectory
Application association
S2
Associate
S3
Abort
S4
Release
Logical device
10-15
10 Communication
S5
LogicalDeviceDirectory
Logical node
S6
LogicalNodeDirectory
S7
GetAllDataValues
S8
GetDataValues
S9
SetDataValues
S10
GetDataDirectory
S11
GetDataDefinition
S12
GetDataSetValues
S13
SetDataSetValues
S14
CreateDataSet
S15
DeleteDataSet
S16
GetDataSetDirectory
Data
Data set
Substitution
S17
SetDataValues
SelectActiveSG
M/O
S19
SelectEditSG
M/O
S20
SetSGValuess
M/O
S21
ConfirmEditSGValues
M/O
S22
GetSGValues
M/O
S23
GetSGCBValues
M/O
C6
Reporting
Buffered report control block
S24
Report
S24-1
data-change
S24-2
qchg-change
S24-3
data-update
S25
GetBRCBValues
C6
S26
SetBRCBValues
C6
C6
Report
S27-1
data-change
S27-2
qchg-change
S27-3
data-update
S28
GetURCBValues
C6
S29
SetURCBValues
C6
Logging
Log control block
S30
GetLCBValues
S31
SetLCBValues
10-16
10 Communication
Log
S32
QueryLogByTime
S33
QueryLogAfter
S34
GetLogStatusValues
SendGOOSEMessage
C8
S36
GetGoReference
C9
S37
GetGOOSEElementNumber
C9
S38
GetGoCBValues
S39
SetGoCBValuess
SendMSVMessage
C10
S46
GetMSVCBValues
S47
SetMSVCBValues
Unicast SVC
S48
SendUSVMessage
C10
S49
GetUSVCBValues
S50
SetUSVCBValues
S51
Select
S52
SelectWithValue
S53
Cancel
S54
Operate
S55
Command-Termination
S56
TimeActivated-Operate
Control
File transfer
S57
GetFile
M/O
S58
SetFile
S59
DeleteFile
S60
GetFileAttributeValues
M/O
Time
SNTP
NOTE!
C6: Shall declare support for at least one (BRCB or URCB)
C7: Shall declare support for at least one (QueryLogByTime or QueryLogAfter)
C8: Shall declare support for at least one (SendGOOSEMessage or SendGSSEMessage)
C9: Shall declare support if TP association is available
C10: Shall declare support for at least one (SendMSVMessage or SendUSVMessage)
10-17
10 Communication
PCS-9600 Series
YES
YES
PDIF: Differential
PDIR: Direction comparison
YES
PDIS: Distance
PDOP: Directional overpower
YES
YES
YES
YES
PTOF: Overfrequency
YES
PTOV: Overvoltage
YES
YES
YES
PTUC: Undercurrent
PTUV: Undervoltage
YES
YES
PTUF: Underfrequency
PVOC: Voltage controlled time overcurrent
10-18
10 Communication
RADR: Disturbance recorder channel analogue
YES
YES
YES
RREC: Autoreclosing
YES
YES
YES
CILO: Interlocking
CPOW: Point-on-wave switching
YES
YES
YES
YES
YES
YES
MMTR: Metering
YES
YES
MMXU: Measurement
YES
YES
10-19
10 Communication
T: Logical Nodes For Switchgear
TCTR: Current transformer
YES
YES
YES
ZBAT: Battery
ZBSH: Bushing
ZCON: Converter
ZGEN: Generator
ZMOT: Motor
ZREA: Reactor
10-20
10 Communication
2.
3.
Function Code
Object
Variation
Qualifier
Master
0x17
Slave
0x81
0x34
0x02
0x07
Master/Slave
Function Code
Object
Variation
Qualifier
Master
0x01
0x34
0x00, 0x01
0x07
Slave
0x81
0x32
0x01
0x07
Master/Slave
Function Code
Object
Variation
Qualifier
Master
0x02
0x32
0x01
0x00,0x01,0x07,0x08
Slave
0x81
2.
Function Code
Object
Variation
Qualifier
Master
0x02
0x50
0x01
0x00, 0x01
Slave
0x81
2.
Supported qualifiers
Master Qualifier
0x00
0x01
0x06
0x07
0x08
Slave Qualifier
0x00
0x01
0x01
0x07
0x08
Master Variation
0x00
0x01
0x02
Slave Variation
0x02
0x01
0x02
The protection operation signals, alarm signals and binary input state change signals are
transported respectively according to the variation sequence in above table.
z
Object 2, SOE
10-21
10 Communication
Master Variation
0x00
0x01
0x02
0x03
Slave Variation
0x02
0x01
0x02
0x03
If the master qualifier is 0x07, the slave responsive qualifier is 0x27; and if the master
qualifier is 0x01, 0x06 or 0x08, the slave responsive qualifier is 0x28.
z
Master Variation
0x00
0x01
0x02
0x03
0x04
Slave Variation
0x01
0x01
0x02
0x03
0x04
The measurement values are transported firstly, and then the protection measurement values
are transported.
z
Master Variation
0x00
0x01
0x02
Slave Variation
0x01
0x01
0x02
3.
4.
5.
10-22
10 Communication
Master Qualifier
0x17
0x27
0x18
0x28
Slave Qualifier
0x17
0x27
0x18
0x28
0x01
Slave Variation
0x01
Control Code
0x01: closing
0x10: tripping
10-23
10 Communication
10-24
11 Installation
11 Installation
Table of Contents
11.1 General ..........................................................................................................11-1
11.2 Safety Instructions .......................................................................................11-1
11.3 Checking the Shipment................................................................................11-2
11.4 Material and Tools Required ........................................................................11-2
11.5 Device Location and Ambient Conditions ..................................................11-2
11.6 Mechanical Installation ................................................................................11-3
11.7 Electrical Installation and Wiring ................................................................11-4
11.7.1 Grounding Guidelines .....................................................................................................11-4
11.7.2 Cubicle Grounding ..........................................................................................................11-4
11.7.3 Ground Connection on the Device ..................................................................................11-5
11.7.4 Grounding Strips and their Installation ............................................................................11-6
11.7.5 Guidelines for Wiring.......................................................................................................11-6
11.7.6 Wiring for Electrical Cables .............................................................................................11-7
List of Figures
Figure 11.6-1 Dimensions of this relay and the cut-out in the cubicle (unit: mm) .............11-3
Figure 11.6-2 Demonstration of plugging a board into its corresponding slot ..................11-4
Figure 11.7-1 Cubicle grounding system ...............................................................................11-5
Figure 11.7-2 Ground terminal of this relay ...........................................................................11-6
Figure 11.7-3 Ground strip and termination ..........................................................................11-6
Figure 11.7-4 Glancing demo about the wiring for electrical cables ...................................11-7
Figure 11.8-1 Control panel (button, switch and link) of the cubicle...................................11-7
Figure 11.8-2 Typical wiring diagram of this relay ................................................................11-8
11-a
11 Installation
11-b
11 Installation
11.1 General
The equipment must be shipped, stored and installed with the greatest care.
Choose the place of installation such that the communication interface and the controls on the
front of the device are easily accessible.
Air must circulate freely around the equipment. Observe all the requirements regarding place of
installation and ambient conditions given in this instruction manual.
Take care that the external wiring is properly brought into the equipment and terminated correctly
and pay special attention to grounding. Strictly observe the corresponding guidelines contained in
this section.
WARNING! The modules may only be inserted in the slots designated in Section 6.2.
Components can be damaged or destroyed by inserting boards in the wrong slots.
DANGER! Improper handling of the equipment can cause damage or an incorrect
response of the equipment itself or the primary plant.
WARNING! Industry packs and ribbon cables may only be replaced or the positions of
jumpers be changed on a workbench appropriately designed for working on electronic
equipment. The modules, bus backplanes are sensitive to electrostatic discharge when
not in the unit's housing.
The basic precautions to guard against electrostatic discharge are as follows:
11-1
11 Installation
Should boards have to be removed from this relay installed in a grounded cubicle in an HV
switchgear installation, please discharge yourself by touching station ground (the cubicle)
beforehand.
Only hold electronic boards at the edges, taking care not to touch the components.
Only works on boards that have been removed from the cubicle on a workbench designed for
electronic equipment and wear a grounded wristband. Do not wear a grounded wristband,
however, while inserting or withdrawing units.
Always store and ship the electronic boards in their original packing. Place electronic parts in
electrostatic screened packing materials.
The location should not be exposed to excessive air pollution (dust, aggressive substances).
11-2
11 Installation
2.
Severe vibration, extreme changes of temperature, high levels of humidity, surge voltages of
high amplitude and short rise time and strong induced magnetic fields should be avoided as
far as possible.
3.
The equipment can in principle be mounted in any attitude, but it is normally mounted vertically
(visibility of markings).
WARNING! Excessively high temperature can appreciably reduce the operating life of
this relay.
Figure 11.6-1 Dimensions of this relay and the cut-out in the cubicle (unit: mm)
NOTE! It is necessary to leave enough space top and bottom of the cut-out in the cubicle
for heat emission of this relay.
As mentioned in Chapter 6, up to eight modules are installed in the enclosure of this relay, and
11-3
11 Installation
these modules must be plugged into the proper slots of this relay respectively. The safety
instructions must be abided by when installing the boards, please see Section 11.2 for the details.
Figure 11.6-2 shows the installation way of a module being plugged into a corresponding slot.
In the case of equipment supplied in cubicles, place the cubicles on the foundations that have
been prepared. Take care while doing so not to jam or otherwise damage any of the cables that
have already been installed. Secure the cubicles to the foundations.
11 Installation
11 Installation
Power supply, binary inputs & outputs: brained copper cable, 1.5mm2 ~ 2.5mm2
11-6
11 Installation
01
02
03
04
05
06
07
08
Tighten
01
Figure 11.7-4 Glancing demo about the wiring for electrical cables
DANGER! Never allow the current transformer (CT) secondary circuit connected to this
equipment to be opened while the primary system is live. Opening the CT circuit will
produce a dangerously high voltage.
Figure 11.8-1 Control panel (button, switch and link) of the cubicle
The typical wiring of this relay is shown as below, all the configurable binary inputs and binary
11-7
11 Installation
A
B
C
05
Ux
06
Uxn
01
Ua
02
Ub
03
Uc
04
Un
Voltage Inputs
07
U0
08
U0n
09
10 11
I02 I02n Ia
12
Ian
13
Ib
14
Ibn
15
Ic
16
Icn
17
18
19
20
21
22
23
24
25
26
I01 I01n I0s I0sn Iam Iamn Ibm Ibmn Icm Icmn
For Protection
For Metering
Current Inputs
NR4412
Ethernet 1
Ground at
Remote
device
Ethernet 2
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
Power
Supply
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
A
B
SGND
A
B
SGND
SYN+
SYNSGND
RTS
TXD
SGND
NET1
NET2
NET3
NET4
NET5
NET6
RX
GPS
SIG_COM
BO_Alm_Fail
BO_Alm_Abnor
TX1
BO_01
RX1
BI_01+
BI_01BI_02+
BI_02BI_03
BI_04
BI_05
BI_06
BI_07
BI_08
BI_09
BI_10
BI_11
BI_12
BI_13
BI_14
BI_15
BI_16
BI_17
BI_18
BI_19
BI_Opto-
BO_01
BO_02
BO_03
BO_02
TX2
BO_04
BO_03
BO_04
RX2
BO_05
BO_06
BO_05
TX3
BO_07
BO_06
RX3
BO_08
BO_07
BO_09
BO_08
TX4
PSW+
PSWGND
RX4
BO_10
BO_11
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
11-8
12 Commissioning
12 Commissioning
Table of Contents
12.1 General ..........................................................................................................12-1
12.2 Safety Instructions .......................................................................................12-1
12.3 Commission Tools........................................................................................12-2
12.4 Setting Familiarization .................................................................................12-2
12.5 Product Checks ............................................................................................12-3
12.5.1 With the Relay De-energized ......................................................................................... 12-4
12.5.2 With the Relay Energized .............................................................................................. 12-5
12.5.3 Protective Function Test................................................................................................. 12-8
12.5.4 On-load Checks ........................................................................................................... 12-18
12-a
12 Commissioning
12-b
12 Commissioning
12.1 General
This relay is fully numerical in their design, implementing all protection and non-protection
functions in software. The relay employs a high degree of self-checking and in the unlikely event of
a failure, will give an alarm. As a result of this, the commissioning test does not need to be as
extensive as with non-numeric electronic or electro-mechanical relays.
To commission numerical relays, it is only necessary to verify that the hardware is functioning
correctly and the application-specific software settings have been applied to the relay.
Blank commissioning test and setting records are provided at the end of this manual for
completion as required.
Before carrying out any work on the equipment, the user should be familiar with the contents of the
safety and technical data sections and the ratings on the equipments rating label.
The earthing screw of the device must be connected solidly to the protective earth conductor
before any other electrical connection is made.
Hazardous voltages can be present on all circuits and components connected to the supply
voltage or to the measuring and test quantities.
Hazardous voltages can be present in the device even after disconnection of the supply
voltage (storage capacitors!)
The limit values stated in the technical data (Chapter 2) must not be exceeded at all, not even
during testing and commissioning.
When testing the device with secondary test equipment, make sure that no other
measurement quantities are connected. Take also into consideration that the trip circuits and
maybe also close commands to the circuit breakers and other primary switches are
disconnected from the device unless expressly stated.
12-1
12 Commissioning
DANGER! Current transformer secondary circuits must have been short-circuited before
the current leads to the device are disconnected.
WARNING! Primary test may only be carried out by qualified personnel, who are familiar
with the commissioning of protection system, the operation of the plant and safety rules
and regulations (switching, earthing, etc.).
Multifunctional dynamic current and voltage injection test set with interval timer.
Multimeter with suitable AC current range and AC/DC voltage ranges of 0~440V and 0~250V
respectively.
Optional equipment:
z
An electronic or brushless insulation tester with a DC output not exceeding 500V (for
insulation resistance test when required).
A portable PC, with appropriate software (this enables the rear communications port to be
tested, if this is to be used, and will also save considerable time during commissioning).
EIA RS-485 to EIA RS-232 converter (if EIA RS-485 IEC60870-5-103 port is being tested).
12-2
12 Commissioning
Function tests
These tests are performed for the following functions that are fully software-based. Tests of the
protection schemes and fault locator require a dynamic test set.
z
Timers test
Conjunctive tests
The tests are performed after the relay is connected with the primary equipment and other
external equipment.
12-3
12 Commissioning
On load test.
Protection panel
Carefully examine the protection panel, protection equipment inside and other parts inside to
see that no physical damage has occurred since installation.
The rated information of other auxiliary protections should be checked to ensure it is correct
for the particular installation.
Panel wiring
Check the conducting wire which is used in the panel to assure that their cross section
meeting the requirement.
Carefully examine the wiring to see that they are no connection failure exists.
Label
Check all the isolator binary inputs, terminal blocks, indicators, switches and push buttons to
make sure that their labels meet the requirements of this project.
Earthing cable
Check whether the earthing cable from the panel terminal block is safely screwed to the panel
steel sheet.
12-4
12 Commissioning
DC power supply
12-5
12 Commissioning
12-6
12 Commissioning
Practical Input
Error
Ia
Ib
Ic
I01
I02
I0s
Practical Input
Error
Ua
Ub
Uc
U0
Ux
12 Commissioning
Correct?
To conclude that the primary function of the protection can trip according to the correct
application settings.
12-8
12 Commissioning
1.
Enable the stage 1 overcurrent protection with VCE and directional element control.
z
2.
3.
4.
Simulate a single-phase fault or multi-phase fault, the current of the fault phase is 1.05
[50/51P1.I_Set], and the protection voltages satisfy the VCE condition (see Section 3.3.3) and
forward directional control condition (see Section 3.3.4).
5.
After the period of [50/51P1.t_Op], the stage 1 overcurrent protection will operate and issue
the trip command. The TRIP LED indicator will be on; a relevant report will be shown on the
LCD.
6.
After the fault is disappeared, this relay will restore the stage 1 overcurrent protection
automatically. Restore the TRIP indicator and the LCD manually.
2.
3.
4.
Simulate a single-phase fault or multi-phase fault, and the current of the fault phase is 2
[50/51P4.I_Set].
5.
After the period of 13.5 [50/51P4.TMS] [50/51P4.t_Op], the IDMT overcurrent protection
will operate and issue the trip command. The TRIP LED indicator will be on; a relevant
report will be shown on the LCD.
6.
After the fault is disappeared, this relay will restore the IDMT protection automatically. Restore
the TRIP indicator and the LCD manually.
12-9
12 Commissioning
NOTE! The IDMT overcurrent protection with other characteristic inverse curves can be
checked through the same method. Note to set the relevant characteristic and logic
settings correctly.
12.5.3.4 Zero Sequence Overcurrent Protection Check
This check, performed the No.1 stage 1 zero sequence overcurrent protection function in the No.1
setting group, demonstrates that the relay is operating correctly at the application-specific settings.
1.
2.
3.
Simulate a normal condition, the external input current of the zero sequence CT is less than
0.95 [50/51G1.3I0_Set].
4.
Simulate a single-phase earth fault, the external input current of the zero sequence CT is
greater than 1.05 [50/51G1.3I0_Set].
5.
After the period of [50/51G1.t_Op], the No.1 stage 1 zero sequence overcurrent protection will
operate and issue the trip command. The TRIP LED indicator will be on; a relevant report
will be shown on the LCD.
6.
After the fault is disappeared, this relay will restore the No.1 stage 1 zero sequence
overcurrent protection automatically. Restore the TRIP indicator and the LCD manually.
NOTE! Another way for testing the zero sequence overcurrent protection is using the
self-calculated zero sequence current.
2.
3.
Simulate a normal condition, the external input current of the sensitive zero sequence CT is
12-10
12 Commissioning
Simulate a single-phase earth fault, the external input current of the zero sequence CT is
greater than 1.05 [50/51SEF1.3I0_Set].
5.
After the period of [50/51SEF1.t_Op], the stage 1 sensitive earth fault protection will operate
and issue the trip command. The TRIP LED indicator will be on; a relevant report will be
shown on the LCD.
6.
After the fault is disappeared, this relay will restore the stage 1 sensitive earth fault protection
automatically. Restore the TRIP indicator and the LCD manually.
2.
3.
Simulate a normal condition; the negative sequence current is less than 0.95
[50/51Q1.I2_Set].
4.
Simulate an unbalance fault; the negative sequence current is greater than 1.05
[50/51Q1.I2_Set].
5.
After the period of [50/51Q1.t_Op], the stage 1 negative sequence overcurrent protection will
operate and issue the trip command. The TRIP LED indicator will be on; a relevant report
will be shown on the LCD.
6.
After the fault is disappeared, this relay will restore the stage 1 negative sequence overcurrent
protection automatically. Restore the TRIP indicator and the LCD manually.
2.
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12 Commissioning
3.
Simulate a normal condition with normal protection voltages and currents, and the load
current is 0.5 [49.K_Trp] [49.Ib_Set].
4.
5.
After the period of about 0.223 [49.Tau], the definite time overload protection will operate
and issue the trip command. The TRIP LED indicator will be on; a relevant report will be
shown on the LCD.
6.
After the fault is disappeared, this relay will restore the thermal overload protection
automatically. Restore the TRIP indicator and the LCD manually.
2.
3.
4.
Simulate a system frequency decline condition. The input protection voltage is greater than
the setting [81.Upp_VCE].
5.
After the period of [81U1.t_Op], the stage 1 under-frequency protection will operate and issue
the trip command. The TRIP LED indicator will be on; a relevant report will be shown on the
LCD.
6.
After the fault is disappeared, this relay will restore the stage 1 under-frequency protection
automatically. Restore the TRIP indicator and the LCD manually.
12-12
12 Commissioning
2.
3.
Simulate a normal condition with normal protection voltages and the circuit breaker is closed.
4.
Simulate an undervoltage condition; anyone of the three phase-to-phase voltages is less than
0.95 [27P1.U_Set].
5.
After the period of [27P1.t_Op], the stage 1 undervoltage protection will operate and issue the
trip command. The TRIP LED indicator will be on; a relevant report will be shown on the
LCD.
6.
After the fault is disappeared, this relay will restore the stage 1 undervoltage protection
automatically. Restore the TRIP indicator and the LCD manually.
2.
3.
4.
5.
After the period of [59P1.t_Op], the stage 1 overvoltage protection will operate and issue the
trip command. The TRIP LED indicator will be on; a relevant report will be shown on the
LCD.
6.
After the fault is disappeared, this relay will restore the stage 1 overvoltage protection
automatically. Restore the TRIP indicator and the LCD manually.
12-13
12 Commissioning
2.
3.
Simulate a normal condition; the negative sequence voltage is less than 0.95 [59Q.U2_Set].
4.
Simulate an unbalance fault; the negative sequence voltage is greater than 1.05
[59Q.U2_Set].
5.
After the period of [59Q.t_Op], the negative sequence overvoltage protection will operate and
issue the trip command. The TRIP LED indicator will be on; a relevant report will be shown
on the LCD.
6.
After the fault is disappeared, this relay will restore the negative sequence overvoltage
protection automatically. Restore the TRIP indicator and the LCD manually.
2.
3.
4.
Simulate a broken conductor condition; the ratio I2/I1 is greater than 1.05 [50BC.I2/I1_Set].
5.
After the period of [50BC.t_Op], the broken conductor protection will operate and issue the trip
command. The TRIP LED indicator will be on; a relevant report will be shown on the LCD.
6.
After the fault is disappeared, this relay will restore the broken conductor protection
automatically. Restore the TRIP indicator and the LCD manually.
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12 Commissioning
2.
3.
Simulate a normal condition with normal protection voltages, currents and synchro-check
voltage, and the circuit breaker is closed. After a period of time delay, the auto-recloser is
ready and in service. A full charged battery sign is shown on the right bottom of the LCD.
4.
Make the stage 1 overcurrent protection operate according the method which is described in
Section 12.5.3.2.
5.
Just at the same time when the stage 1 overcurrent protection is operated, simulate a normal
condition with normal voltage inputs (protection and synchro-check) and without current
inputs, and the circuit breaker is opened. After the period of [79.t_3PS1], the auto-recloser will
operate, the RECLOSE LED indicator will be on; a relevant report will be shown on the LCD.
The auto-recloser with other check modes can be checked through the same method. Note to set
the relevant logic settings as 1. For the details about the auto-recloser theory, see Section 3.17.
12.5.3.14 SOTF Overcurrent Protection Check
This check, performed the SOTF overcurrent protection in No.1 setting group, demonstrates that
the relay is operating correctly at the application-specific settings.
1.
Enable the SOTF overcurrent protection. Do the following configuration on the base of the
setting configuration as described in Section 12.5.3.13.
z
2.
3.
Repeat the step 3 to step 5 as described in Section 12.5.3.13, and make the stage 1
overcurrent protection and the auto-recloser operate successfully.
4.
Simulate a single-phase fault or multi-phase fault, and the current of the fault phase is greater
than 1.05 [50PSOTF.I_Set], and the circuit breaker is closed at the same time.
12-15
12 Commissioning
5.
After the period of [50PSOTF.t_Op], the SOTF overcurrent protection will operate and issue
the trip command. The TRIP LED indicator will be on; a relevant report will be shown on the
LCD.
Enable the stage 1 breaker failure protection and the stage 1 overcurrent protection.
z
2.
3.
Simulate a normal condition with normal currents and the circuit breaker is closed.
4.
Make the stage 1 overcurrent protection operate according the method which is described in
Section 12.5.3.2.
5.
Make the fault phase current is greater than 1.05 [50BF.I_Set] and the circuit breaker is
closed.
6.
After the period of [50BF.t_ReTrp], the breaker failure protection will operate and issue the
re-trip command; and after the period of [50BF.t_Op], the breaker failure protection will
operate and issue the trip command. The TRIP LED indicator will be on; a relevant report
will be shown on the LCD.
7.
After the fault is disappeared, this relay will restore the breaker failure protection automatically.
Restore the TRIP indicator and the LCD manually.
12-16
12 Commissioning
2.
3.
4.
Energized the binary input which is defined as the input of the No.1 mechanical protection.
5.
After the period of [MR1.t_Op], the No.1 mechanical protection will operate and issue the trip
command. The TRIP LED indicator will be on; a relevant report will be shown on the LCD.
6.
After the signal of the No.1 mechanical protection is disappeared, this relay will restore the
No.1 mechanical protection automatically. Restore the TRIP indicator and the LCD
manually.
2.
3.
Simulate a fault condition, make the any of phase currents be greater than 1.05 [50DZ.I_Set]
and make the circuit breaker be opened.
4.
After the period of [50DZ.t_Op], the dead zone protection will operate and issue the trip
command. The TRIP LED indicator will be on; a relevant report will be shown on the LCD.
5.
After the fault is disappeared, this relay will restore the dead zone protection automatically.
Restore the TRIP indicator and the LCD manually.
12-17
12 Commissioning
2.
3.
Simulate a normal condition with normal currents and the circuit breaker is closed.
4.
Simulate a abnormal condition, make all three phase currents be less than the setting
[37.I_Set] and make the circuit breaker be closed.
5.
After the period of [37.t_Op], the undercurrent protection will operate and issue the trip
command. The TRIP LED indicator will be on; a relevant report will be shown on the LCD.
6.
After the fault is disappeared, this relay will restore the undercurrent protection automatically.
Restore the TRIP indicator and the LCD manually.
Confirm the external wiring to the current and voltage inputs is correct.
However, these checks can only be carried out if there are no restrictions preventing the
tenderization of the plant being protected.
Remove all test leads, temporary shorting leads, etc. and replace any external wiring that has
been removed to allow testing.
If it has been necessary to disconnect any of the external wiring from the protection in order to
perform any of the foregoing tests, it should be ensured that all connections are replaced in
accordance with the relevant external connection or scheme diagram. Confirm current and voltage
transformer wiring.
12.5.4.1 Final Checks
After the above tests are completed, remove all test or temporary shorting leads, etc. If it has been
necessary to disconnect any of the external wiring from the protection in order to perform the
wiring verification tests, it should be ensured that all connections are replaced in accordance with
the relevant external connection or scheme diagram.
Ensure that the protection has been restored to service.
If the protection is in a new installation or the circuit breaker has just been maintained, the circuit
breaker maintenance and current counters should be zero. If a test block is installed, remove the
test plug and replace the cover so that the protection is put into service.
Ensure that all event records, fault records, disturbance records and alarms have been cleared
and LEDs has been reset before leaving the protection.
12-18
13 Maintenance
13 Maintenance
Table of Contents
13.1 Maintenance Schedule.................................................................................13-1
13.2 Regular Testing.............................................................................................13-1
13.3 Failure Tracing and Repair ..........................................................................13-1
13.4 Replace Failed Modules...............................................................................13-1
13-a
13 Maintenance
13-b
13 Maintenance
13 Maintenance
removed module. Furthermore, the replaced module should have the same software version. And
the replaced analog input module and power supply module should have the same ratings.
WARNING! Units and modules may only be replaced while the supply is switched off and
only by appropriately trained and qualified personnel. Strictly observe the basic
precautions to guard against electrostatic discharge.
WARNING! When handling a module, take anti-static measures such as wearing an
earthed wrist band and placing modules on an earthed conductive mat. Otherwise, many
of the electronic components could suffer damage. After replacing the CPU module,
check the settings.
DANGER! After replacing modules, be sure to check that the same configuration is set as
before the replacement. If this is not the case, there is a danger of the unintended
operation of switchgear taking place or of protections not functioning correctly. Persons
may also be put in danger.
13-2
14-a
14-b
14.1 Decommissioning
14.1.1 Switching off
To switch off this relay, switch off the external miniature circuit breaker of the power supply.
14.1.3 Dismantling
The rack of this relay may now be removed from the system cubicle, after which the cubicles may
also be removed.
DANGER! When the station is in operation, make sure that there is an adequate safety
distance to live parts, especially as dismantling is often performed by unskilled personnel.
14.2 Disposal
In every country there are companies specialized in the proper disposal of electronic waste.
NOTE! Strictly observe all local and national regulations when disposing of the device.
14-1
14-2
Software
Source
New
Version
Beta
2.00
2.10
Date
2012-03-19
Description of change
Form the original manual.
15-1
15-2