INA103

I NA
103

I NA
103

Low Noise, Low Distortion

INSTRUMENTATION AMPLIFIER
FEATURES

APPLICATIONS

LOW NOISE: 1nV/Hz

LOW THD+N: 0.0009% at 1kHz, G = 100
HIGH GBW: 100MHz at G = 1000

HIGH QUALITY MICROPHONE PREAMPS

(REPLACES TRANSFORMERS)
MOVING-COIL PREAMPLIFIERS

WIDE SUPPLY RANGE: 9V to 25V

HIGH CMRR: >100dB
BUILT-IN GAIN SETTING RESISTORS:
G = 1, 100
UPGRADES AD625

DIFFERENTIAL RECEIVERS
AMPLIFICATION OF SIGNALS FROM:
Strain Gages (Weigh Scale Applications)
Thermocouples
Bridge Transducers

DESCRIPTION
The INA103 is a very low noise, low distortion monolithic instrumentation amplifier. Its current-feedback
circuitry achieves very wide bandwidth and excellent
dynamic response. It is ideal for low-level audio
signals such as balanced low-impedance microphones.
The INA103 provides near-theoretical limit noise performance for 200 source impedances. Many industrial applications also benefit from its low noise and
wide bandwidth.

The INA103 is available in 16-pin plastic DIP and

SOL-16 surface-mount packages. Commercial and Industrial temperature range models are available.

Unique distortion cancellation circuitry reduces distortion to extremely low levels, even in high gain. Its
balanced input, low noise and low distortion provide
superior performance compared to transformer-coupled
microphone amplifiers used in professional audio
equipment.
The INA103s wide supply voltage (9 to 25V) and
high output current drive allow its use in high-level
audio stages as well. A copper lead frame in the plastic
DIP assures excellent thermal performance.

Gain Drive
12
Input 16
Gain Sense 15

Offset Offset
Null
Null
3

6k

+
A1

3k

6k
11 Sense

RG 13

60.6
G = 100 14
+RG

+Gain Sense

+Input

3k
6k

A3

10

Output

Ref

6k

A2
+

+Gain Drive

V+

International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111 Twx: 910-952-1111
Internet: http://www.burr-brown.com/ FAXLine: (800) 548-6133 (US/Canada Only) Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132

SBOS003

1990 Burr-Brown Corporation

PDS-1016H
1

INA103

Printed in U.S.A. March, 1998

SPECIFICATIONS
All specifications at TA = +25C, VS = 15V and RL = 2k, unless otherwise noted.
INA103KP, KU
PARAMETER

CONDITIONS

GAIN
Range of Gain
Gain Equation (1)
Gain Error, DC G = 1
G = 100
Equation
Gain Temp. Co. G = 1
G = 100
Equation
Nonlinearity, DC G = 1
G = 100
OUTPUT
Voltage, RL = 600
RL = 600
Current
Short Circuit Current
Capacitive Load Stability
INPUT OFFSET VOLTAGE
Initial Offset RTI (3)
(KU Grade)
vs Temp G = 1 to 1000
G = 1000
vs Supply
INPUT BIAS CURRENT
Initial Bias Current
vs Temp
Initial Offset Current
vs Temp

MIN
1

G = 1 + 6k/RG
0.005
0.07
0.05
10
25
25
0.0003
0.0006

10V Output

10V Output

10V Output

11.5
20
40

TA = TMIN to TMAX
VS = 25, TA = 25C
TA = TMIN to TMAX

INPUT NOISE
Voltage (5)
10Hz
100Hz
1kHz
Current, 1kHz

MAX

UNITS

1000

V/V
V/V
%
%
%
ppm/C
ppm/C
ppm/C
% of FS(2)
% of FS

0.05
0.25

0.01
0.01

12
21

V
V
mA
mA
nF

70
10
(30 + 1200/G)
(250+ 5000/G)

TA = TMIN to TMAX
TA = TMIN to T MAX
9V to 25V

1 + 20/G

TA = TMIN to TMAX
TA = TMIN to TMAX

INPUT IMPEDANCE
Differential Mode
Common-Mode
INPUT VOLTAGE RANGE
Common-Mode Range (4)
CMR
G=1
G = 100

TYP

0.2 + 8/G

4 + 60/G

2.5
15
0.04
0.5

12
1

V
V
V/C
V/C
V/V
A
nA/C
A
nA/C

60 || 2
60 || 5

M || pF
M || pF

11

12

72
100

86
125

dB
dB

2
1.2
1
2

nV/Hz
nV/Hz
nV/Hz
pA/Hz

1kHz
20Hz-20kHz

65
100

nV/Hz
dBu

Small Signal
Small Signal
G=1

6
800

MHz
kHz

240
15
0.0009

kHz
V/s
%

VO = 20V Step

1.7
1.5

s
s

VO = 20V Step

2
3.5
1

s
s
s

DC to 60Hz
DC to 60Hz
RS = 0

OUTPUT NOISE
Voltage
A Weighted, 20Hz-20kHz
DYNAMIC RESPONSE
3dB Bandwidth: G = 1
G = 100
Full Power Bandwidth
VOUT = 10V, RL = 600
Slew Rate
THD + Noise
Settling Time 0.1%
G=1
G = 100
Settling Time 0.01%
G=1
G = 100
Overload Recovery (6)

G = 1 to 500
G = 100, f = 1kHz

50% Overdrive

NOTES: (1) Gains other than 1 and 100 can be set by adding an external resistor, RG between pins 2 and 15. Gain accuracy is a function of RG. (2) FS = Full Scale.
(3) Adjustable to zero. (4) VO = 0V, see Typical Curves for VCM vs VO. (5) VNOISE RTI = V2N INPUT + (VN OUTPUT/Gain)2 + 4KTRG. See Typical Curves. (6) Time required
for output to return from saturation to linear operation following the removal of an input overdrive voltage.

INA103

SPECIFICATIONS

(CONT)

All specifications at TA = +25C, VS = 15V and RL = 2k, unless otherwise noted.

INA103KP, KU
PARAMETER

CONDITIONS

MIN

POWER SUPPLY
Rated Voltage
Voltage Range
Quiescent Current

TYP
15
9

TEMPERATURE RANGE
Specification
Operation
Storage
Thermal Resistance, JA

0
40
40

Top View
(1)

16

Input

15

Gain Sense

+ Offset Null

14

G = 100

Offset Null

13

RG

+ Gain Drive

12

Gain Drive

+RG

11

Sense

Ref

10

Output

V+

+ Gain Sense

25
12.5

V
V
mA

+70
+85
+100

Any integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
ABSOLUTE MAXIMUM RATINGS(1)
Power Supply Voltage ....................................................................... 25V
Input Voltage Range, Continuous ....................................................... VS
Operating Temperature Range: ........................................ 40C to +85C
Storage Temperature Range: ........................................... 40C to +85C
Junction Temperature:
P, U Package .............................................................................. +125C
Lead Temperature (soldering, 10s) ............................................... +300C
Output Short Circuit to Common ............................................. Continuous

NOTE: (1) Pin 1 MarkingSOL-16 Package

PACKAGE/ORDERING INFORMATION

PRODUCT

PACKAGE

PACKAGE
DRAWING
NUMBER(1)

INA103KP
INA103KU

Plastic DIP
SOL-16

180
211

C
C
C
C/W

ELECTROSTATIC
DISCHARGE SENSITIVITY

DIP or SOIC
1

UNITS

100

PIN CONFIGURATION

+ Input

MAX

TEMPERATURE
RANGE
0C to +70C
0C to +70C

NOTE: (1) Stresses above these ratings may cause permanent damage.

NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

INA103

TYPICAL PERFORMANCE CURVES

At TA = +25C, VS = 15V, unless otherwise noted.

OUTPUT SWING vs SUPPLY

25

20

20
Output Voltage (V)

Input Voltage Range (V)

INPUT VOLTAGE RANGE vs SUPPLY

25

15

10

15

10

5
5

10

15

20

25

10

Power Supply Voltage (V)

MAX COMMON-MODE VOLTAGE

vs OUTPUT VOLTAGE

20

25

OUTPUT SWING vs LOAD RESISTANCE

22

16

16.5

V S = 25V

Output Voltage (V)

Common-Mode Voltage (V)

15

Power Supply Voltage (V)

11
V S = 15V
5.5

12

5.5

11

16.5

22

200

Output Voltage (V)

400

600

800

1k

Load Resistance ( )

OFFSET VOLTAGE vs TIME FROM POWER UP

(G = 100)

INPUT BIAS CURRENT vs SUPPLY

2.60

20

Input Bias Current (A)

Change In VOSI (V)

2.55
10

10

2.50
2.45
2.40
2.35
2.30
2.25

20
0

Time (min)

15

20

Power Supply Voltage (V)

INA103

10

25

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25C, VS = 15V, unless otherwise noted.

SMALL SIGNAL TRANSIENT RESPONSE

(G = 1)

INPUT BIAS CURRENT vs TEMPERATURE

Output Voltage (V)

1
55

50

100

Time (s)

125

Temperature (C)

SMALL SIGNAL TRANSIENT RESPONSE

(G = 100)

LARGE SIGNAL TRANSIENT RESPONSE

(G = 1)

Output Voltage (V)

Output Voltage (V)

Time (s)

Time (s)

SETTLING TIME vs GAIN

(0.1%, 20V STEP)

LARGE SIGNAL TRANSIENT RESPONSE

(G = 100)

10

Settling Time (s)

Output Voltage (V)

Input Bias Current (A)

0
1

Time (s)

10

100

1000

Gain

INA103

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25C, VS = 15V, unless otherwise noted.

SETTLING TIME vs GAIN

(0.01%, 20V STEP)

SMALL-SIGNAL FREQUENCY RESPONSE

10

70
60
40

G = 100

30
Gain (dB)

Settling Time (s)

G = 1000

50

20

G = 10

10
0
10

G=1

20

30
40

50
1

10

100

1000

10

100

1k

10k

Gain

NOISE VOLTAGE (RTI) vs FREQUENCY

10M

CMR vs FREQUENCY

100

Common-Mode Rejection (dB)

Noise (RTI) (nV/ Hz)

1M

140

1k

G=1

G = 10

10

G = 500 G = 1000

G = 100

120

G=

100

100

G=

80

G=

60

G=

40

G=

500

100
10

20
0

1
10

100

1k

10k

10

100

1k

10k

100k

Frequency (Hz)

Frequency (Hz)

THD + N vs FREQUENCY

V+ POWER SUPPLY REJECTION

vs FREQUENCY

1M

140

120

G = 100
G = 10

100

G=1

Power Supply Rejection (dB)

VOUT = +18dBu
0.1
THD + N (%)

100k

Frequency (Hz)

G = 1000

0.010

G=1
0.001

G = 100
G = 10

0.0001

G = 1000

80
60
40
20
0

10

100

1k

10k 20k

Frequency (Hz)

100

1k
Frequency (Hz)

INA103

10

10k

100k

1M

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25C, VS = 15V, unless otherwise noted.

V POWER SUPPLY REJECTION

vs FREQUENCY

THD + N vs LEVEL
1

G = 100, 1000

f = 1kHz

120
G = 10
100

0.1

G=1

THD + N (%)

Power Supply Rejection (dB)

140

80
60

0.010

40

G=1

20

0.001
0

0.0005
1

10

100

1k

10k

100k

1M

60

45

30

Frequency (Hz)

15

5
G=1
V OUT = 20Vp-p
f = 1kHz

0.01

CCIF IMD (%)

THD + N (%)

CCIF IMD vs AMPLITUDE

THD + N vs LOAD
0.1

0.001

G = 1000

0.1

G = 100

0.010

G=1
G = 10

0.001

0.0001

0.0001

200

400

600

800

60

1k

50

40

RLOAD ( )

30

20

10

10

20

10

20

Output Amplitude (dBu)

CCIF IMD vs FREQUENCY

SMPTE IMD vs AMPLITUDE

1
SMPTE IMD (%)

CCIF IMD (%)

15

Output Amplitude (dBu)

0.1
G = 1000
0.010

G = 1000
0.1

G = 100

G=1

0.010

G = 100
0.001

G = 10
G=1
2k

G = 10

0.001
0.0005

0.0001
10k

20k

60

Frequency (Hz)

50

40

30

20

10

Output Amplitude (dBu)

INA103

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25C, VS = 15V unless, otherwise noted.

CURRENT NOISE SPECTRAL DENSITY

SMPTE IMD vs FREQUENCY

100
Current Noise Density (pA/ Hz)

SMPTE IMD (%)

0.1

G = 1000

0.010

G = 100
G=1
G = 10

0.001
0.0005

10

1
2k

10k

20k

10

100

1k

10k

Frequency (Hz)

Frequency (Hz)

APPLICATIONS INFORMATION
useful if various input sources are connected to the INA103.
Although not shown in other figures, this network can be
used, if needed, with all applications shown.

Figure 1 shows the basic connections required for operation.

Power supplies should be bypassed with 1F tantalum
capacitors near the device pins. The output Sense (pin 11)
and output Reference (pin 7) should be low impedance
connections. Resistance of a few ohms in series with these
connections will degrade the common-mode rejection of the
amplifier.
To avoid oscillations, make short, direct connection to the
gain set resistor and gain sense connections. Avoid running
output signals near these sensitive input nodes.

GAIN SELECTION
Gains of 1 or 100V/V can be set without external resistors.
For G = 1V/V (unity gain) leave pin 14 open (no connection)see Figure 4. For G = 100V/V, connect pin 14 to pin
6see Figure 5.
Gain can also be accurately set with a single external resistor
as shown in Figure 1. The two internal feedback resistors are
laser-trimmed to 3k within approximately 0.1%. The
temperature coefficient of these resistors is approximately
50ppm/C. Gain using an external RG resistor is
6k
G=1+
RG

INPUT CONSIDERATIONS
Certain source impedances can cause the INA103 to oscillate. This depends on circuit layout and source or cable
characteristics connected to the input. An input network
consisting of a small inductor and resistor (Figure 2) can
greatly reduce the tendancy to oscillate. This is especially

INA103

V+
1F Tantalum
+

50

9
16

16
1.2H

15

V IN RG
+

13
11

INA103

14

VO = G VIN

10

11
INA103

7
6

RL

VOUT

2
1.2H

1
8

V
NOTES: (1) No RG required for G = 1.
See gain-set connections in Figure 4.
(2) RG for G = 100 is internal. See
gain-set connection in Figure 5.

GAIN

GAIN (dB)

RG ()

1
3.16
10
31.6
100
316
1000

0
10
20
30
40
50
60

Note 1
2774
667
196
60.6(2)
19
6

50

FIGURE 2. Input Stabilization Network.

Offset voltage can be trimmed with the optional circuit
shown in Figure 3. This offset trim circuit primarily adjusts
the output stage offset, but also has a small effect on input
stage offset. For a 1mV adjustment of the output voltage, the
input stage offset is adjusted approximately 1V. Use this
adjustment to null the INA103s offset voltage with zero
differential input voltage. Do not use this adjustment to null
offset produced by a sensor, or offset produced by subsequent stages, since this will increase temperature drift.

FIGURE 1. Basic Circuit Configuration.

Accuracy and TCR of the external RG will also contribute to
gain error and temperature drift. These effects can be directly inferred from the gain equation.
Connections available on A1 and A2 allow external resistors
to be substituted for the internal 3k feedback resistors. A
precision resistor network can be used for very accurate and
stable gains. To preserve the low noise of the INA103, the
value of external feedback resistors should be kept low.
Increasing the feedback resistors to 20k would increase
noise of the INA103 to approximately 1.5nV/Hz. Due to
the current-feedback input circuitry, bandwidth would also
be reduced.

To offset the output voltage without affecting drift, use the

circuit shown in Figure 4. The voltage applied to pin 7 is
summed at the output. The op amp connected as a buffer
provides a low impedance at pin 7 to assure good commonmode rejection.
Figure 5 shows a method to trim offset voltage in ACcoupled applications. A nearly constant and equal input bias
current of approximately 2.5A flows into both input terminals. A variable input trim voltage is created by adjusting the
balance of the two input bias return resistances through
which the input bias currents must flow.

NOISE PERFORMANCE
The INA103 provides very low noise with low source
impedance. Its 1nV/Hz voltage noise delivers near theoretical noise performance with a source impedance of 200.
Relatively high input stage current is used to achieve this
low noise. This results in relatively high input bias current
and input current noise. As a result, the INA103 may not
provide best noise performance with source impedances
greater than 10k. For source impedance greater than 10k,
consider the INA114 (excellent for precise DC applications), or the INA111 FET-input IA for high speed applications.

10k
16

6k
G = 1 +
RG

15

13
V IN RG

OFFSET ADJUSTMENT
Offset voltage of the INA103 has two components: input
stage offset voltage is produced by A1 and A2; and, output
stage offset is produced by A3. Both input and output stage
offset are laser trimmed and may not need adjustment in
many applications.

14

11 10

INA103

VOUT

6
2
1

Offset Adjust
Range = 250mV. RTI

FIGURE 3. Offset Adjustment Circuit.

INA103

OUTPUT SENSE
An output sense terminal allows greater gain accuracy in
driving the load. By connecting the sense connection at the
load, IR voltage loss to the load is included inside the
feedback loop. Current drive can be increased by connecting a current booster inside the feedback loop as shown in
Figure 11.

Figure 6 shows an active control loop that adjusts the output

offset voltage to zero. A2, R, and C form an integrator that
produces an offsetting voltage applied to one input of the
INA103. This produces a 6dB/octave low frequency rolloff like the capacitor input coupling in Figure 5.
COMMON-MODE INPUT RANGE
For proper operation, the combined differential input signal
and common-mode input voltage must not cause the input
amplifiers to exceed their output swing limits. The linear
input range is shown in the typical performance curve
Maximum Common-Mode Voltage vs Output Voltage.
For a given total gain, the input common-mode range can be
increased by reducing the input stage gain and increasing the
output stage gain with the circuit shown in Figure 7.

IB IB+ 2.5A

16

Gain = 1V/V
(0dB)

15

In

13
11

INA103

VIN 14

IB

VOUT

10

Gain = 100V/V
(40dB)

16
15

11

13

V+

10

INA103

14

7
100A(1)

VOUT

OPA27

IB +

150

10k
+In
(1)
50k

150

Offset Adjustment
Range = 15mV

50k

100A(1)

100k

FIGURE 4. Output Offsetting.

(1)

NOTE: (1) 50k R, 100k pot is

max recommended value. Use
smaller values in this ratio if possible.

FIGURE 5. Input Offset Adjustment for AC-Coupled Inputs.

Gain = 100V/V
(40dB)

16
In

15

10

INA103

14
6

C
1F

1
(1)

100k

(1)

10k
A2

2k

1/2 OPA1013

NOTE: (1) 100k is max recommended

value. Use smaller value if possible.

FIGURE 6. Automatic DC Restoration.

10

VOUT
R
100k

2
+In

f3dB =

11

13

INA103

(1)

NOTE: (1) 1/2 REF200

100k

Gain
12 RC

RF

16
R1

15

16

13
11

INA103

VIN 14

R2

15

10

VOUT

V IN RG

11 10

INA103

14

R3

12

13

VOUT

6
5

2
G = 1+

Output Stage Gain =

OUTPUT STAGE
GAIN

R1 and R3
(k)

R2
()

2
5
10

1k
1.2k
1.2k

2.4k
632
273

(R2 || 12k) + R1 + R3
(R2 || 12k)

2RF
RG

RF
RF > 10k can increase noise and reduce bandwidthsee text.
NOTE: AD625 equivalent pinout.

FIGURE 7. Gain Adjustment of Output Stage.

FIGURE 8. Use of External Resistors for Gain Set.

(b) INA103 G = 1, VIN = 15V, RL = 600

(a) AD625 G = 1, VIN = 15V, RL = 600

A common problem with many IC op amps and instrumentation amplifiers is shown in (a). Here, the amplifiers input is driven beyond its linear common-mode
range, forcing the output of the amplifier into the supply rails. The output then folds back, i.e., a more positive input voltage now causes the output of the amplifier
to go negative. The INA103 has protection circuitry to prevent fold-back, and as shown in (b), limits cleanly.

FIGURE 9. INA103 Overload Condition Performance.

Gain = 1V/V
(0dB)

16

V+

10

15

16
15

13
VIN 14

11

INA103

10

13

V IN RG

14
6

20

MJ15011

CMR
Trim

2
1

Introduces
approximately
+0.2% Gain Error.

11
10

INA103

100
VOUT
(To headphone
or speaker)

7
MJ15012
Buffer inside feedback loop

FIGURE 10. Optional Circuit for Externally Trimming CMR.

FIGURE 11. Increasing Output Circuit Drive.

11

INA103

47F/63V
16
+
6.8k

+48V

15

2.2k

20dB
Pad

1
Phantom
Power
240

cm 3
2
6.8k

10
Gain
Adjust

47k

13
1k

11 10

INA103

14

V OUT

7
6

100k
1F

2
47F/63V
1
+

2.2k

20dB
Pad

OPA627

240
Output offset voltage
control loop.

FIGURE 12. Microphone Preamplifier with Provision for Phantom Power Microphones.

16
15
10k

12

13
INA103

14

V IN

10k
11

10

VOUT

7
6
10k

10k

5
2
1

100

+
Shield driver minimizes degradation of CMR due
to distributed capacitance on the input lines.

OPA602

FIGURE 13. Instrumentation Amplifier with Shield Driver.

16
OPA627

15
13

11

V IN

2
1
Gain = 100V/V
(40dB)

OPA627

FIGURE 14. Gain-of-100 INA103 with FET Buffers.

INA103

10

INA103

14

12

V OUT = 100 V IN

IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TIs standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customers applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TIs publication of information regarding any third
partys products or services does not constitute TIs approval, warranty or endorsement thereof.

Copyright 2000, Texas Instruments Incorporated

This datasheet has been download from:

www.datasheetcatalog.com
Datasheets for electronics components.

Texas Instruments
http://www.ti.com

This file is the datasheet for the following electronic components:

INA103 - http://www.ti.com/product/ina103?HQS=TI-null-null-dscatalog-df-pf-null-wwe