Comparison of Various 2.

4GHz LNA Topologies

Designed in 0.35m austriamicrosystems technology

Alena Djugova, Jelena Radic, Mirjana Videnovic-Misic

Department of Power, Electronics and Communications Engineering
Faculty of Technical Sciences, University of Novi Sad
Novi Sad, Serbia
alenad@uns.ac.rs, jelenar_@uns.ac.rs, mirjam@uns.ac.rs
AbstractIn this paper two 2.4GHz low noise amplifier (LNA)
configurations in austriamicrosystems 0.35m SiGe BiCMOS
technology are presented. Drawbacks and advantages of
amplifiers in terms of their Figures of Merit (FOMs) and power
consumption (PD) are showed. A current reuse LNA has voltage
gain (S21) of 23.9dB, noise figure of 2.73dB and input/output
return loss of 17.9dB/14.6dB, while consuming 4.9mA from
3.3V supply. A cascade two-stage LNA achieves 24dB of voltage
gain, 2.98dB of noise figure and input/output return loss of
15.5dB/21.8dB, consuming 4.6mA from the 3.3V supply. Both
amplifiers offer high circuit stability parameters.
Keywords-low noise amplifier (LNA), current reuse technique,
power consumption (PD), S-parameters, noise figure (NF),
stability

I.

INTRODUCTION

A low noise amplifier (LNA) is one of the basic building

blocks in the typical wireless receivers. Therefore, it must meet
stringent design requirements. An LNA needs to provide
enough gain to amplify received weak signal to overcome the
noise of the subsequent stages [1]. At the same time, circuit
power consumption (PD) has to be minimized, without adding
too much noise and distortion.
To achieve these goals two narrowband two-stage LNA
topologies, current reuse and cascade, were designed in
austriamicrosystems ( ) 0.35m SiGe BiCMOS technology
at Bluetooth 2.4GHz frequency. The emphasis of this work was
to minimize LNA power consumption and improve (voltage)
gain while still maintaining acceptable noise performance, high
stability and good input and output matching. Used
technology is low-cost but suffers from limited number of lowQ inductors. Consequently, it is difficult to make the trade-off
between PD and others LNA Figures of Merit (FOMs).
Compared to other LNA topologies designed at 2.4GHz in the
same
technology [2, 3, 4], architectures presented in this
paper show smaller PD with higher S21 parameter.
In this paper, current reuse and cascade LNA topologies are
presented in Section II. Simulated FOMs for both LNA designs
are given in Section III followed by discussion of achieved
trade-offs and advantages of each topology. The Section IV
concludes the paper.

II.

CURRENT REUSE AND CASCADE LNA TOPOGIES

The schematics of the current reuse and cascade LNA are

shown in Fig.1 and Fig.2, respectively. It can be seen that both
topologies have two same amplifying stages where the first one
is typical cascode amplifier. The second stage is commonsource amplifier introduced into the designs in two different
manners cascode in Fig.1 or cascade in Fig.2 architecture.
Therefore, the same methodology was used for bias and input
circuit design.
The LNA bias circuit is composed of resistors Rref, Rbias and
transistor M4, where transistor M4 forms current mirror with
M1. To decrease the overall PD, transistor M4 width, W4,
should be small fraction of transistor M1 width, W1. The value
of Rbias is chosen large enough to provide high impedance path
to RF signal while giving at the same time small contribution to
the circuit noise.
In order to provide maximum power transfer at 2.4GHz
both LNA architectures are input matched using inductive
source degeneration (Ls in the schematics). The source
degenerated LNA first order input impedance Zin (ignoring Cgd)
is equal to:
1
g
Z in = j Ls + Lg +
+ m Ls ,
(1)
jC gs C gs

where Cgs is total gate-source capacitance and gm is

transconductance of the input RF transistor M1. At resonant
frequency 0, where imaginary parts cancel, input impedance
becomes:
g
imag (Z in ) | = 0 Z in = m Ls = T Ls .
(2)
0
C
gs

In case of the perfect input LNA match with source

degeneration inductor Ls, input impedance Zin = T Ls is equal
to source resistance Rs = 50. As this input matching method
do not use additional noisy components (resistors) lower noise
figure (NF) is expected. Moreover, the major NF contributors
are parasitic resistances associated to low-Q integrated spiral
inductors.

Figure 2. Two-stage cascade architecture

III.
Figure 1. Two-stage current reuse architecture

An additional degree of freedom is provided by the gate

inductance Lg that is used to set the resonance frequency 0
given by:

C gs C g 2
0 = (Lg + Ls )
.
C gs + C g

(3)

Capacitors Cg and Cb are input and output DC blocking

capacitors. Their values are chosen large so they do not
influence the resonant frequency of the input and output circuit,
respectively. The resonant circuit (L, Cd, Cb, Rmix) at the output
of both architectures has the same topology and defines the
output resonant frequency:

0 out

=
L (Cbp + Cd )

[ (

)] ,

where Cbp = Cb Q 2 Q 2 + 1

1
2

(4)

Q = (0out Cb Rmix )

Resistor Rmix value is equal to 100 = 2Rs, which is the input

impedance of an LNA consecutive stage the differential
mixer. The input and output resonant frequencies are usually
set equal to each other to provide higher gain and narrow
bandwidth operation. However, they can be offset to yield
flatter and broader response.
In current reuse topology, shown in Fig.1, Vbias is applied to
the gate of transistor M2 as the bias voltage while the high
value capacitor C1 provides ideal ac ground to source of
transistor M3. The capacitor C2 is large enough to enable
coupling of two cascoded amplifier stages. Inductors L1 and L2
in parallel represent the load of the first stage and play the same
role as inductor Ld in the second LNA topology.
In the cascade topology, shown in Fig.2, additional degrees
of freedom, with components R and C, are introduced. The
resistor R role is to decrease second stage power consumption
while the capacitor C is introduced with the aim to reduce
resistor R influence on S21 parameter.

SIMULATION RESULTS AND DISCUSSION

The designed circuits have been simulated using Spectre

Simulator from Cadence Design System at 2.4GHz operating
frequency. Initial device dimensions and component values in
SiGe 0.35m BiCMOS four-metal technology were
obtained using the optimization technique with constant power
consumption [5]. In order to get simulation results as close as
BSIM3V3 models for all
possible to measurement results,
circuit components were introduced. Due to increased
complexity of the circuit it was necessary to carefully examine
dependence of the LNA FOMs on circuit parameters. This has
been carried out by changing values of one by one circuit
parameter analyzing at the same time the LNA performance
behavior for both topologies. Though chosen technology has
thick top metal and inductors with the highest performance
within 0.35m
technologies number of inductors is very
limited and their quality factor significantly contributes to NF.
Moreover, to obtain good input matching (S11 < 10dB [6, 7])
and high voltage gain (S21) the low inductor Ls value is needed.
As the minimum available inductor value is 1.07nH, the
-model
was
obtained
from
inductor
Ls=0.7nH
Microelectronics group specialized in inductor modelling [8] in
the same 0.35m SiGe BiCMOS technology.
Both LNA topologies were optimized with the main aim to
minimize PD, improve voltage gain while still keeping
acceptable values for remaining FOMs [6, 7]. Simulation
results for the current reuse LNA topology FOMs are given in
Fig. 35 (S11 and S22, S12 and S21, NF and NFmin) while for the
cascade topology FOMs are showed in Fig. 68 (S11 and S22,
S12 and S21, NF and NFmin). The current reuse design shows
higher power dissipation equal to 4.98mA at Vdd = 3.3V. For
the second LNA topology power consumption is 4.6mA at the
same voltage supply. This result is in contradiction with
common belief where current reuse technique has potential to
obtain lower circuit dissipation. The possible causes of this
unexpected LNA power behaviour could be limited number of
inductors values, the key circuit design parameters, and higher
component coupling through parasitics. Power dissipation in
current reuse LNA could be reduced with Rref increase or W1
decrease or W4 increase. To obtain optimum values for PD, S11
and S21 all three techniques have to be used to overcome
inductor number limitation.

Figure 3. The current reuse LNA input (S11) and output (S22) return loss

Figure 6. The cascade LNA input (S11) and output (S22) return loss

Figure 4. The current reuse LNA input-output isolation (S12) and voltage
gain (S21)

Figure 7. The cascade LNA input-output isolation (S12) and voltage gain
(S21)

Figure 5. The current reuse LNA noise figure (NF) and minimum noise
figure (NFmin)

Figure 8. The cascade LNA noise figure (NF) and minimum noise figure
(NFmin)

The cascade LNA topology has managed to achieve lower

power dissipation with increase in Rref and R values. As a
result, NF is higher (2.98dB) compared to its counterpart
(2.73dB). Additional contribution to the high LNA cascade
NF could be attributed to selected
Lg inductor with low
Q=5.5 value and specific position at the input of the LNA.
From (3) can be seen that resonant frequency 0 at the input
can be dominantly adjusted with Lg and Cgs. The change of Lg
value from 12.08nH to 19.06nH shifted S11 minimum position
closer to 2.4GHz, but significantly deteriorated NF (around

11%) due to lower 19.06nH Q factor. Input matching could be

achieved with Cgs (W1) increase which resulted in higher
power dissipation and better S21. As the aim of presented LNA
design is to obtain simultaneously low power dissipation and
high S21, the first approach for input matching is chosen.
Additional S21 improvement is achieved with large Ld inductor
value. Better S11 value at 2.4GHz could not be achieved due to
limited number of inductors, while S22 value minimum could
not be set to 2.4GHz due to higher power consumption and
trade-off between S22 and S21.

TABLE I.

SIMULATION RESULTS OF DESIGNED LNAS AND OTHER WORKS

0.35m

technology

This work, Fig.1

This work, Fig.2

[2]

[3]

[4]

f0 [GHz]

2.4

2.4

2.4

2.4

2.4

S11 [dB]

17.9

15.5

20

na

32

S21 [dB]

23.9

24

11

20

20.6

S22 [dB]

14.6

21.8

10

na

14

NF [dB]

2.73

2.98

1.7

0.9

3.7

Power consumption (PD)

4.9mA@3.3V

4.6mA@3.3V

5mA@3.3V

14mA@3.3V

11mA@3V

Topology

Two stage

Two stage

One stage

One stage

Two stage

Technology

BiCMOS
(S35D4)

BiCMOS
(S35D4)

CMOS
(C35B3)

CMOS
(C35B3)

CMOS
(C35B4)

Stability parameters simulations were performed from

1GHz to 4GHz. For whole simulated range presented LNA
topologies satisfy unconditional stability requirements, where
Rollet stability factor Kf >1 and alternate stability factor B1f >0
[9]. At 2.4GHz for current reuse topology Kf=5.894 and
B1f=0.978 while for cascade topology Kf =4.889 and B1f =1.01.
The optimized FOMs for current reuse and cascade LNAs
together with FOMs values for similar LNA topologies in
0.35m technology [2, 3, 4] are summarized in Table I. In
comparison with LNAs found in literature [2, 3, 4], designs
presented in this paper show smaller power consumption and
S22 and higher S21. It can be seen, from Table I, that LNAs [2,
technology which in comparison
3] are designed in CMOS
BiCMOS offers higher versatility of inductors values
with
at a price of lower Q factor. To avoid influence of inductors
low Q factor on source degenerated single stage LNA
parameter NF, authors [2] have used a variable off-chip
inductor (Lg), a bondwire (Ls) and an ASITIC designed
integrated inductor. As a result S11 = 20dB and NF = 1.7dB
are better than for topologies presented in this paper. The
source degenerated LNA design, presented in [3], has the best
NF = 0.9dB value and significant S21 = 20dB at a price of the
highest power consumption. The LNA topology given in [4]
has exceptional S11 = 32dB value. As this topology is not
source degenerated its input match is achieved through
coupling with load inductors.
Design tricks, applied in [3, 4] could be used to improve
some FOMs in current reuse and cascade LNA architectures.
IV.

CONCLUSION

The cascade LNA is more flexible than current reuse

topology for PD minimization due to lower parasitic
components influence. In first topology some decoupling
techniques could be applied (to tune-off parasitic capacitances)
to gain better design flexibility. However, the occupied area
could be significantly larger due to additional inductors and
capacitances resulting in higher manufacturing cost. The main
problem, especially during S-parameters and NF adjustments,
is lack of sufficient number of integrated inductors. That

indirectly results in higher PD. This problem could be

overcome with the use of ASITIC or other similar tools for
inductor design. However, as inductance Ls should be
extremely small and Lg very high, it is difficult to see what
program could reliably design those inductors.
ACKNOWLEDGMENT
This research was supported by the Serbian Ministry of
Science and Technological Development (contract TR-11023
and TR-11006) and FP6-INCO project (contract number
043669). The authors wish to express their gratitude to IUMA
inductors group, University of Las Palmas de Gran Canaria
(Spain), for providing necessary inductor models.
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